271 	sys_write32(val, RM_COMM_REG(pd, RM_COMM_CONTROL));  in rm_cfg_start()
275 	sys_write32(val, RM_COMM_REG(pd, RM_COMM_CONTROL));  in rm_cfg_start()
278 	sys_write32(RM_COMM_MSI_DISABLE_VAL,  in rm_cfg_start()
283 	sys_write32(val, RM_COMM_REG(pd, RM_COMM_CONTROL));  in rm_cfg_start()
286 	sys_write32(RM_COMM_AE_TIMEOUT_VAL, RM_COMM_REG(pd,  in rm_cfg_start()
290 	sys_write32(val, RM_COMM_REG(pd, RM_COMM_CONTROL));  in rm_cfg_start()
295 	sys_write32(val, RM_COMM_REG(pd, RM_AE0_AE_CONTROL));  in rm_cfg_start()
297 	sys_write32(val, RM_COMM_REG(pd, RM_AE0_AE_CONTROL));  in rm_cfg_start()
302 	sys_write32(val, RM_COMM_REG(pd, RM_COMM_AXI_CONTROL));  in rm_cfg_start()
305 	sys_write32(RM_COMM_TIMER_CONTROL0_VAL,  in rm_cfg_start()
307 	sys_write32(RM_COMM_TIMER_CONTROL1_VAL,  in rm_cfg_start()
309 	sys_write32(RM_COMM_RM_BURST_LENGTH,  in rm_cfg_start()
315 	sys_write32(val, RM_COMM_REG(pd, RM_COMM_MASK_SEQUENCE_MAX_COUNT));  in rm_cfg_start()
340 	sys_write32(val,  RM_COMM_REG(pd, RM_COMM_CONTROL));  in rm_cfg_finish()
358 	sys_write32(val, RM_RING_REG(pd, idx, RING_CONTROL));  in set_ring_active()
374 	sys_write32(0x0, RM_RING_REG(pd, idx, RING_CONTROL));  in init_ring()
377 	sys_write32(RING_CONTROL_FLUSH, RM_RING_REG(pd, idx, RING_CONTROL));  in init_ring()
393 	sys_write32(0x0, RM_RING_REG(pd, idx, RING_CONTROL));  in init_ring()
398 	sys_write32(val, RM_COMM_REG(pd, RM_COMM_CTRL_REG(idx)));  in init_ring()
405 	sys_write32(val, RM_RING_REG(pd, idx, RING_CMPL_WR_PTR_DDR_CONTROL));  in init_ring()
408 	sys_write32(val, RM_RING_REG(pd, idx, RING_BD_START_ADDR));  in init_ring()
410 	sys_write32(val, RM_RING_REG(pd, idx, RING_CMPL_START_ADDR));  in init_ring()
563 	sys_write32(status, RM_COMM_REG(pd,  in rm_isr()
569 	sys_write32(err_stat,  in rm_isr()
574 	sys_write32(err_stat,  in rm_isr()
715 	sys_write32(val, RM_RING_REG(pd, idx,  in set_pkt_count()