187 	sys_write32(reg_val, reg_base + XUARTPS_CR_OFFSET);  in xlnx_ps_disable_uart()
211 	sys_write32(reg_val, reg_base + XUARTPS_CR_OFFSET);  in xlnx_ps_enable_uart()
268 		sys_write32(divisor, reg_base + XUARTPS_BAUDDIV_OFFSET);  in set_baudrate()
269 		sys_write32(generator, reg_base + XUARTPS_BAUDGEN_OFFSET);  in set_baudrate()
309 	sys_write32(reg_val, reg_base + XUARTPS_MR_OFFSET);  in uart_xlnx_ps_init()
312 	sys_write32(0x01U, reg_base + XUARTPS_RXWM_OFFSET);  in uart_xlnx_ps_init()
315 	sys_write32(XUARTPS_IXR_MASK, reg_base + XUARTPS_IDR_OFFSET);  in uart_xlnx_ps_init()
323 	sys_write32(XUARTPS_IXR_MASK, reg_base + XUARTPS_ISR_OFFSET);  in uart_xlnx_ps_init()
380 	sys_write32((uint32_t)(c & 0xFF), reg_base + XUARTPS_FIFO_OFFSET);  in uart_xlnx_ps_poll_out()
634 	sys_write32(mode_reg,    reg_base + XUARTPS_MR_OFFSET);  in uart_xlnx_ps_configure()
635 	sys_write32(modemcr_reg, reg_base + XUARTPS_MODEMCR_OFFSET);  in uart_xlnx_ps_configure()
848 	sys_write32(XUARTPS_IXR_TXEMPTY, reg_base + XUARTPS_IDR_OFFSET);  in uart_xlnx_ps_fifo_fill()
852 		sys_write32((uint32_t)tx_data[data_iter++], reg_base + XUARTPS_FIFO_OFFSET);  in uart_xlnx_ps_fifo_fill()
854 	sys_write32(XUARTPS_IXR_TXEMPTY, reg_base + XUARTPS_IER_OFFSET);  in uart_xlnx_ps_fifo_fill()
894 	sys_write32(  in uart_xlnx_ps_irq_tx_enable()
908 	sys_write32(  in uart_xlnx_ps_irq_tx_disable()
960 	sys_write32(XUARTPS_IXR_RTRIG, reg_base + XUARTPS_IER_OFFSET);  in uart_xlnx_ps_irq_rx_enable()
972 	sys_write32(XUARTPS_IXR_RTRIG, reg_base + XUARTPS_IDR_OFFSET);  in uart_xlnx_ps_irq_rx_disable()
990 		sys_write32(XUARTPS_IXR_RTRIG, reg_base + XUARTPS_ISR_OFFSET);  in uart_xlnx_ps_irq_rx_ready()
1004 	sys_write32(  in uart_xlnx_ps_irq_err_enable()
1024 	sys_write32(  in uart_xlnx_ps_irq_err_disable()