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Searched refs:sys_read32 (Results 51 – 75 of 196) sorted by relevance

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/Zephyr-latest/drivers/dai/intel/ssp/
Dssp.c122 sys_write32((sys_read32(dest) & (~mask)) | (val & mask), dest); in dai_ssp_update_bits()
247 mdivc = sys_read32(dai_mn_base(dp) + MN_MDIVCTRL); in dai_ssp_setup_initial_mclk_source()
297 mdivc = sys_read32(dai_mn_base(dp) + MN_MDIVCTRL); in dai_ssp_check_current_mclk_source()
394 mdivc = sys_read32(dai_mn_base(dp) + MN_MDIVCTRL); in dai_ssp_mn_release_mclk()
402 mdivc = sys_read32(dai_mn_base(dp) + MN_MDIVCTRL); in dai_ssp_mn_release_mclk()
587 mdivc = sys_read32(dai_mn_base(dp) + MN_MDIVCTRL); in dai_ssp_setup_initial_bclk_mn_source()
616 mdivc = sys_read32(dai_mn_base(dp) + MN_MDIVCTRL); in dai_ssp_reset_bclk_mn_source()
745 if (!WAIT_FOR((sys_read32(reg) & mask) == val, us, k_busy_wait(1))) { in dai_ssp_poll_for_register_delay()
759 shim_reg = sys_read32(dai_shim_base(dp) + SHIM_CLKCTL) | in dai_ssp_pm_runtime_dis_ssp_clk_gating()
777 shim_reg = sys_read32(dai_shim_base(dp) + SHIM_CLKCTL) & in dai_ssp_pm_runtime_en_ssp_clk_gating()
[all …]
/Zephyr-latest/soc/nordic/nrf54h/
Dsoc.c91 .vsup = sys_read32(FICR_ADDR_GET(HSFLL_NODE, vsup)), in trim_hsfll()
92 .coarse = sys_read32(FICR_ADDR_GET(HSFLL_NODE, coarse)), in trim_hsfll()
93 .fine = sys_read32(FICR_ADDR_GET(HSFLL_NODE, fine)) in trim_hsfll()
/Zephyr-latest/drivers/serial/
Duart_efinix_sapphire.c43 while ((sys_read32(UART0_STATUS_REG_ADDR) & BSP_UART_WRITE_AVAILABILITY_MASK) == 0) { in uart_efinix_sapphire_poll_out()
52 if ((sys_read32(UART0_STATUS_REG_ADDR) & BSP_UART_READ_OCCUPANCY_MASK) != 0) { in uart_efinix_sapphire_poll_in()
Duart_pl011_ambiq.h177 sys_write32((sys_read32(addr) | DT_INST_PHA(n, ambiq_pwrcfg, mask)), addr); \
178 while (!(sys_read32(pwr_status_addr) & HCPA_MASK)) { \
195 sys_write32((sys_read32(addr) | DT_INST_PHA(n, ambiq_pwrcfg, mask)), addr); \
196 while ((sys_read32(pwr_status_addr) & DT_INST_PHA(n, ambiq_pwrcfg, mask)) != \
Duart_altera.c160 status = sys_read32(config->base + ALTERA_AVALON_UART_STATUS_REG_OFFSET); in uart_altera_poll_in()
163 *p_char = sys_read32(config->base + ALTERA_AVALON_UART_RXDATA_REG_OFFSET); in uart_altera_poll_in()
191 status = sys_read32(config->base + ALTERA_AVALON_UART_STATUS_REG_OFFSET); in uart_altera_poll_out()
257 data->status_act = sys_read32(config->base + ALTERA_AVALON_UART_STATUS_REG_OFFSET); in uart_altera_err_check()
418 data->status_act = sys_read32(config->base + ALTERA_AVALON_UART_STATUS_REG_OFFSET); in uart_altera_fifo_fill()
465 *rx_data = sys_read32(config->base + ALTERA_AVALON_UART_RXDATA_REG_OFFSET); in uart_altera_fifo_read()
469 data->status_act = sys_read32(config->base + ALTERA_AVALON_UART_STATUS_REG_OFFSET); in uart_altera_fifo_read()
476 data->status_act = sys_read32(config->base + ALTERA_AVALON_UART_STATUS_REG_OFFSET); in uart_altera_fifo_read()
679 data->status_act = sys_read32(config->base + ALTERA_AVALON_UART_STATUS_REG_OFFSET); in uart_altera_irq_update()
804 data->status_act = sys_read32(config->base + ALTERA_AVALON_UART_STATUS_REG_OFFSET); in uart_altera_isr()
[all …]
Duart_intel_lw.c155 status = sys_read32(config->base + INTEL_LW_UART_STATUS_REG_OFFSET); in uart_intel_lw_poll_in()
158 *p_char = sys_read32(config->base + INTEL_LW_UART_RXDATA_REG_OFFSET); in uart_intel_lw_poll_in()
204 status = sys_read32(config->base + INTEL_LW_UART_STATUS_REG_OFFSET); in uart_intel_lw_poll_out()
217 status = sys_read32(config->base + INTEL_LW_UART_STATUS_REG_OFFSET); in uart_intel_lw_poll_out()
292 data->status_act = sys_read32(config->base + INTEL_LW_UART_STATUS_REG_OFFSET); in uart_intel_lw_err_check()
461 data->status_act = sys_read32(config->base in uart_intel_lw_fifo_fill()
503 rx_data[ret_val++] = sys_read32(config->base + in uart_intel_lw_fifo_read()
505 data->status_act = sys_read32(config->base in uart_intel_lw_fifo_read()
701 data->status_act = sys_read32(config->base + INTEL_LW_UART_STATUS_REG_OFFSET); in uart_intel_lw_irq_update()
820 data->status_act = sys_read32(config->base + INTEL_LW_UART_STATUS_REG_OFFSET); in uart_intel_lw_isr()
[all …]
/Zephyr-latest/drivers/ethernet/
Deth_cyclonev.c158 return EMAC_DMA_MODE_SWR_GET(sys_read32(EMAC_DMAGRP_BUS_MODE_ADDR(p->base_addr))); in eth_cyclonev_get_software_reset_status()
332 reg_val = sys_read32(EMAC_GMACGRP_MAC_FRAME_FILTER_ADDR(p->base_addr)); in eth_cyclonev_set_config()
508 sys_read32( in eth_cyclonev_send()
511 sys_read32( in eth_cyclonev_send()
515 if (sys_read32(EMAC_DMAGRP_STATUS_ADDR(p->base_addr)) & in eth_cyclonev_send()
555 sys_read32(EMAC_DMAGRP_STATUS_ADDR(p->base_addr)) & p->interrupt_mask; in eth_cyclonev_isr()
556 irq_status_emac = sys_read32(EMAC_GMAC_INT_STAT_ADDR(p->base_addr)); in eth_cyclonev_isr()
582 uint32_t regval = sys_read32(GMACGRP_CONTROL_STATUS_ADDR(p->base_addr)); in eth_cyclonev_isr()
615 cfg_reg_set = sys_read32(GMACGRP_MAC_CONFIG_ADDR(p->base_addr)); in eth_cyclonev_isr()
884 p->feature = sys_read32(EMAC_DMA_HW_FEATURE_ADDR(p->base_addr)); in eth_cyclonev_probe()
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Deth_xlnx_gem.c201 reg_val = sys_read32(dev_conf->base_addr + in DT_INST_FOREACH_STATUS_OKAY()
276 reg_val = sys_read32(dev_conf->base_addr + ETH_XLNX_GEM_ISR_OFFSET); in eth_xlnx_gem_isr()
452 reg_val = sys_read32(reg_ctrl) & (ETH_XLNX_GEM_TXBD_WRAP_BIT | in eth_xlnx_gem_send()
485 reg_val = sys_read32(reg_ctrl); in eth_xlnx_gem_send()
491 reg_val = sys_read32(dev_conf->base_addr + ETH_XLNX_GEM_NWCTRL_OFFSET); in eth_xlnx_gem_send()
546 reg_val = sys_read32(dev_conf->base_addr + ETH_XLNX_GEM_NWCTRL_OFFSET); in eth_xlnx_gem_start_device()
590 reg_val = sys_read32(dev_conf->base_addr + ETH_XLNX_GEM_NWCTRL_OFFSET); in eth_xlnx_gem_stop_device()
852 clk_ctrl_reg = sys_read32(dev_conf->clk_ctrl_reg_address); in eth_xlnx_gem_configure_clocks()
868 tmp = sys_read32(ETH_XLNX_CRL_APB_WPROT_REGISTER_ADDRESS); in eth_xlnx_gem_configure_clocks()
878 clk_ctrl_reg = sys_read32(dev_conf->clk_ctrl_reg_address); in eth_xlnx_gem_configure_clocks()
[all …]
Deth_stellaris.c145 reg_val = sys_read32(REG_MACDATA); in eth_stellaris_rx_pkt()
169 reg_val = sys_read32(REG_MACDATA); in eth_stellaris_rx_pkt()
180 reg_val = sys_read32(REG_MACDATA); in eth_stellaris_rx_pkt()
235 int isr_val = sys_read32(REG_MACRIS); in eth_stellaris_isr()
251 num_packets = sys_read32(REG_MACNP); in eth_stellaris_isr()
Deth_dwmac_stm32h7x.c76 reg_val = sys_read32(reg_addr); in dwmac_bus_init()
81 reg_val = sys_read32(reg_addr); in dwmac_bus_init()
/Zephyr-latest/soc/espressif/esp32s3/
Dsoc.h32 sys_write32(sys_read32(mem_addr) | v, mem_addr); in esp32_set_mask32()
37 sys_write32(sys_read32(mem_addr) & ~v, mem_addr); in esp32_clear_mask32()
/Zephyr-latest/soc/litex/litex_vexriscv/
Dsoc.h45 return sys_read32(addr); in litex_read32()
63 return ((uint64_t)sys_read32(addr) << 32) | (uint64_t)sys_read32(addr + 0x4); in litex_read64()
/Zephyr-latest/drivers/pinctrl/renesas/rcar/
Dpfc_rcar.c80 uint32_t val = sys_read32(pfc_base + PFC_RCAR_GPSR + in pfc_rcar_set_gpsr()
96 uint32_t val = sys_read32(pfc_base + reg_offs); in pfc_rcar_set_ipsr()
148 val = sys_read32(pfc_base + reg); in pfc_rcar_set_drive_strength()
187 val = sys_read32(pfc_base + bias_reg->puen); in pfc_rcar_set_bias()
195 val = sys_read32(pfc_base + bias_reg->pud); in pfc_rcar_set_bias()
285 val = sys_read32(pfc_base + voltage_reg->offset); in pfc_rcar_set_voltage()
/Zephyr-latest/drivers/flash/
Dflash_cadence_qspi_nor_ll.c23 return (sys_read32(cad_params->reg_base + CAD_QSPI_CFG) & CAD_QSPI_CFG_IDLE) >> 31; in cad_qspi_idle()
102 uint32_t cfg = sys_read32(cad_params->reg_base + CAD_QSPI_CFG); in cad_qspi_timing_config()
126 sys_write32((sys_read32(cad_params->reg_base + CAD_QSPI_CFG) & CAD_QSPI_CFG_CS_MSK) | in cad_qspi_stig_cmd_helper()
134 uint32_t reg = sys_read32(cad_params->reg_base + CAD_QSPI_FLASHCMD); in cad_qspi_stig_cmd_helper()
196 output[0] = sys_read32(cad_params->reg_base + CAD_QSPI_FLASHCMD_RDDATA0); in cad_qspi_stig_read_cmd()
199 output[1] = sys_read32(cad_params->reg_base + CAD_QSPI_FLASHCMD_RDDATA1); in cad_qspi_stig_read_cmd()
723 CAD_QSPI_SRAMPART_ADDR(sys_read32(cad_params->reg_base + CAD_QSPI_SRAMPART)); in cad_qspi_indirect_page_bound_write()
728 sys_read32(cad_params->reg_base + CAD_QSPI_SRAMFILL)); in cad_qspi_indirect_page_bound_write()
762 sys_read32(cad_params->reg_base + CAD_QSPI_SRAMFILL)); in cad_qspi_read_bank()
765 *read_data++ = sys_read32(cad_params->data_base); in cad_qspi_read_bank()
[all …]
Dflash_cadence_nand_ll.c19 if (!WAIT_FOR(CNF_GET_CTRL_BUSY(sys_read32(CNF_CMDREG(base_address, CTRL_STATUS))) == 0U, in cdns_nand_wait_idle()
65 reg_value = sys_read32(CNF_CTRLPARAM(base_address, VERSION)); in cdns_nand_device_info()
74 reg_value = sys_read32(CNF_CTRLPARAM(base_address, DEV_PARAMS0)); in cdns_nand_device_info()
85 reg_value = sys_read32(CNF_CTRLCFG(base_address, DEV_LAYOUT)); in cdns_nand_device_info()
89 reg_value = sys_read32(CNF_CTRLPARAM(base_address, DEV_AREA)); in cdns_nand_device_info()
94 params->nblocks_per_lun = sys_read32(CNF_CTRLPARAM(base_address, DEV_BLOCKS_PLUN)); in cdns_nand_device_info()
121 status = sys_read32((base_address + CMD_STAT_CMD_STATUS)); in cdns_nand_get_thrd_status()
135 if (!WAIT_FOR((sys_read32((base_address) + THR_STATUS) & BIT(thread)) == 0U, in cdns_wait_for_thread()
225 sys_read32(CNF_CTRLPARAM(base_address, ONFI_TIMING_0))); in cdns_nand_set_opr_mode()
248 sys_read32(CNF_CTRLPARAM(base_address, ONFI_TIMING_0))); in cdns_nand_set_opr_mode()
[all …]
/Zephyr-latest/drivers/mdio/
Dmdio_dwcxgmac.c65 ret = WAIT_FOR(!(sys_read32(reg_addr) & DMA_MODE_SWR_SET_MSK), delay_us, k_msleep(1)); in dwxgmac_software_reset()
78 ret = WAIT_FOR(!(sys_read32(reg_addr) & bit_msk), delay_us, k_msleep(1)); in mdio_busy_wait()
108 reg_data = sys_read32(reg_addr); in mdio_transfer()
134 sys_read32(reg_addr)); in mdio_transfer()
/Zephyr-latest/drivers/dai/intel/alh/
Dalh.c82 sys_write32(sys_read32(ALHASCTL) | ALHASCTL_OSEL(0x3), ALHASCTL); in alh_claim_ownership()
83 sys_write32(sys_read32(ALHCSCTL) | ALHASCTL_OSEL(0x3), ALHCSCTL); in alh_claim_ownership()
97 sys_write32(sys_read32(ALHASCTL) | ALHASCTL_OSEL(0), ALHASCTL); in alh_release_ownership()
98 sys_write32(sys_read32(ALHCSCTL) | ALHASCTL_OSEL(0), ALHCSCTL); in alh_release_ownership()
/Zephyr-latest/drivers/gpio/
Dgpio_intel.c197 val = sys_read32(regs(dev) + offset); in check_perm()
209 val = sys_read32(regs(dev) + offset); in check_perm()
239 int_sts = sys_read32(reg); in gpio_intel_isr()
276 cfg0 = sys_read32(reg); in gpio_intel_config()
277 cfg1 = sys_read32(reg + 4); in gpio_intel_config()
358 cfg0 = sys_read32(reg); in gpio_intel_pin_interrupt_configure()
359 cfg1 = sys_read32(reg + 4); in gpio_intel_pin_interrupt_configure()
460 reg_val = sys_read32(reg_addr); in port_get_raw()
492 reg_val = sys_read32(reg_addr); in port_set_raw()
Dgpio_efinix_sapphire.c60 uint32_t c_reg_val = sys_read32(GPIO_OUTPUT_ENABLE_ADDR); in cfg_output_enable_bit()
73 uint32_t c_reg_val = sys_read32(GPIO_OUTPUT_ADDR); in cfg_output_bit()
122 uint32_t c_reg_val = sys_read32(GPIO_OUTPUT_ADDR); in get_port()
/Zephyr-latest/soc/lowrisc/opentitan/
Dsoc.c36 while (sys_read32(PWRMGR_BASE + PWRMGR_CFG_CDC_SYNC_REG_OFFSET)) { in soc_early_init_hook()
/Zephyr-latest/drivers/pcie/endpoint/
Dpcie_ep_iproc.c235 data = sys_read32(CRMU_MCU_EXTRA_EVENT_STATUS); in iproc_pcie_perst()
256 data = sys_read32(CRMU_MCU_EXTRA_EVENT_STATUS); in iproc_pcie_hot_reset()
315 data = sys_read32(PCIE_PERSTB_INTR_CTL_STS); in iproc_pcie_reset_config()
319 data = sys_read32(CRMU_MCU_EXTRA_EVENT_MASK); in iproc_pcie_reset_config()
334 data = sys_read32(PCIE_PERSTB_INTR_CTL_STS); in iproc_pcie_reset_config()
338 data = sys_read32(CRMU_MCU_EXTRA_EVENT_MASK); in iproc_pcie_reset_config()
397 data = sys_read32(PMON_LITE_PCIE_AXI_FILTER_0_CONTROL); in iproc_pcie_msix_pvm_config()
/Zephyr-latest/soc/nxp/imx/imx8ulp/adsp/include/adsp/
Dio.h17 return sys_read32(reg); in io_reg_read()
/Zephyr-latest/soc/nxp/imx/imx8x/adsp/include/adsp/
Dio.h17 return sys_read32(reg); in io_reg_read()
/Zephyr-latest/soc/nxp/imx/imx8/adsp/include/adsp/
Dio.h17 return sys_read32(reg); in io_reg_read()
/Zephyr-latest/soc/nxp/imx/imx8m/adsp/include/adsp/
Dio.h17 return sys_read32(reg); in io_reg_read()

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