1 /*
2  * Copyright (c) 2023 Rivos Inc.
3  *
4  * SPDX-License-Identifier: Apache-2.0
5  */
6 
7 #include <zephyr/arch/cpu.h>
8 #include <zephyr/devicetree.h>
9 #include <zephyr/init.h>
10 
11 /* OpenTitan power management regs. */
12 #define PWRMGR_BASE (DT_REG_ADDR(DT_NODELABEL(pwrmgr)))
13 #define PWRMGR_CFG_CDC_SYNC_REG_OFFSET  0x018
14 #define PWRMGR_RESET_EN_REG_OFFSET      0x02c
15 #define PWRMGR_RESET_EN_WDOG_SRC_MASK   0x002
16 
17 /* Ibex timer registers. */
18 #define RV_TIMER_BASE (DT_REG_ADDR(DT_NODELABEL(mtimer)))
19 #define RV_TIMER_CTRL_REG_OFFSET        0x004
20 #define RV_TIMER_INTR_ENABLE_REG_OFFSET 0x100
21 #define RV_TIMER_CFG0_REG_OFFSET        0x10c
22 #define RV_TIMER_CFG0_PRESCALE_MASK     0xfff
23 #define RV_TIMER_CFG0_PRESCALE_OFFSET   0
24 #define RV_TIMER_CFG0_STEP_MASK         0xff
25 #define RV_TIMER_CFG0_STEP_OFFSET       16
26 #define RV_TIMER_LOWER0_OFFSET          0x110
27 #define RV_TIMER_COMPARE_LOWER0_OFFSET  0x118
28 
soc_early_init_hook(void)29 void soc_early_init_hook(void)
30 {
31 	/* Enable the watchdog reset (bit 1). */
32 	sys_write32(2u, PWRMGR_BASE + PWRMGR_RESET_EN_REG_OFFSET);
33 	/* Write CFG_CDC_SYNC to commit change. */
34 	sys_write32(1u, PWRMGR_BASE + PWRMGR_CFG_CDC_SYNC_REG_OFFSET);
35 	/* Poll CFG_CDC_SYNC register until it reads 0. */
36 	while (sys_read32(PWRMGR_BASE + PWRMGR_CFG_CDC_SYNC_REG_OFFSET)) {
37 	}
38 
39 	/* Initialize the Machine Timer, so it behaves as a regular one. */
40 	sys_write32(1u, RV_TIMER_BASE + RV_TIMER_CTRL_REG_OFFSET);
41 	/* Enable timer interrupts. */
42 	sys_write32(1u, RV_TIMER_BASE + RV_TIMER_INTR_ENABLE_REG_OFFSET);
43 }
44