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/Zephyr-latest/lib/posix/options/
DKconfig.timer7 bool "POSIX timers, clocks, and sleep functions"
DCMakeLists.txt94 sleep.c
DKconfig.profile15 imply POSIX_MULTI_PROCESS # sleep(), getpid(), etc
/Zephyr-latest/boards/microchip/mec172xmodular_assy6930/
Dmec172xmodular_assy6930.dts211 pinctrl-names = "default", "sleep";
/Zephyr-latest/boards/nordic/nrf9160dk/
Dnrf9160dk_nrf52840.dts172 pinctrl-names = "default", "sleep";
/Zephyr-latest/boards/st/nucleo_wl55jc/doc/
Dnucleo_wl55jc.rst302 sleep mode. Unfortunately, default openocd configuration, which is debug
303 compatible, doesn't allow flashing when SoC is in sleep mode.
305 please update board's openocd.cfg configuration file to select sleep mode
/Zephyr-latest/boards/ti/cc1352p7_launchpad/doc/
Dindex.rst217 sleep state 2 (standby mode) is allowed, and polling is used to retrieve input
221 disable sleep state 2 while polling:
/Zephyr-latest/drivers/ieee802154/
DKconfig93 Enable support for CSL debugging by avoiding sleep state in favor of receive state.
/Zephyr-latest/scripts/net/
Drun-sample-tests.sh169 sleep 3
/Zephyr-latest/subsys/logging/frontends/
DKconfig56 Before going to sleep CPU shall write to STM some dummy data to ensure
/Zephyr-latest/boards/renesas/da14695_dk_usb/doc/
Dindex.rst24 the sleep clock is 32768 Hz. The frequency of the system clock is 32 MHz.
/Zephyr-latest/tests/posix/headers/src/
Dunistd_h.c280 zassert_not_null(sleep); in ZTEST()
/Zephyr-latest/boards/ti/cc1352r_sensortag/doc/
Dindex.rst234 sleep state 2 (standby mode) is allowed, and polling is used to retrieve input
238 disable sleep state 2 while polling:
/Zephyr-latest/doc/services/pm/
Ddevice.rst86 from a sleep state, devices are resumed in the opposite order that they were
297 When the system is idle and the SoC is going to sleep, the power management
394 * sleep state would be suitable but constraints will
403 Some devices are capable of waking the system up from a sleep state.
/Zephyr-latest/dts/arm/nxp/
Dnxp_rt5xx_common.dtsi48 /* This is the setting for Deep-sleep Mode */
58 * during deep sleep mode.
60 deep-sleep-config = <0xC800>,
/Zephyr-latest/boards/seagate/faze/doc/
Dindex.rst90 | PIO0_20 | GPIO | USB sleep |
/Zephyr-latest/boards/renesas/da1469x_dk_pro/doc/
Dindex.rst25 the sleep clock is 32768 Hz. The frequency of the system clock is 32 MHz.
/Zephyr-latest/boards/waveshare/rp2040_zero/doc/
Dindex.rst16 - Low-power sleep and dormant modes.
/Zephyr-latest/samples/modules/canopennode/
DREADME.rst196 time.sleep(5)
200 time.sleep(5)
204 time.sleep(5)
/Zephyr-latest/tests/kernel/context/
DREADME.txt98 thread back from sleep
/Zephyr-latest/boards/beagle/beagleconnect_freedom/
Dbeagleconnect_freedom.dts149 pinctrl-names = "default", "sleep";
/Zephyr-latest/drivers/console/
DKconfig77 allowed to enter sleep/deep sleep state and turn off the clock of UART
/Zephyr-latest/subsys/logging/
DKconfig.processing73 int "Set internal log processing thread sleep period"
/Zephyr-latest/scripts/pylib/pytest-twister-harness/src/twister_harness/device/
Dhardware_adapter.py237 time.sleep(0.05)
/Zephyr-latest/boards/ti/msp_exp432p401r_launchxl/doc/
Dindex.rst27 * The on-board 32-kHz crystal allows for lower LPM3 sleep currents and a higher-precision clock sou…

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