| /Zephyr-latest/drivers/adc/ |
| D | adc_sam_afec.c | 65 Afec *regs; member
75 Afec *const afec = cfg->regs; in adc_sam_channel_setup()
127 Afec *const afec = cfg->regs; in adc_sam_start_conversion()
270 Afec *const afec = cfg->regs; in adc_sam_init()
346 Afec *const afec = cfg->regs; in adc_sam_isr()
371 .regs = (Afec *)DT_INST_REG_ADDR(n), \
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| /Zephyr-latest/tests/drivers/ipm/src/ |
| D | ipm_dummy.h | 28 volatile struct ipm_dummy_regs regs; member
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| /Zephyr-latest/drivers/pinctrl/ |
| D | pinctrl_sam.c | 63 soc_pin.regs = (Gpio *) sam_port_addrs[port_idx]; in pinctrl_configure_pin()
65 soc_pin.regs = (Pio *) sam_port_addrs[port_idx]; in pinctrl_configure_pin()
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| /Zephyr-latest/drivers/pcie/host/ |
| D | vc.h | 121 uint32_t pcie_vc_cap_lookup(pcie_bdf_t bdf, struct pcie_vc_regs *regs);
125 struct pcie_vc_resource_regs *regs,
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| /Zephyr-latest/drivers/ethernet/ |
| D | phy_gecko.h | 19 ETH_TypeDef *regs; member
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| D | eth_gecko.c | 70 ETH_TypeDef *eth = cfg->regs; in eth_gecko_setup_mac()
142 ETH_TypeDef *eth = cfg->regs; in frame_get()
268 ETH_TypeDef *eth = cfg->regs; in eth_tx()
375 ETH_TypeDef *eth = cfg->regs; in eth_isr()
434 ETH_TypeDef *eth = cfg->regs; in eth_init_pins()
470 ETH_TypeDef *eth = cfg->regs; in eth_init()
513 ETH_TypeDef *eth = cfg->regs; in eth_iface_init()
658 .regs = (ETH_TypeDef *)
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| /Zephyr-latest/tests/drivers/sensor/ina230/src/ |
| D | ina230_emul.c | 35 struct ina230_reg *regs; member
40 struct ina230_reg *c_reg = data->regs; in get_register()
184 .regs = (struct ina230_reg *)ina23##v##_regs_##n, \
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| /Zephyr-latest/drivers/i2c/ |
| D | i2c_max32_rtio.c | 34 mxc_i2c_regs_t *regs; member
72 mxc_i2c_regs_t *i2c = cfg->regs; in max32_do_configure()
111 mxc_i2c_regs_t *i2c = cfg->regs; in max32_msg_start()
308 if (cfg->regs->clkhi == I2C_STANDAR_BITRATE_CLKHI) { in max32_complete()
343 mxc_i2c_regs_t *i2c = cfg->regs; in i2c_max32_isr()
355 mxc_i2c_regs_t *i2c = cfg->regs; in i2c_max32_init()
422 .regs = (mxc_i2c_regs_t *)DT_INST_REG_ADDR(_num), \
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| D | i2c_max32.c | 38 mxc_i2c_regs_t *regs; member
75 mxc_i2c_regs_t *i2c = cfg->regs; in api_configure()
111 mxc_i2c_regs_t *i2c = config->regs; in api_target_register()
130 mxc_i2c_regs_t *i2c = config->regs; in api_target_unregister()
196 mxc_i2c_regs_t *i2c = cfg->regs; in api_recover_bus()
297 Wrap_MXC_I2C_Restart(cfg->regs); in i2c_max32_dma_callback()
299 Wrap_MXC_I2C_Stop(cfg->regs); in i2c_max32_dma_callback()
368 mxc_i2c_regs_t *i2c = cfg->regs; in i2c_max32_transfer_dma()
435 mxc_i2c_regs_t *i2c = cfg->regs; in i2c_max32_transfer()
528 mxc_i2c_regs_t *i2c = cfg->regs; in i2c_max32_transfer()
[all …]
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| D | i2c_sam4l_twim.c | 67 Twim *regs; member
110 Twim *const twim = cfg->regs; in i2c_clk_set()
288 Twim *const twim = cfg->regs; in i2c_start_xfer()
421 Twim *const twim = cfg->regs; in i2c_sam_twim_isr()
539 Twim *const twim = cfg->regs; in i2c_sam_twim_initialize()
620 .regs = (Twim *)DT_INST_REG_ADDR(n), \
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| /Zephyr-latest/samples/drivers/espi/src/ |
| D | main.c | 423 static int pr_check_range(struct mchp_espi_saf *regs, const struct espi_saf_pr *pr) in pr_check_range() argument
430 if (regs->SAF_PROT_RG[pr->pr_num].START != (pr->start >> 12)) { in pr_check_range()
434 if (regs->SAF_PROT_RG[pr->pr_num].LIMIT != (limit >> 12)) { in pr_check_range()
441 static int pr_check_enable(struct mchp_espi_saf *regs, const struct espi_saf_pr *pr) in pr_check_enable() argument
444 if (regs->SAF_PROT_RG[pr->pr_num].LIMIT > regs->SAF_PROT_RG[pr->pr_num].START) { in pr_check_enable()
448 if (regs->SAF_PROT_RG[pr->pr_num].START > regs->SAF_PROT_RG[pr->pr_num].LIMIT) { in pr_check_enable()
456 static int pr_check_lock(struct mchp_espi_saf *regs, const struct espi_saf_pr *pr) in pr_check_lock() argument
459 if (regs->SAF_PROT_LOCK & BIT(pr->pr_num)) { in pr_check_lock()
463 if (!(regs->SAF_PROT_LOCK & BIT(pr->pr_num))) { in pr_check_lock()
474 static int pr_check_master_bm(struct mchp_espi_saf *regs, const struct espi_saf_pr *pr) in pr_check_master_bm() argument
[all …]
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| /Zephyr-latest/tests/drivers/counter/counter_nrf_rtc/fixed_top/src/ |
| D | test_counter_fixed_top.c | 33 static NRF_RTC_Type *const regs[] = { variable
96 NRF_RTC_Type *reg = regs[idx]; in test_top_handler_on_instance()
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| /Zephyr-latest/dts/arm/st/f3/ |
| D | stm32f302X8.dtsi | 25 st,backup-regs = <20>;
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| /Zephyr-latest/dts/arm/st/l1/ |
| D | stm32l151Xb-a.dtsi | 28 st,backup-regs = <5>;
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| D | stm32l151Xb.dtsi | 28 st,backup-regs = <20>;
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| /Zephyr-latest/scripts/dts/ |
| D | gen_dts_cmake.py | 143 if node.regs is not None:
148 for reg in node.regs:
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| /Zephyr-latest/tests/arch/arm/arm_thread_swap/src/ |
| D | arm_thread_arch.c | 61 static void load_callee_saved_regs(const _callee_saved_t *regs) in load_callee_saved_regs() argument
78 : "r" (regs) in load_callee_saved_regs()
87 : "r" (regs) in load_callee_saved_regs()
145 const volatile struct _preempt_float *regs) in load_fp_callee_saved_regs() argument
150 : "r" (regs) in load_fp_callee_saved_regs()
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| /Zephyr-latest/drivers/sensor/maxim/max17262/ |
| D | max17262.c | 186 } regs[] = { in max17262_sample_fetch() local
203 for (size_t i = 0; i < ARRAY_SIZE(regs); i++) { in max17262_sample_fetch()
206 rc = max17262_reg_read(dev, regs[i].reg_addr, regs[i].dest); in max17262_sample_fetch()
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| /Zephyr-latest/arch/arc/core/ |
| D | thread.c | 128 _callee_saved_stack_t *regs = UINT_TO_POINTER(stack_ptr); in arch_setup_callee_saved_regs() local
130 ARG_UNUSED(regs); in arch_setup_callee_saved_regs()
140 regs->TLSREG = thread->tls; in arch_setup_callee_saved_regs()
143 regs->r30 = thread->tls; in arch_setup_callee_saved_regs()
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| /Zephyr-latest/scripts/kconfig/ |
| D | kconfigfunctions.py | 171 if not node.regs:
174 if int(index) >= len(node.regs):
177 if node.regs[int(index)].addr is None:
180 return node.regs[int(index)].addr >> _dt_units_to_scale(unit)
187 if not node.regs:
190 if int(index) >= len(node.regs):
193 if node.regs[int(index)].size is None:
196 return node.regs[int(index)].size >> _dt_units_to_scale(unit)
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| /Zephyr-latest/drivers/watchdog/ |
| D | wdt_sifive.c | 54 uintptr_t regs; member
65 ((const struct wdt_sifive_device_config *const)(dev)->config)->regs)
282 .regs = DT_INST_REG_ADDR(0),
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| /Zephyr-latest/include/zephyr/arch/xtensa/ |
| D | gdbstub.h | 92 struct xtensa_register *regs; member
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| /Zephyr-latest/dts/arm/st/l4/ |
| D | stm32l4r5.dtsi | 31 st,backup-regs = <32>;
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| /Zephyr-latest/drivers/i2s/ |
| D | i2s_sam_ssc.c | 71 Ssc *regs; member
211 Ssc *const ssc = dev_cfg->regs; in dma_rx_callback()
271 Ssc *const ssc = dev_cfg->regs; in dma_tx_callback()
328 Ssc *const ssc = dev_cfg->regs; in set_rx_data_format()
421 Ssc *const ssc = dev_cfg->regs; in set_tx_data_format()
554 Ssc *const ssc = dev_cfg->regs; in i2s_sam_configure()
789 Ssc *const ssc = dev_cfg->regs; in i2s_sam_trigger()
930 Ssc *const ssc = dev_cfg->regs; in i2s_sam_isr()
956 Ssc *const ssc = dev_cfg->regs; in i2s_sam_initialize()
1018 .regs = (Ssc *)DT_INST_REG_ADDR(0),
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| /Zephyr-latest/drivers/flash/ |
| D | flash_stm32_qspi.c | 93 QUADSPI_TypeDef *regs; member
226 LOG_DBG("CCR 0x%x", dev_cfg->regs->CCR); in qspi_send_cmd()
303 LOG_DBG("CCR 0x%x", dev_cfg->regs->CCR); in qspi_write_access()
1011 uint8_t regs[4] = { 0 }; in qspi_write_status_register() local
1023 regs[0] = reg; in qspi_write_status_register()
1024 regs_p = ®s[0]; in qspi_write_status_register()
1027 ret = qspi_read_status_register(dev, 2, ®s[1]); in qspi_write_status_register()
1036 regs[1] = reg; in qspi_write_status_register()
1037 regs_p = ®s[1]; in qspi_write_status_register()
1042 ret = qspi_read_status_register(dev, 1, ®s[0]); in qspi_write_status_register()
[all …]
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