1 /*
2 * Copyright (c) 2024 Analog Devices, Inc.
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #define DT_DRV_COMPAT adi_max32_i2c
8
9 #include <errno.h>
10 #include <zephyr/drivers/i2c.h>
11 #include <zephyr/drivers/pinctrl.h>
12 #include <zephyr/drivers/clock_control/adi_max32_clock_control.h>
13 #include <zephyr/irq.h>
14
15 #if defined(CONFIG_I2C_MAX32_DMA)
16 #include <zephyr/drivers/dma.h>
17 #endif /* CONFIG_I2C_MAX32_DMA */
18
19 #include <wrap_max32_i2c.h>
20
21 #define ADI_MAX32_I2C_INT_FL0_MASK 0x00FFFFFF
22 #define ADI_MAX32_I2C_INT_FL1_MASK 0x7
23
24 #define ADI_MAX32_I2C_STATUS_MASTER_BUSY BIT(5)
25
26 #define I2C_RECOVER_MAX_RETRIES 3
27
28 #ifdef CONFIG_I2C_MAX32_DMA
29 struct max32_i2c_dma_config {
30 const struct device *dev;
31 const uint32_t channel;
32 const uint32_t slot;
33 };
34 #endif /* CONFIG_I2C_MAX32_DMA */
35
36 /* Driver config */
37 struct max32_i2c_config {
38 mxc_i2c_regs_t *regs;
39 const struct pinctrl_dev_config *pctrl;
40 const struct device *clock;
41 struct max32_perclk perclk;
42 uint32_t bitrate;
43 #if defined(CONFIG_I2C_TARGET) || defined(CONFIG_I2C_MAX32_INTERRUPT)
44 uint8_t irqn;
45 void (*irq_config_func)(const struct device *dev);
46 #endif
47 #ifdef CONFIG_I2C_MAX32_DMA
48 struct max32_i2c_dma_config tx_dma;
49 struct max32_i2c_dma_config rx_dma;
50 #endif /* CONFIG_I2C_MAX32_DMA */
51 };
52
53 struct max32_i2c_data {
54 mxc_i2c_req_t req;
55 const struct device *dev;
56 struct k_sem lock;
57 uint8_t target_mode;
58 uint8_t flags;
59 #ifdef CONFIG_I2C_TARGET
60 struct i2c_target_config *target_cfg;
61 bool first_write;
62 #endif /* CONFIG_I2C_TARGET */
63 uint32_t readb;
64 uint32_t written;
65 #if defined(CONFIG_I2C_MAX32_INTERRUPT) || defined(CONFIG_I2C_MAX32_DMA)
66 struct k_sem xfer;
67 int err;
68 #endif
69 };
70
api_configure(const struct device * dev,uint32_t dev_cfg)71 static int api_configure(const struct device *dev, uint32_t dev_cfg)
72 {
73 int ret = 0;
74 const struct max32_i2c_config *const cfg = dev->config;
75 mxc_i2c_regs_t *i2c = cfg->regs;
76
77 switch (I2C_SPEED_GET(dev_cfg)) {
78 case I2C_SPEED_STANDARD: /** I2C Standard Speed: 100 kHz */
79 ret = MXC_I2C_SetFrequency(i2c, MXC_I2C_STD_MODE);
80 break;
81
82 case I2C_SPEED_FAST: /** I2C Fast Speed: 400 kHz */
83 ret = MXC_I2C_SetFrequency(i2c, MXC_I2C_FAST_SPEED);
84 break;
85
86 #if defined(MXC_I2C_FASTPLUS_SPEED)
87 case I2C_SPEED_FAST_PLUS: /** I2C Fast Plus Speed: 1 MHz */
88 ret = MXC_I2C_SetFrequency(i2c, MXC_I2C_FASTPLUS_SPEED);
89 break;
90 #endif
91
92 #if defined(MXC_I2C_HIGH_SPEED)
93 case I2C_SPEED_HIGH: /** I2C High Speed: 3.4 MHz */
94 ret = MXC_I2C_SetFrequency(i2c, MXC_I2C_HIGH_SPEED);
95 break;
96 #endif
97
98 default:
99 /* Speed not supported */
100 return -ENOTSUP;
101 }
102
103 return ret;
104 }
105
106 #ifdef CONFIG_I2C_TARGET
api_target_register(const struct device * dev,struct i2c_target_config * cfg)107 static int api_target_register(const struct device *dev, struct i2c_target_config *cfg)
108 {
109 const struct max32_i2c_config *config = dev->config;
110 struct max32_i2c_data *data = dev->data;
111 mxc_i2c_regs_t *i2c = config->regs;
112 int ret;
113
114 data->target_cfg = cfg;
115
116 ret = MXC_I2C_Init(i2c, 0, cfg->address);
117 if (ret == E_NO_ERROR) {
118 data->target_mode = 1;
119 irq_enable(config->irqn);
120 MXC_I2C_SlaveTransactionAsync(i2c, NULL);
121 }
122
123 return ret == E_NO_ERROR ? 0 : E_FAIL;
124 }
125
api_target_unregister(const struct device * dev,struct i2c_target_config * cfg)126 static int api_target_unregister(const struct device *dev, struct i2c_target_config *cfg)
127 {
128 const struct max32_i2c_config *config = dev->config;
129 struct max32_i2c_data *data = dev->data;
130 mxc_i2c_regs_t *i2c = config->regs;
131
132 data->target_cfg = NULL;
133 data->target_mode = 0;
134
135 #ifndef CONFIG_I2C_MAX32_INTERRUPT
136 irq_disable(config->irqn);
137 #endif
138
139 return MXC_I2C_Init(i2c, 1, 0);
140 }
141
i2c_max32_target_callback(const struct device * dev,mxc_i2c_regs_t * i2c,mxc_i2c_slave_event_t event)142 static int i2c_max32_target_callback(const struct device *dev, mxc_i2c_regs_t *i2c,
143 mxc_i2c_slave_event_t event)
144 {
145 struct max32_i2c_data *data = dev->data;
146 const struct i2c_target_callbacks *target_cb = data->target_cfg->callbacks;
147 static uint8_t rxval, txval, rxcnt;
148
149 switch (event) {
150 case MXC_I2C_EVT_MASTER_WR:
151 if (data->first_write && target_cb->write_requested) {
152 target_cb->write_requested(data->target_cfg);
153 data->first_write = false;
154 }
155 break;
156 case MXC_I2C_EVT_MASTER_RD:
157 break;
158 case MXC_I2C_EVT_RX_THRESH:
159 case MXC_I2C_EVT_OVERFLOW:
160 rxcnt = MXC_I2C_GetRXFIFOAvailable(i2c);
161 if (target_cb->write_received) {
162 while (rxcnt--) {
163 MXC_I2C_ReadRXFIFO(i2c, &rxval, 1);
164 target_cb->write_received(data->target_cfg, rxval);
165 }
166 } else {
167 MXC_I2C_ClearRXFIFO(i2c);
168 }
169 break;
170 case MXC_I2C_EVT_TX_THRESH:
171 case MXC_I2C_EVT_UNDERFLOW:
172 if (target_cb->read_requested) {
173 target_cb->read_requested(data->target_cfg, &txval);
174 MXC_I2C_WriteTXFIFO(i2c, &txval, 1);
175 }
176 if (target_cb->read_processed) {
177 target_cb->read_processed(data->target_cfg, &txval);
178 }
179 break;
180 case MXC_I2C_EVT_TRANS_COMP:
181 if (target_cb->stop) {
182 target_cb->stop(data->target_cfg);
183 }
184 data->first_write = true;
185 break;
186 }
187
188 return 0;
189 }
190 #endif /* CONFIG_I2C_TARGET */
191
api_recover_bus(const struct device * dev)192 static int api_recover_bus(const struct device *dev)
193 {
194 int ret;
195 const struct max32_i2c_config *const cfg = dev->config;
196 mxc_i2c_regs_t *i2c = cfg->regs;
197
198 ret = MXC_I2C_Recover(i2c, I2C_RECOVER_MAX_RETRIES);
199
200 return ret;
201 }
202
203 #ifndef CONFIG_I2C_MAX32_INTERRUPT
i2c_max32_transfer_sync(mxc_i2c_regs_t * i2c,struct max32_i2c_data * data)204 static int i2c_max32_transfer_sync(mxc_i2c_regs_t *i2c, struct max32_i2c_data *data)
205 {
206 uint32_t int_fl0, int_fl1;
207 uint32_t readb = 0;
208 mxc_i2c_req_t *req = &data->req;
209
210 /* Wait for acknowledge */
211 if (data->flags & (I2C_MSG_RESTART | I2C_MSG_READ)) {
212 do {
213 MXC_I2C_GetFlags(i2c, &int_fl0, &int_fl1);
214 } while (!(int_fl0 & ADI_MAX32_I2C_INT_FL0_ADDR_ACK) &&
215 !(int_fl0 & ADI_MAX32_I2C_INT_FL0_ERR));
216 }
217
218 if (int_fl0 & ADI_MAX32_I2C_INT_FL0_ERR) {
219 return -EIO;
220 }
221
222 while (req->tx_len > data->written) {
223 MXC_I2C_GetFlags(i2c, &int_fl0, &int_fl1);
224 if (int_fl0 & ADI_MAX32_I2C_INT_FL0_TX_THD) {
225 data->written += MXC_I2C_WriteTXFIFO(i2c, &req->tx_buf[data->written],
226 req->tx_len - data->written);
227 MXC_I2C_ClearFlags(i2c, ADI_MAX32_I2C_INT_FL0_TX_THD, 0);
228 }
229
230 if (int_fl0 & ADI_MAX32_I2C_INT_FL0_ERR) {
231 return -EIO;
232 }
233 }
234
235 MXC_I2C_ClearFlags(i2c, ADI_MAX32_I2C_INT_FL0_DONE, 0);
236 Wrap_MXC_I2C_SetRxCount(i2c, req->rx_len);
237 while (req->rx_len > readb) {
238 MXC_I2C_GetFlags(i2c, &int_fl0, &int_fl1);
239 if (int_fl0 & (ADI_MAX32_I2C_INT_FL0_RX_THD | ADI_MAX32_I2C_INT_FL0_DONE)) {
240 readb += MXC_I2C_ReadRXFIFO(i2c, &req->rx_buf[readb], req->rx_len - readb);
241 MXC_I2C_ClearFlags(i2c, ADI_MAX32_I2C_INT_FL0_RX_THD, 0);
242 }
243
244 if (int_fl0 & ADI_MAX32_I2C_INT_FL0_ERR) {
245 return -EIO;
246 }
247
248 MXC_I2C_GetFlags(i2c, &int_fl0, &int_fl1);
249 if ((int_fl0 & ADI_MAX32_I2C_INT_FL0_DONE) && (req->rx_len > readb) &&
250 MXC_I2C_GetRXFIFOAvailable(i2c) == 0) {
251 Wrap_MXC_I2C_SetRxCount(i2c, req->rx_len - readb);
252 Wrap_MXC_I2C_Restart(i2c);
253 MXC_I2C_ClearFlags(i2c, ADI_MAX32_I2C_INT_FL0_DONE, 0);
254 i2c->fifo = (req->addr << 1) | 0x1;
255 }
256 }
257
258 MXC_I2C_GetFlags(i2c, &int_fl0, &int_fl1);
259 if (int_fl0 & ADI_MAX32_I2C_INT_FL0_ERR) {
260 return -EIO;
261 }
262
263 if (data->flags & I2C_MSG_STOP) {
264 MXC_I2C_Stop(i2c);
265 do {
266 MXC_I2C_GetFlags(i2c, &int_fl0, &int_fl1);
267 } while (!(int_fl0 & ADI_MAX32_I2C_INT_FL0_STOP));
268 }
269
270 if (req->rx_len) {
271 do {
272 MXC_I2C_GetFlags(i2c, &int_fl0, &int_fl1);
273 } while (!(int_fl0 & ADI_MAX32_I2C_INT_FL0_DONE));
274 } else {
275 while (Wrap_MXC_I2C_GetTxFIFOLevel(i2c) > 0) {
276 MXC_I2C_GetFlags(i2c, &int_fl0, &int_fl1);
277 }
278 }
279 MXC_I2C_ClearFlags(i2c, ADI_MAX32_I2C_INT_FL0_MASK, ADI_MAX32_I2C_INT_FL1_MASK);
280
281 return 0;
282 }
283 #endif /* CONFIG_I2C_MAX32_INTERRUPT */
284
285 #if defined(CONFIG_I2C_MAX32_DMA)
i2c_max32_dma_callback(const struct device * dev,void * arg,uint32_t channel,int status)286 static void i2c_max32_dma_callback(const struct device *dev, void *arg, uint32_t channel,
287 int status)
288 {
289 struct max32_i2c_data *data = arg;
290 const struct device *i2c_dev = data->dev;
291 const struct max32_i2c_config *const cfg = i2c_dev->config;
292
293 if (status < 0) {
294 data->err = -EIO;
295 } else {
296 if (data->req.restart) {
297 Wrap_MXC_I2C_Restart(cfg->regs);
298 } else {
299 Wrap_MXC_I2C_Stop(cfg->regs);
300 }
301 }
302 }
303
i2c_max32_tx_dma_load(const struct device * dev,struct i2c_msg * msg)304 static int i2c_max32_tx_dma_load(const struct device *dev, struct i2c_msg *msg)
305 {
306 int ret;
307 const struct max32_i2c_config *config = dev->config;
308 struct max32_i2c_data *data = dev->data;
309 struct dma_config dma_cfg = {0};
310 struct dma_block_config dma_blk = {0};
311
312 dma_cfg.channel_direction = MEMORY_TO_PERIPHERAL;
313 dma_cfg.dma_callback = i2c_max32_dma_callback;
314 dma_cfg.user_data = (void *)data;
315 dma_cfg.dma_slot = config->tx_dma.slot;
316 dma_cfg.block_count = 1;
317 dma_cfg.source_data_size = 1U;
318 dma_cfg.source_burst_length = 1U;
319 dma_cfg.dest_data_size = 1U;
320 dma_cfg.head_block = &dma_blk;
321 dma_blk.block_size = msg->len;
322 dma_blk.source_addr_adj = DMA_ADDR_ADJ_INCREMENT;
323 dma_blk.source_address = (uint32_t)msg->buf;
324
325 ret = dma_config(config->tx_dma.dev, config->tx_dma.channel, &dma_cfg);
326 if (ret < 0) {
327 return ret;
328 }
329
330 return dma_start(config->tx_dma.dev, config->tx_dma.channel);
331 }
332
i2c_max32_rx_dma_load(const struct device * dev,struct i2c_msg * msg)333 static int i2c_max32_rx_dma_load(const struct device *dev, struct i2c_msg *msg)
334 {
335 int ret;
336 const struct max32_i2c_config *config = dev->config;
337 struct max32_i2c_data *data = dev->data;
338 struct dma_config dma_cfg = {0};
339 struct dma_block_config dma_blk = {0};
340
341 dma_cfg.channel_direction = PERIPHERAL_TO_MEMORY;
342 dma_cfg.dma_callback = i2c_max32_dma_callback;
343 dma_cfg.user_data = (void *)data;
344 dma_cfg.dma_slot = config->rx_dma.slot;
345 dma_cfg.block_count = 1;
346 dma_cfg.source_data_size = 1U;
347 dma_cfg.source_burst_length = 1U;
348 dma_cfg.dest_data_size = 1U;
349 dma_cfg.head_block = &dma_blk;
350 dma_blk.block_size = msg->len;
351 dma_blk.dest_addr_adj = DMA_ADDR_ADJ_INCREMENT;
352 dma_blk.dest_address = (uint32_t)msg->buf;
353
354 ret = dma_config(config->rx_dma.dev, config->rx_dma.channel, &dma_cfg);
355 if (ret < 0) {
356 return ret;
357 }
358
359 return dma_start(config->rx_dma.dev, config->rx_dma.channel);
360 }
361
i2c_max32_transfer_dma(const struct device * dev,struct i2c_msg * msgs,uint8_t num_msgs,uint16_t target_address)362 static int i2c_max32_transfer_dma(const struct device *dev, struct i2c_msg *msgs, uint8_t num_msgs,
363 uint16_t target_address)
364 {
365 int ret = 0;
366 const struct max32_i2c_config *const cfg = dev->config;
367 struct max32_i2c_data *data = dev->data;
368 mxc_i2c_regs_t *i2c = cfg->regs;
369 uint8_t target_rw;
370 unsigned int i = 0;
371
372 k_sem_take(&data->lock, K_FOREVER);
373
374 MXC_I2C_SetRXThreshold(i2c, 1);
375 MXC_I2C_SetTXThreshold(i2c, 2);
376 MXC_I2C_ClearTXFIFO(i2c);
377 MXC_I2C_ClearRXFIFO(i2c);
378
379 for (i = 0; i < num_msgs; i++) {
380 data->req.restart = !(msgs[i].flags & I2C_MSG_STOP);
381 if (msgs[i].flags & I2C_MSG_READ) {
382 target_rw = (target_address << 1) | 0x1;
383 MXC_I2C_WriteTXFIFO(i2c, &target_rw, 1);
384 Wrap_MXC_I2C_SetRxCount(i2c, msgs[i].len);
385 ret = i2c_max32_rx_dma_load(dev, &msgs[i]);
386 if (ret < 0) {
387 break;
388 }
389
390 MXC_I2C_EnableInt(
391 i2c, ADI_MAX32_I2C_INT_EN0_DONE | ADI_MAX32_I2C_INT_EN0_ERR, 0);
392 i2c->dma |= ADI_MAX32_I2C_DMA_RX_EN;
393 } else {
394 target_rw = (target_address << 1) & ~0x1;
395 MXC_I2C_WriteTXFIFO(i2c, &target_rw, 1);
396 ret = i2c_max32_tx_dma_load(dev, &msgs[i]);
397 if (ret < 0) {
398 break;
399 }
400
401 MXC_I2C_EnableInt(
402 i2c, ADI_MAX32_I2C_INT_EN0_DONE | ADI_MAX32_I2C_INT_EN0_ERR, 0);
403 i2c->dma |= ADI_MAX32_I2C_DMA_TX_EN;
404 }
405 data->err = 0;
406
407 Wrap_MXC_I2C_Start(i2c);
408 ret = k_sem_take(&data->xfer, K_FOREVER);
409 Wrap_MXC_I2C_SetIntEn(i2c, 0, 0);
410 i2c->dma &= ~(ADI_MAX32_I2C_DMA_TX_EN | ADI_MAX32_I2C_DMA_RX_EN);
411
412 if (data->err) {
413 ret = data->err;
414 }
415 if (ret) {
416 MXC_I2C_Stop(i2c);
417 dma_stop(cfg->tx_dma.dev, cfg->tx_dma.channel);
418 dma_stop(cfg->rx_dma.dev, cfg->rx_dma.channel);
419 }
420 }
421
422 k_sem_give(&data->lock);
423
424 return ret;
425 }
426 #endif /* CONFIG_I2C_MAX32_DMA */
427
428 #ifdef CONFIG_I2C_MAX32_INTERRUPT
i2c_max32_transfer(const struct device * dev,struct i2c_msg * msgs,uint8_t num_msgs,uint16_t target_address)429 static int i2c_max32_transfer(const struct device *dev, struct i2c_msg *msgs, uint8_t num_msgs,
430 uint16_t target_address)
431 {
432 int ret = 0;
433 const struct max32_i2c_config *const cfg = dev->config;
434 struct max32_i2c_data *data = dev->data;
435 mxc_i2c_regs_t *i2c = cfg->regs;
436 mxc_i2c_req_t *req = &data->req;
437 uint8_t target_rw;
438 unsigned int i = 0;
439
440 req->i2c = i2c;
441 req->addr = target_address;
442
443 k_sem_take(&data->lock, K_FOREVER);
444
445 MXC_I2C_ClearRXFIFO(i2c);
446 MXC_I2C_ClearTXFIFO(i2c);
447 MXC_I2C_SetRXThreshold(i2c, 1);
448
449 /* First message should always begin with a START condition */
450 msgs[0].flags |= I2C_MSG_RESTART;
451
452 for (i = 0; i < num_msgs; i++) {
453 if (msgs[i].flags & I2C_MSG_READ) {
454 req->rx_buf = (unsigned char *)msgs[i].buf;
455 req->rx_len = msgs[i].len;
456 req->tx_buf = NULL;
457 req->tx_len = 0;
458 target_rw = (target_address << 1) | 0x1;
459 } else {
460 req->tx_buf = (unsigned char *)msgs[i].buf;
461 req->tx_len = msgs[i].len;
462 req->rx_buf = NULL;
463 req->rx_len = 0;
464 target_rw = (target_address << 1) & ~0x1;
465 }
466
467 /*
468 * If previous message ends with a STOP condition, this message
469 * should begin with a START
470 */
471 if (i > 0) {
472 if ((msgs[i - 1].flags & (I2C_MSG_STOP | I2C_MSG_READ))) {
473 msgs[i].flags |= I2C_MSG_RESTART;
474 }
475 }
476
477 data->flags = msgs[i].flags;
478 data->readb = 0;
479 data->written = 0;
480 data->err = 0;
481
482 MXC_I2C_ClearFlags(i2c, ADI_MAX32_I2C_INT_FL0_MASK, ADI_MAX32_I2C_INT_FL1_MASK);
483 MXC_I2C_EnableInt(i2c, ADI_MAX32_I2C_INT_EN0_ERR, 0);
484 Wrap_MXC_I2C_SetRxCount(i2c, req->rx_len);
485 if ((data->flags & I2C_MSG_RESTART)) {
486 MXC_I2C_EnableInt(i2c, ADI_MAX32_I2C_INT_EN0_ADDR_ACK, 0);
487 MXC_I2C_Start(i2c);
488 Wrap_MXC_I2C_WaitForRestart(i2c);
489 MXC_I2C_WriteTXFIFO(i2c, &target_rw, 1);
490 } else {
491 if (req->tx_len) {
492 data->written = MXC_I2C_WriteTXFIFO(i2c, req->tx_buf, 1);
493 MXC_I2C_EnableInt(i2c, ADI_MAX32_I2C_INT_EN0_TX_THD, 0);
494 } else {
495 MXC_I2C_EnableInt(i2c, ADI_MAX32_I2C_INT_EN0_RX_THD, 0);
496 }
497 }
498
499 ret = k_sem_take(&data->xfer, K_FOREVER);
500 if (data->err) {
501 MXC_I2C_Stop(i2c);
502 ret = data->err;
503 } else {
504 if (data->flags & I2C_MSG_STOP) {
505 /* Wait for busy flag to be cleared */
506 while (i2c->status & ADI_MAX32_I2C_STATUS_MASTER_BUSY) {
507 }
508 MXC_I2C_ClearFlags(i2c, ADI_MAX32_I2C_INT_FL0_MASK,
509 ADI_MAX32_I2C_INT_FL1_MASK);
510 }
511 }
512 if (ret) {
513 break;
514 }
515 }
516
517 k_sem_give(&data->lock);
518
519 return ret;
520 }
521 #else
i2c_max32_transfer(const struct device * dev,struct i2c_msg * msgs,uint8_t num_msgs,uint16_t target_address)522 static int i2c_max32_transfer(const struct device *dev, struct i2c_msg *msgs, uint8_t num_msgs,
523 uint16_t target_address)
524 {
525 int ret = 0;
526 const struct max32_i2c_config *const cfg = dev->config;
527 struct max32_i2c_data *data = dev->data;
528 mxc_i2c_regs_t *i2c = cfg->regs;
529 mxc_i2c_req_t *req = &data->req;
530 uint8_t target_rw;
531 unsigned int i = 0;
532
533 req->i2c = i2c;
534 req->addr = target_address;
535
536 k_sem_take(&data->lock, K_FOREVER);
537
538 MXC_I2C_ClearRXFIFO(i2c);
539
540 /* First message should always begin with a START condition */
541 msgs[0].flags |= I2C_MSG_RESTART;
542
543 for (i = 0; i < num_msgs; i++) {
544 if (msgs[i].flags & I2C_MSG_READ) {
545 req->rx_buf = (unsigned char *)msgs[i].buf;
546 req->rx_len = msgs[i].len;
547 req->tx_buf = NULL;
548 req->tx_len = 0;
549 target_rw = (target_address << 1) | 0x1;
550 } else {
551 req->tx_buf = (unsigned char *)msgs[i].buf;
552 req->tx_len = msgs[i].len;
553 req->rx_buf = NULL;
554 req->rx_len = 0;
555 target_rw = (target_address << 1) & ~0x1;
556 }
557
558 /*
559 * If previous message ends with a STOP condition, this message
560 * should begin with a START
561 */
562 if (i > 0) {
563 if ((msgs[i - 1].flags & (I2C_MSG_STOP | I2C_MSG_READ))) {
564 msgs[i].flags |= I2C_MSG_RESTART;
565 }
566 }
567
568 data->flags = msgs[i].flags;
569 data->readb = 0;
570 data->written = 0;
571
572 MXC_I2C_ClearFlags(i2c, ADI_MAX32_I2C_INT_FL0_MASK, ADI_MAX32_I2C_INT_FL1_MASK);
573
574 Wrap_MXC_I2C_SetIntEn(i2c, 0, 0);
575 if (data->flags & I2C_MSG_RESTART) {
576 MXC_I2C_Start(i2c);
577 Wrap_MXC_I2C_WaitForRestart(i2c);
578 MXC_I2C_WriteTXFIFO(i2c, &target_rw, 1);
579 }
580 ret = i2c_max32_transfer_sync(i2c, data);
581 if (ret) {
582 MXC_I2C_Stop(i2c);
583 break;
584 }
585 }
586
587 k_sem_give(&data->lock);
588
589 return ret;
590 }
591 #endif /* CONFIG_I2C_MAX32_INTERRUPT */
592
api_transfer(const struct device * dev,struct i2c_msg * msgs,uint8_t num_msgs,uint16_t target_address)593 static int api_transfer(const struct device *dev, struct i2c_msg *msgs, uint8_t num_msgs,
594 uint16_t target_address)
595 {
596 #if CONFIG_I2C_MAX32_DMA
597 const struct max32_i2c_config *cfg = dev->config;
598
599 if ((cfg->tx_dma.channel != 0xFF) && (cfg->rx_dma.channel != 0xFF)) {
600 return i2c_max32_transfer_dma(dev, msgs, num_msgs, target_address);
601 }
602 #endif
603 return i2c_max32_transfer(dev, msgs, num_msgs, target_address);
604 }
605
606 #ifdef CONFIG_I2C_TARGET
i2c_max32_isr_target(const struct device * dev,mxc_i2c_regs_t * i2c)607 static void i2c_max32_isr_target(const struct device *dev, mxc_i2c_regs_t *i2c)
608 {
609 uint32_t ctrl;
610 uint32_t int_fl0;
611 uint32_t int_fl1;
612 uint32_t int_en0;
613 uint32_t int_en1;
614
615 ctrl = i2c->ctrl;
616 Wrap_MXC_I2C_GetIntEn(i2c, &int_en0, &int_en1);
617 MXC_I2C_GetFlags(i2c, &int_fl0, &int_fl1);
618 MXC_I2C_ClearFlags(i2c, ADI_MAX32_I2C_INT_FL0_MASK, ADI_MAX32_I2C_INT_FL1_MASK);
619
620 if (int_fl0 & ADI_MAX32_I2C_INT_FL0_ERR) {
621 /* Error occurred, notify callback function and end transaction */
622 i2c_max32_target_callback(dev, i2c, MXC_I2C_EVT_TRANS_COMP);
623
624 MXC_I2C_ClearFlags(i2c, ADI_MAX32_I2C_INT_FL0_MASK, ADI_MAX32_I2C_INT_FL1_MASK);
625 MXC_I2C_ClearTXFIFO(i2c);
626 MXC_I2C_ClearRXFIFO(i2c);
627 }
628
629 /* Check whether data is available if we received an interrupt occurred while receiving */
630 if (int_en0 & ADI_MAX32_I2C_INT_EN0_RX_THD || int_en1 & ADI_MAX32_I2C_INT_EN1_RX_OVERFLOW) {
631 if (int_fl0 & ADI_MAX32_I2C_INT_FL0_RX_THD) {
632 i2c_max32_target_callback(dev, i2c, MXC_I2C_EVT_RX_THRESH);
633 }
634
635 if (int_fl1 & ADI_MAX32_I2C_INT_FL1_RX_OVERFLOW) {
636 i2c_max32_target_callback(dev, i2c, MXC_I2C_EVT_OVERFLOW);
637 }
638 }
639
640 /* Check whether TX FIFO needs to be refilled if interrupt ocurred while transmitting */
641 if (int_en0 & (ADI_MAX32_I2C_INT_EN0_TX_THD | ADI_MAX32_I2C_INT_EN0_TX_LOCK_OUT) ||
642 int_en1 & ADI_MAX32_I2C_INT_EN1_TX_UNDERFLOW) {
643 if (int_fl0 & ADI_MAX32_I2C_INT_FL0_TX_THD) {
644 i2c_max32_target_callback(dev, i2c, MXC_I2C_EVT_TX_THRESH);
645 }
646
647 if (int_fl1 & ADI_MAX32_I2C_INT_EN1_TX_UNDERFLOW) {
648 i2c_max32_target_callback(dev, i2c, MXC_I2C_EVT_UNDERFLOW);
649 }
650
651 if (int_fl0 & ADI_MAX32_I2C_INT_FL0_TX_LOCK_OUT) {
652 int_en0 = ADI_MAX32_I2C_INT_EN0_ADDR_MATCH;
653 int_en1 = 0;
654 i2c_max32_target_callback(dev, i2c, MXC_I2C_EVT_TRANS_COMP);
655 }
656 }
657
658 /* Check if transaction completed or restart occurred */
659 if (int_en0 & ADI_MAX32_I2C_INT_EN0_DONE) {
660 if (int_fl0 & ADI_MAX32_I2C_INT_FL0_STOP) {
661 /* Stop/NACK condition occurred, transaction complete */
662 i2c_max32_target_callback(dev, i2c, MXC_I2C_EVT_TRANS_COMP);
663 int_en0 = ADI_MAX32_I2C_INT_EN0_ADDR_MATCH;
664 } else if (int_fl0 & ADI_MAX32_I2C_INT_FL0_DONE) {
665 /* Restart detected, re-arm address match interrupt */
666 int_en0 = ADI_MAX32_I2C_INT_EN0_ADDR_MATCH;
667 }
668 int_en1 = 0;
669 }
670
671 /* Check for address match interrupt */
672 if (int_en0 & ADI_MAX32_I2C_INT_EN0_ADDR_MATCH) {
673 if (int_fl0 & ADI_MAX32_I2C_INT_FL0_ADDR_MATCH) {
674 /* Address match occurred, prepare for transaction */
675 if (i2c->ctrl & MXC_F_I2C_CTRL_READ) {
676 /* Read request received from the master */
677 i2c_max32_target_callback(dev, i2c, MXC_I2C_EVT_MASTER_RD);
678 int_en0 = ADI_MAX32_I2C_INT_EN0_TX_THD |
679 ADI_MAX32_I2C_INT_EN0_TX_LOCK_OUT |
680 ADI_MAX32_I2C_INT_EN0_DONE | ADI_MAX32_I2C_INT_EN0_ERR;
681 int_en1 = ADI_MAX32_I2C_INT_EN1_TX_UNDERFLOW;
682 } else {
683 /* Write request received from the master */
684 i2c_max32_target_callback(dev, i2c, MXC_I2C_EVT_MASTER_WR);
685 int_en0 = ADI_MAX32_I2C_INT_EN0_RX_THD |
686 ADI_MAX32_I2C_INT_EN0_DONE | ADI_MAX32_I2C_INT_EN0_ERR;
687 int_en1 = ADI_MAX32_I2C_INT_EN1_RX_OVERFLOW;
688 }
689 }
690 }
691 Wrap_MXC_I2C_SetIntEn(i2c, int_en0, int_en1);
692 }
693 #endif /* CONFIG_I2C_TARGET */
694
695 #ifdef CONFIG_I2C_MAX32_INTERRUPT
i2c_max32_isr_controller(const struct device * dev,mxc_i2c_regs_t * i2c)696 static void i2c_max32_isr_controller(const struct device *dev, mxc_i2c_regs_t *i2c)
697 {
698 struct max32_i2c_data *data = dev->data;
699 mxc_i2c_req_t *req = &data->req;
700 uint32_t written, readb;
701 uint32_t txfifolevel;
702 uint32_t int_fl0, int_fl1;
703 uint32_t int_en0, int_en1;
704
705 written = data->written;
706 readb = data->readb;
707
708 Wrap_MXC_I2C_GetIntEn(i2c, &int_en0, &int_en1);
709 MXC_I2C_GetFlags(i2c, &int_fl0, &int_fl1);
710 MXC_I2C_ClearFlags(i2c, ADI_MAX32_I2C_INT_FL0_MASK, ADI_MAX32_I2C_INT_FL1_MASK);
711 txfifolevel = Wrap_MXC_I2C_GetTxFIFOLevel(i2c);
712
713 if (int_fl0 & ADI_MAX32_I2C_INT_FL0_ERR) {
714 data->err = -EIO;
715 Wrap_MXC_I2C_SetIntEn(i2c, 0, 0);
716 k_sem_give(&data->xfer);
717 return;
718 }
719
720 if (int_fl0 & ADI_MAX32_I2C_INT_FL0_ADDR_ACK) {
721 MXC_I2C_DisableInt(i2c, ADI_MAX32_I2C_INT_EN0_ADDR_ACK, 0);
722 if (written < req->tx_len) {
723 MXC_I2C_EnableInt(i2c, ADI_MAX32_I2C_INT_EN0_TX_THD, 0);
724 } else if (readb < req->rx_len) {
725 MXC_I2C_EnableInt(
726 i2c, ADI_MAX32_I2C_INT_EN0_RX_THD | ADI_MAX32_I2C_INT_EN0_DONE, 0);
727 }
728 }
729
730 if (req->tx_len &&
731 (int_fl0 & (ADI_MAX32_I2C_INT_FL0_TX_THD | ADI_MAX32_I2C_INT_FL0_DONE))) {
732 if (written < req->tx_len) {
733 written += MXC_I2C_WriteTXFIFO(i2c, &req->tx_buf[written],
734 req->tx_len - written);
735 } else {
736 if (!(int_en0 & ADI_MAX32_I2C_INT_EN0_DONE)) {
737 /* We are done, stop sending more data */
738 MXC_I2C_DisableInt(i2c, ADI_MAX32_I2C_INT_EN0_TX_THD, 0);
739 if (data->flags & I2C_MSG_STOP) {
740 MXC_I2C_EnableInt(i2c, ADI_MAX32_I2C_INT_EN0_DONE, 0);
741 /* Done flag is not set if stop/restart is not set */
742 Wrap_MXC_I2C_Stop(i2c);
743 } else {
744 k_sem_give(&data->xfer);
745 }
746 }
747
748 if ((int_fl0 & ADI_MAX32_I2C_INT_FL0_DONE)) {
749 MXC_I2C_DisableInt(i2c, ADI_MAX32_I2C_INT_EN0_DONE, 0);
750 k_sem_give(&data->xfer);
751 }
752 }
753 } else if ((int_fl0 & (ADI_MAX32_I2C_INT_FL0_RX_THD | ADI_MAX32_I2C_INT_FL0_DONE))) {
754 readb += MXC_I2C_ReadRXFIFO(i2c, &req->rx_buf[readb], req->rx_len - readb);
755 if (readb == req->rx_len) {
756 MXC_I2C_DisableInt(i2c, ADI_MAX32_I2C_INT_EN0_RX_THD, 0);
757 if (data->flags & I2C_MSG_STOP) {
758 MXC_I2C_DisableInt(i2c, ADI_MAX32_I2C_INT_EN0_DONE, 0);
759 Wrap_MXC_I2C_Stop(i2c);
760 k_sem_give(&data->xfer);
761 } else {
762 if (int_fl0 & ADI_MAX32_I2C_INT_FL0_DONE) {
763 MXC_I2C_DisableInt(i2c, ADI_MAX32_I2C_INT_EN0_DONE, 0);
764 k_sem_give(&data->xfer);
765 }
766 }
767 } else if ((int_en0 & ADI_MAX32_I2C_INT_EN0_DONE) &&
768 (int_fl0 & ADI_MAX32_I2C_INT_FL0_DONE)) {
769 MXC_I2C_DisableInt(
770 i2c, (ADI_MAX32_I2C_INT_EN0_RX_THD | ADI_MAX32_I2C_INT_EN0_DONE),
771 0);
772 Wrap_MXC_I2C_SetRxCount(i2c, req->rx_len - readb);
773 MXC_I2C_EnableInt(i2c, ADI_MAX32_I2C_INT_EN0_ADDR_ACK, 0);
774 i2c->fifo = (req->addr << 1) | 0x1;
775 Wrap_MXC_I2C_Restart(i2c);
776 }
777 }
778
779 data->written = written;
780 data->readb = readb;
781 }
782 #endif /* CONFIG_I2C_MAX32_INTERRUPT */
783
784 #ifdef CONFIG_I2C_MAX32_DMA
i2c_max32_isr_controller_dma(const struct device * dev,mxc_i2c_regs_t * i2c)785 static void i2c_max32_isr_controller_dma(const struct device *dev, mxc_i2c_regs_t *i2c)
786 {
787 struct max32_i2c_data *data = dev->data;
788 uint32_t int_fl0, int_fl1;
789 uint32_t int_en0, int_en1;
790
791 Wrap_MXC_I2C_GetIntEn(i2c, &int_en0, &int_en1);
792 MXC_I2C_GetFlags(i2c, &int_fl0, &int_fl1);
793 MXC_I2C_ClearFlags(i2c, ADI_MAX32_I2C_INT_FL0_MASK, ADI_MAX32_I2C_INT_FL1_MASK);
794
795 if (int_fl0 & ADI_MAX32_I2C_INT_FL0_ERR) {
796 data->err = -EIO;
797 Wrap_MXC_I2C_SetIntEn(i2c, 0, 0);
798 k_sem_give(&data->xfer);
799 } else {
800 if (!data->err && (int_en0 & ADI_MAX32_I2C_INT_EN0_DONE)) {
801 k_sem_give(&data->xfer);
802 }
803 }
804 }
805 #endif /* CONFIG_I2C_MAX32_DMA */
806
807 #if defined(CONFIG_I2C_TARGET) || defined(CONFIG_I2C_MAX32_INTERRUPT)
i2c_max32_isr(const struct device * dev)808 static void i2c_max32_isr(const struct device *dev)
809 {
810 const struct max32_i2c_config *cfg = dev->config;
811 struct max32_i2c_data *data = dev->data;
812 mxc_i2c_regs_t *i2c = cfg->regs;
813
814 #ifdef CONFIG_I2C_MAX32_INTERRUPT
815 if (data->target_mode == 0) {
816 #ifdef CONFIG_I2C_MAX32_DMA
817 if ((cfg->tx_dma.channel != 0xFF) && (cfg->rx_dma.channel != 0xFF)) {
818 i2c_max32_isr_controller_dma(dev, i2c);
819 return;
820 }
821 #endif
822 i2c_max32_isr_controller(dev, i2c);
823 return;
824 }
825 #endif /* CONFIG_I2C_MAX32_INTERRUPT */
826
827 #ifdef CONFIG_I2C_TARGET
828 if (data->target_mode == 1) {
829 i2c_max32_isr_target(dev, i2c);
830 }
831 #endif
832 }
833 #endif /* CONFIG_I2C_TARGET || CONFIG_I2C_MAX32_INTERRUPT */
834
835 static DEVICE_API(i2c, api) = {
836 .configure = api_configure,
837 .transfer = api_transfer,
838 #ifdef CONFIG_I2C_TARGET
839 .target_register = api_target_register,
840 .target_unregister = api_target_unregister,
841 #endif
842 #ifdef CONFIG_I2C_RTIO
843 .iodev_submit = i2c_iodev_submit_fallback,
844 #endif
845 .recover_bus = api_recover_bus,
846 };
847
i2c_max32_init(const struct device * dev)848 static int i2c_max32_init(const struct device *dev)
849 {
850 const struct max32_i2c_config *const cfg = dev->config;
851 struct max32_i2c_data *data = dev->data;
852 mxc_i2c_regs_t *i2c = cfg->regs;
853 int ret = 0;
854
855 if (!device_is_ready(cfg->clock)) {
856 return -ENODEV;
857 }
858
859 MXC_I2C_Shutdown(i2c); /* Clear everything out */
860
861 ret = clock_control_on(cfg->clock, (clock_control_subsys_t)&cfg->perclk);
862 if (ret) {
863 return ret;
864 }
865
866 ret = pinctrl_apply_state(cfg->pctrl, PINCTRL_STATE_DEFAULT);
867 if (ret) {
868 return ret;
869 }
870
871 ret = MXC_I2C_Init(i2c, 1, 0); /* Configure as master */
872 if (ret) {
873 return ret;
874 }
875
876 MXC_I2C_SetFrequency(i2c, cfg->bitrate);
877
878 k_sem_init(&data->lock, 1, 1);
879
880 #if defined(CONFIG_I2C_TARGET) || defined(CONFIG_I2C_MAX32_INTERRUPT)
881 cfg->irq_config_func(dev);
882 #endif
883
884 #ifdef CONFIG_I2C_MAX32_INTERRUPT
885 irq_enable(cfg->irqn);
886
887 k_sem_init(&data->xfer, 0, 1);
888 #endif
889
890 #if defined(CONFIG_I2C_TARGET)
891 data->first_write = true;
892 data->target_mode = 0;
893 #endif
894 data->dev = dev;
895
896 return ret;
897 }
898
899 #if defined(CONFIG_I2C_TARGET) || defined(CONFIG_I2C_MAX32_INTERRUPT)
900 #define I2C_MAX32_CONFIG_IRQ_FUNC(n) \
901 .irq_config_func = i2c_max32_irq_config_func_##n, .irqn = DT_INST_IRQN(n),
902
903 #define I2C_MAX32_IRQ_CONFIG_FUNC(n) \
904 static void i2c_max32_irq_config_func_##n(const struct device *dev) \
905 { \
906 IRQ_CONNECT(DT_INST_IRQN(n), DT_INST_IRQ(n, priority), i2c_max32_isr, \
907 DEVICE_DT_INST_GET(n), 0); \
908 }
909 #else
910 #define I2C_MAX32_CONFIG_IRQ_FUNC(n)
911 #define I2C_MAX32_IRQ_CONFIG_FUNC(n)
912 #endif
913
914 #if CONFIG_I2C_MAX32_DMA
915 #define MAX32_DT_INST_DMA_CTLR(n, name) \
916 COND_CODE_1(DT_INST_NODE_HAS_PROP(n, dmas), \
917 (DEVICE_DT_GET(DT_INST_DMAS_CTLR_BY_NAME(n, name))), (NULL))
918
919 #define MAX32_DT_INST_DMA_CELL(n, name, cell) \
920 COND_CODE_1(DT_INST_NODE_HAS_PROP(n, dmas), (DT_INST_DMAS_CELL_BY_NAME(n, name, cell)), \
921 (0xff))
922
923 #define MAX32_I2C_TX_DMA_INIT(n) \
924 .tx_dma.dev = MAX32_DT_INST_DMA_CTLR(n, tx), \
925 .tx_dma.channel = MAX32_DT_INST_DMA_CELL(n, tx, channel), \
926 .tx_dma.slot = MAX32_DT_INST_DMA_CELL(n, tx, slot),
927 #define MAX32_I2C_RX_DMA_INIT(n) \
928 .rx_dma.dev = MAX32_DT_INST_DMA_CTLR(n, rx), \
929 .rx_dma.channel = MAX32_DT_INST_DMA_CELL(n, rx, channel), \
930 .rx_dma.slot = MAX32_DT_INST_DMA_CELL(n, rx, slot),
931 #else
932 #define MAX32_I2C_TX_DMA_INIT(n)
933 #define MAX32_I2C_RX_DMA_INIT(n)
934 #endif
935
936 #define DEFINE_I2C_MAX32(_num) \
937 PINCTRL_DT_INST_DEFINE(_num); \
938 I2C_MAX32_IRQ_CONFIG_FUNC(_num) \
939 static const struct max32_i2c_config max32_i2c_dev_cfg_##_num = { \
940 .regs = (mxc_i2c_regs_t *)DT_INST_REG_ADDR(_num), \
941 .pctrl = PINCTRL_DT_INST_DEV_CONFIG_GET(_num), \
942 .clock = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(_num)), \
943 .perclk.bus = DT_INST_CLOCKS_CELL(_num, offset), \
944 .perclk.bit = DT_INST_CLOCKS_CELL(_num, bit), \
945 .bitrate = DT_INST_PROP(_num, clock_frequency), \
946 I2C_MAX32_CONFIG_IRQ_FUNC(_num) MAX32_I2C_TX_DMA_INIT(_num) \
947 MAX32_I2C_RX_DMA_INIT(_num)}; \
948 static struct max32_i2c_data max32_i2c_data_##_num; \
949 I2C_DEVICE_DT_INST_DEFINE(_num, i2c_max32_init, NULL, &max32_i2c_data_##_num, \
950 &max32_i2c_dev_cfg_##_num, PRE_KERNEL_2, \
951 CONFIG_I2C_INIT_PRIORITY, &api);
952
953 DT_INST_FOREACH_STATUS_OKAY(DEFINE_I2C_MAX32)
954
