93 	QUADSPI_TypeDef *regs;  member
226 	LOG_DBG("CCR 0x%x", dev_cfg->regs->CCR);  in qspi_send_cmd()
303 	LOG_DBG("CCR 0x%x", dev_cfg->regs->CCR);  in qspi_write_access()
1011 	uint8_t regs[4] = { 0 };  in qspi_write_status_register()  local
1023 		regs[0] = reg;  in qspi_write_status_register()
1024 		regs_p = &regs[0];  in qspi_write_status_register()
1027 			ret = qspi_read_status_register(dev, 2, &regs[1]);  in qspi_write_status_register()
1036 		regs[1] = reg;  in qspi_write_status_register()
1037 		regs_p = &regs[1];  in qspi_write_status_register()
1042 			ret = qspi_read_status_register(dev, 1, &regs[0]);  in qspi_write_status_register()
1048 			regs_p = &regs[0];  in qspi_write_status_register()
1053 		regs[2] = reg;  in qspi_write_status_register()
1054 		regs_p = &regs[2];  in qspi_write_status_register()
1614 	.regs = (QUADSPI_TypeDef *)DT_REG_ADDR(STM32_QSPI_NODE),