| /Zephyr-latest/drivers/gpio/ |
| D | gpio_rv32m1.c | 82 uint32_t mask = 0U; in gpio_rv32m1_configure() local
133 mask |= PORT_PCR_MUX_MASK; in gpio_rv32m1_configure()
139 mask |= PORT_PCR_PE_MASK | PORT_PCR_PS_MASK; in gpio_rv32m1_configure()
155 mask |= PORT_PCR_IRQC_MASK; in gpio_rv32m1_configure()
158 port_base->PCR[pin] = (port_base->PCR[pin] & ~mask) | pcr; in gpio_rv32m1_configure()
174 uint32_t mask, in gpio_rv32m1_port_set_masked_raw() argument
180 gpio_base->PDOR = (gpio_base->PDOR & ~mask) | (mask & value); in gpio_rv32m1_port_set_masked_raw()
186 uint32_t mask) in gpio_rv32m1_port_set_bits_raw() argument
191 gpio_base->PSOR = mask; in gpio_rv32m1_port_set_bits_raw()
197 uint32_t mask) in gpio_rv32m1_port_clear_bits_raw() argument
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| D | gpio_davinci.c | 103 gpio_port_pins_t mask, gpio_port_value_t value) in gpio_davinci_port_set_masked_raw() argument
107 regs->out_data = (regs->out_data & (~mask)) | (mask & value); in gpio_davinci_port_set_masked_raw()
113 gpio_port_pins_t mask) in gpio_davinci_port_set_bits_raw() argument
117 regs->set_data |= mask; in gpio_davinci_port_set_bits_raw()
123 gpio_port_pins_t mask) in gpio_davinci_port_clear_bits_raw() argument
127 regs->clr_data |= mask; in gpio_davinci_port_clear_bits_raw()
133 gpio_port_pins_t mask) in gpio_davinci_port_toggle_bits() argument
137 regs->out_data ^= mask; in gpio_davinci_port_toggle_bits()
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| D | gpio_cc13xx_cc26xx.c | 48 uint32_t mask);
50 uint32_t mask);
137 uint32_t mask, in gpio_cc13xx_cc26xx_port_set_masked_raw() argument
140 GPIO_setMultiDio(mask & value); in gpio_cc13xx_cc26xx_port_set_masked_raw()
141 GPIO_clearMultiDio(mask & ~value); in gpio_cc13xx_cc26xx_port_set_masked_raw()
147 uint32_t mask) in gpio_cc13xx_cc26xx_port_set_bits_raw() argument
149 GPIO_setMultiDio(mask); in gpio_cc13xx_cc26xx_port_set_bits_raw()
155 uint32_t mask) in gpio_cc13xx_cc26xx_port_clear_bits_raw() argument
157 GPIO_clearMultiDio(mask); in gpio_cc13xx_cc26xx_port_clear_bits_raw()
163 uint32_t mask) in gpio_cc13xx_cc26xx_port_toggle_bits() argument
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| D | gpio_mchp_xec.c | 68 uint32_t mask = 0U; in gpio_xec_configure() local
87 mask |= MCHP_GPIO_CTRL_DIR_MASK; in gpio_xec_configure()
88 mask |= MCHP_GPIO_CTRL_INPAD_DIS_MASK; in gpio_xec_configure()
89 mask |= MCHP_GPIO_CTRL_PWRG_MASK; in gpio_xec_configure()
90 mask |= MCHP_GPIO_CTRL_AOD_MASK; in gpio_xec_configure()
96 *current_pcr1 = (*current_pcr1 & ~mask) | pcr1; in gpio_xec_configure()
110 mask |= MCHP_GPIO_CTRL_PUD_MASK; in gpio_xec_configure()
121 mask |= MCHP_GPIO_CTRL_BUFT_MASK; in gpio_xec_configure()
132 mask |= MCHP_GPIO_CTRL_OUTV_HI; in gpio_xec_configure()
154 *current_pcr1 = (*current_pcr1 & ~mask) | pcr1; in gpio_xec_configure()
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| D | gpio_emul.c | 115 get_pins_with_flags(const struct device *port, gpio_port_pins_t mask, in get_pins_with_flags() argument
126 if ((drv_data->flags[i] & mask) == flags) { in get_pins_with_flags()
183 gpio_port_pins_t mask, in gpio_emul_gen_interrupt_bits() argument
197 for (i = 0, *interrupts = 0; mask && i < config->num_pins; in gpio_emul_gen_interrupt_bits()
198 ++i, mask >>= 1, prev_values >>= 1, values >>= 1) { in gpio_emul_gen_interrupt_bits()
199 if ((mask & 1) == 0) { in gpio_emul_gen_interrupt_bits()
271 static void gpio_emul_pend_interrupt(const struct device *port, gpio_port_pins_t mask, in gpio_emul_pend_interrupt() argument
281 gpio_emul_gen_interrupt_bits(port, mask, prev_values, values, in gpio_emul_pend_interrupt()
289 gpio_emul_gen_interrupt_bits(port, mask, prev_values, values, in gpio_emul_pend_interrupt()
297 gpio_port_pins_t mask, in gpio_emul_input_set_masked_int() argument
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| D | gpio_mchp_mss.c | 105 gpio_port_pins_t mask) in mss_gpio_port_toggle_bits() argument
109 gpio->gpio_out ^= mask; in mss_gpio_port_toggle_bits()
125 gpio_port_pins_t mask, in mss_gpio_port_set_masked_raw() argument
130 gpio->gpio_out = (gpio->gpio_out & ~mask) | (value & mask); in mss_gpio_port_set_masked_raw()
136 gpio_port_pins_t mask) in mss_gpio_port_set_bits_raw() argument
140 gpio->gpio_out |= mask; in mss_gpio_port_set_bits_raw()
146 gpio_port_pins_t mask) in mss_gpio_port_clear_bits_raw() argument
150 gpio->gpio_out &= ~mask; in mss_gpio_port_clear_bits_raw()
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| D | gpio_intel.c | 430 static int port_get_raw(const struct device *dev, uint32_t mask, in port_get_raw() argument
444 while (mask != 0U) { in port_get_raw()
445 pin = find_lsb_set(mask) - 1; in port_get_raw()
451 mask &= ~BIT(pin); in port_get_raw()
470 static int port_set_raw(const struct device *dev, uint32_t mask, in port_set_raw() argument
476 while (mask != 0) { in port_set_raw()
477 pin = find_lsb_set(mask) - 1; in port_set_raw()
483 mask &= ~BIT(pin); in port_set_raw()
507 uint32_t mask, in gpio_intel_port_set_masked_raw() argument
512 port_get_raw(dev, mask, &port_val, true); in gpio_intel_port_set_masked_raw()
[all …]
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| /Zephyr-latest/drivers/entropy/ |
| D | entropy_nrf5.c | 78 uint8_t mask; member
123 uint32_t mask = rngp->mask; in rng_pool_get() local
139 available = (last - first) & mask; in rng_pool_get()
148 rngp->first_alloc = (first + len) & mask; in rng_pool_get()
153 first = (first + 1) & mask; in rng_pool_get()
180 uint8_t mask = rngp->mask; in rng_pool_put() local
183 if (((last - first) & mask) == mask) { in rng_pool_put()
188 rngp->last = (last + 1) & mask; in rng_pool_put()
198 rngp->mask = size - 1; in rng_pool_init()
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| D | entropy_smartbond.c | 29 uint8_t mask; member
140 uint32_t mask = rngp->mask; in rng_pool_get() local
156 available = (last - first) & mask; in rng_pool_get()
165 rngp->first_alloc = (first + len) & mask; in rng_pool_get()
170 first = (first + 1) & mask; in rng_pool_get()
197 uint8_t mask = rngp->mask; in rng_pool_put() local
200 if (((last - first) & mask) == mask) { in rng_pool_put()
205 rngp->last = (last + 1) & mask; in rng_pool_put()
231 rngp->mask = size - 1; in rng_pool_init()
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| /Zephyr-latest/dts/riscv/ite/ |
| D | it81xx2.dtsi | 68 func3-en-mask = <0 0 0 0
72 func4-en-mask = <0 0 0 0
76 volt-sel-mask = <0 0 0 0
88 func3-en-mask = <0x01 0x02 0 0
92 func4-en-mask = <0 0 0 0
96 volt-sel-mask = <0 0 0 0x02
108 func3-en-mask = <0 0 0 0x10
112 func4-en-mask = <0 0 0 0
116 volt-sel-mask = <0x80 0x20 0x10 0
128 func3-en-mask = <0 0 0 0
[all …]
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| D | it82xx2.dtsi | 57 wuc-mask = <BIT(3) BIT(4) BIT(5) BIT(0)
83 wuc-mask = <BIT(5) BIT(6) BIT(4) BIT(7)
109 wuc-mask = <BIT(5) BIT(3) BIT(7) BIT(4)
135 wuc-mask = <BIT(0) BIT(1) BIT(4) BIT(6)
161 wuc-mask = <BIT(0) BIT(1) BIT(2) BIT(3)
187 wuc-mask = <BIT(0) BIT(1) BIT(2) BIT(3)
213 wuc-mask = <BIT(3) BIT(4) BIT(5) BIT(3)
239 wuc-mask = <BIT(0) BIT(1) BIT(2) BIT(3)
265 wuc-mask = <BIT(7) BIT(0) BIT(1) BIT(2)
291 wuc-mask = <BIT(0) BIT(1) BIT(2) BIT(3)
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| /Zephyr-latest/drivers/serial/ |
| D | uart_rv32m1_lpuart.c | 127 uint32_t mask = kLPUART_TxDataRegEmptyInterruptEnable; in rv32m1_lpuart_irq_tx_enable() local
129 LPUART_EnableInterrupts(config->base, mask); in rv32m1_lpuart_irq_tx_enable()
135 uint32_t mask = kLPUART_TxDataRegEmptyInterruptEnable; in rv32m1_lpuart_irq_tx_disable() local
137 LPUART_DisableInterrupts(config->base, mask); in rv32m1_lpuart_irq_tx_disable()
151 uint32_t mask = kLPUART_TxDataRegEmptyInterruptEnable; in rv32m1_lpuart_irq_tx_ready() local
153 return (LPUART_GetEnabledInterrupts(config->base) & mask) in rv32m1_lpuart_irq_tx_ready()
160 uint32_t mask = kLPUART_RxDataRegFullInterruptEnable; in rv32m1_lpuart_irq_rx_enable() local
162 LPUART_EnableInterrupts(config->base, mask); in rv32m1_lpuart_irq_rx_enable()
168 uint32_t mask = kLPUART_RxDataRegFullInterruptEnable; in rv32m1_lpuart_irq_rx_disable() local
170 LPUART_DisableInterrupts(config->base, mask); in rv32m1_lpuart_irq_rx_disable()
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| D | uart_mcux.c | 211 uint32_t mask = kUART_TxDataRegEmptyInterruptEnable; in uart_mcux_irq_tx_enable() local
213 UART_EnableInterrupts(config->base, mask); in uart_mcux_irq_tx_enable()
219 uint32_t mask = kUART_TxDataRegEmptyInterruptEnable; in uart_mcux_irq_tx_disable() local
221 UART_DisableInterrupts(config->base, mask); in uart_mcux_irq_tx_disable()
235 uint32_t mask = kUART_TxDataRegEmptyInterruptEnable; in uart_mcux_irq_tx_ready() local
238 return (UART_GetEnabledInterrupts(config->base) & mask) in uart_mcux_irq_tx_ready()
245 uint32_t mask = kUART_RxDataRegFullInterruptEnable; in uart_mcux_irq_rx_enable() local
247 UART_EnableInterrupts(config->base, mask); in uart_mcux_irq_rx_enable()
253 uint32_t mask = kUART_RxDataRegFullInterruptEnable; in uart_mcux_irq_rx_disable() local
255 UART_DisableInterrupts(config->base, mask); in uart_mcux_irq_rx_disable()
[all …]
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| /Zephyr-latest/drivers/rtc/ |
| D | rtc_xmc4xxx.c | 101 uint16_t *mask) in rtc_xmc4xxx_alarm_get_supported_fields() argument
106 *mask = RTC_XMC4XXX_SUPPORTED_ALARM_MASK; in rtc_xmc4xxx_alarm_get_supported_fields()
110 static int rtc_xmc4xxx_alarm_set_time(const struct device *dev, uint16_t id, uint16_t mask, in rtc_xmc4xxx_alarm_set_time() argument
115 if (id != 0 || (mask > 0 && timeptr == NULL)) { in rtc_xmc4xxx_alarm_set_time()
119 if (mask == 0) { in rtc_xmc4xxx_alarm_set_time()
125 if (mask != RTC_XMC4XXX_SUPPORTED_ALARM_MASK) { in rtc_xmc4xxx_alarm_set_time()
135 static int rtc_xmc4xxx_alarm_get_time(const struct device *dev, uint16_t id, uint16_t *mask, in rtc_xmc4xxx_alarm_get_time() argument
141 if (id != 0 || mask == NULL || timeptr == NULL) { in rtc_xmc4xxx_alarm_get_time()
145 *mask = RTC_XMC4XXX_SUPPORTED_ALARM_MASK; in rtc_xmc4xxx_alarm_get_time()
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| D | rtc_pcf8563.c | 206 uint16_t *mask) in pcf8563_alarm_get_supported_fields() argument
216 *mask = PCF8563_RTC_ALARM_TIME_MASK; in pcf8563_alarm_get_supported_fields()
221 static int pcf8563_alarm_set_time(const struct device *dev, uint16_t id, uint16_t mask, in pcf8563_alarm_set_time() argument
233 if ((mask & ~(PCF8563_RTC_ALARM_TIME_MASK)) != 0) { in pcf8563_alarm_set_time()
234 LOG_ERR("invalid alarm field mask 0x%04x", mask); in pcf8563_alarm_set_time()
238 if (!rtc_utils_validate_rtc_time(timeptr, mask)) { in pcf8563_alarm_set_time()
247 if ((mask & RTC_ALARM_TIME_MASK_MINUTE) != 0) { in pcf8563_alarm_set_time()
254 if ((mask & RTC_ALARM_TIME_MASK_HOUR) != 0) { in pcf8563_alarm_set_time()
260 if ((mask & RTC_ALARM_TIME_MASK_MONTHDAY) != 0) { in pcf8563_alarm_set_time()
266 if ((mask & RTC_ALARM_TIME_MASK_WEEKDAY) != 0) { in pcf8563_alarm_set_time()
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| D | rtc_nxp_irtc.c | 132 uint16_t *mask) in nxp_irtc_alarm_get_supported_fields() argument
140 *mask = (RTC_ALARM_TIME_MASK_SECOND | RTC_ALARM_TIME_MASK_MINUTE | in nxp_irtc_alarm_get_supported_fields()
147 static int nxp_irtc_alarm_set_time(const struct device *dev, uint16_t id, uint16_t mask, in nxp_irtc_alarm_set_time() argument
154 if (id != 0 || (mask && (timeptr == 0)) || in nxp_irtc_alarm_set_time()
155 (timeptr && !rtc_utils_validate_rtc_time(timeptr, mask))) { in nxp_irtc_alarm_set_time()
163 if (mask & RTC_ALARM_TIME_MASK_SECOND) { in nxp_irtc_alarm_set_time()
167 if (mask & RTC_ALARM_TIME_MASK_MINUTE) { in nxp_irtc_alarm_set_time()
171 if (mask & RTC_ALARM_TIME_MASK_HOUR) { in nxp_irtc_alarm_set_time()
175 if (mask & RTC_ALARM_TIME_MASK_MONTHDAY) { in nxp_irtc_alarm_set_time()
179 if (mask & RTC_ALARM_TIME_MASK_MONTH) { in nxp_irtc_alarm_set_time()
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| /Zephyr-latest/include/zephyr/drivers/ |
| D | rtc.h | 116 uint16_t *mask);
122 typedef int (*rtc_api_alarm_set_time)(const struct device *dev, uint16_t id, uint16_t mask,
129 typedef int (*rtc_api_alarm_get_time)(const struct device *dev, uint16_t id, uint16_t *mask,
243 uint16_t *mask);
246 uint16_t *mask) in z_impl_rtc_alarm_get_supported_fields() argument
252 return DEVICE_API_GET(rtc, dev)->alarm_get_supported_fields(dev, id, mask); in z_impl_rtc_alarm_get_supported_fields()
278 __syscall int rtc_alarm_set_time(const struct device *dev, uint16_t id, uint16_t mask,
281 static inline int z_impl_rtc_alarm_set_time(const struct device *dev, uint16_t id, uint16_t mask, in z_impl_rtc_alarm_set_time() argument
288 return DEVICE_API_GET(rtc, dev)->alarm_set_time(dev, id, mask, timeptr); in z_impl_rtc_alarm_set_time()
306 __syscall int rtc_alarm_get_time(const struct device *dev, uint16_t id, uint16_t *mask,
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| /Zephyr-latest/soc/nxp/imxrt/imxrt6xx/cm33/ |
| D | flash_clock_setup.c | 32 uint32_t mask = 0; in flash_init() local
48 mask |= FLEXSPI_STS2_AREFLOCK_MASK | FLEXSPI_STS2_ASLVLOCK_MASK; in flash_init()
53 mask |= FLEXSPI_STS2_BREFLOCK_MASK | FLEXSPI_STS2_BSLVLOCK_MASK; in flash_init()
58 if ((status & mask) == mask) { in flash_init()
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| /Zephyr-latest/soc/nxp/imx/imx8ulp/adsp/include/adsp/ |
| D | io.h | 25 static inline void io_reg_update_bits(uint32_t reg, uint32_t mask, in io_reg_update_bits() argument
28 io_reg_write(reg, (io_reg_read(reg) & (~mask)) | (value & mask)); in io_reg_update_bits()
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| /Zephyr-latest/soc/nxp/imx/imx8x/adsp/include/adsp/ |
| D | io.h | 25 static inline void io_reg_update_bits(uint32_t reg, uint32_t mask, in io_reg_update_bits() argument
28 io_reg_write(reg, (io_reg_read(reg) & (~mask)) | (value & mask)); in io_reg_update_bits()
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| /Zephyr-latest/soc/nxp/imx/imx8/adsp/include/adsp/ |
| D | io.h | 25 static inline void io_reg_update_bits(uint32_t reg, uint32_t mask, in io_reg_update_bits() argument
28 io_reg_write(reg, (io_reg_read(reg) & (~mask)) | (value & mask)); in io_reg_update_bits()
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| /Zephyr-latest/soc/nxp/imx/imx8m/adsp/include/adsp/ |
| D | io.h | 25 static inline void io_reg_update_bits(uint32_t reg, uint32_t mask, in io_reg_update_bits() argument
28 io_reg_write(reg, (io_reg_read(reg) & (~mask)) | (value & mask)); in io_reg_update_bits()
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| /Zephyr-latest/soc/nxp/imxrt/imxrt5xx/f1/include/adsp/ |
| D | io.h | 25 static inline void io_reg_update_bits(uint32_t reg, uint32_t mask, in io_reg_update_bits() argument
28 io_reg_write(reg, (io_reg_read(reg) & (~mask)) | (value & mask)); in io_reg_update_bits()
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| /Zephyr-latest/drivers/interrupt_controller/ |
| D | intc_wkpu_nxp_s32.c | 112 uint32_t mask = BIT(irq % 32U); in wkpu_nxp_s32_enable_interrupt() local
121 reg_val |= mask; in wkpu_nxp_s32_enable_interrupt()
123 reg_val &= ~mask; in wkpu_nxp_s32_enable_interrupt()
129 reg_val |= mask; in wkpu_nxp_s32_enable_interrupt()
131 reg_val &= ~mask; in wkpu_nxp_s32_enable_interrupt()
136 REG_WRITE(WKPU_WISR(reg_idx), REG_READ(WKPU_WISR(reg_idx)) | mask); in wkpu_nxp_s32_enable_interrupt()
137 REG_WRITE(WKPU_IRER(reg_idx), REG_READ(WKPU_IRER(reg_idx)) | mask); in wkpu_nxp_s32_enable_interrupt()
143 uint32_t mask = BIT(irq % 32U); in wkpu_nxp_s32_disable_interrupt() local
149 REG_WRITE(WKPU_WIREER(reg_idx), REG_READ(WKPU_WIREER(reg_idx)) & ~mask); in wkpu_nxp_s32_disable_interrupt()
150 REG_WRITE(WKPU_WIFEER(reg_idx), REG_READ(WKPU_WIFEER(reg_idx)) & ~mask); in wkpu_nxp_s32_disable_interrupt()
[all …]
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| /Zephyr-latest/drivers/pinctrl/ |
| D | pinctrl_mci_io_mux.c | 31 uint32_t mask, set; in configure_pin_props() local
55 mask = 0x3 << ((gpio_idx & 0xF) << 1); in configure_pin_props()
57 *pull_reg = (*pull_reg & ~mask) | set; in configure_pin_props()
61 *slew_reg = (*slew_reg & ~mask) | set; in configure_pin_props()
64 mask = (0x1 << (gpio_idx & 0x1F)); in configure_pin_props()
66 *sleep_force_en = (*sleep_force_en & ~mask) | set; in configure_pin_props()
68 *sleep_force_val = (*sleep_force_val & ~mask) | set; in configure_pin_props()
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