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Searched refs:domain (Results 51 – 75 of 283) sorted by relevance

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/Zephyr-latest/drivers/spi/
Dspi_cc13xx_cc26xx.c259 uint32_t domain, periph; \
263 domain = PRCM_DOMAIN_SERIAL; \
266 domain = PRCM_DOMAIN_PERIPH; \
270 PRCMPowerDomainOn(domain); \
284 while (PRCMPowerDomainsAllOn(domain) != \
/Zephyr-latest/dts/arm/st/h7/
Dstm32h745.dtsi91 /* System data RAM accessible over AXI bus: AXI SRAM in D1 domain */
97 /* System data RAM accessible over AHB bus: SRAM1 in D2 domain */
104 /* System data RAM accessible over AHB bus: SRAM2 in D2 domain */
111 /* System data RAM accessible over AHB bus: SRAM3 in D2 domain */
118 /* System data RAM accessible over AHB bus: SRAM4 in D3 domain */
Dstm32h7a3.dtsi113 /* System data RAM accessible over AXI bus: AXI SRAM1 in CD domain */
119 /* System data RAM accessible over AXI bus: AXI SRAM2 in CD domain */
126 /* System data RAM accessible over AXI bus: AXI SRAM3 in CD domain */
133 /* System data RAM accessible over AHB bus: SRAM1 in CD domain */
140 /* System data RAM accessible over AHB bus: SRAM2 in CD domain */
147 /* System data RAM accessible over AHB bus: SRD SRAM in SRD domain */
/Zephyr-latest/doc/services/logging/
Dindex.rst31 - Design ready for multi-domain/multi-processor system.
34 - Support for multi-domain logging.
84 domain ID which might be used for multiprocessor systems), timestamp and
401 A log message contains a message descriptor (source, domain and level), timestamp,
518 Multi-domain support
521 More complex systems can consist of multiple domains where each domain is an
525 Tracing and debugging on a multi-domain system is more complex and requires an efficient logging
528 * Log inside each domain independently.
529 This option is not always possible as it requires that each domain has an available backend
532 * Use a multi-domain logging system where log messages from each domain end up in one root domain,
[all …]
/Zephyr-latest/include/zephyr/drivers/clock_control/
Drenesas_cpg_mssr.h16 uint32_t domain; member
/Zephyr-latest/boards/ezurio/bl5340_dvk/
DKconfig13 The board which will be used for CPUNET domain when creating a multi
26 The board which will be used for CPUAPP domain when creating a multi
/Zephyr-latest/dts/arm/renesas/rcar/gen4/
Dr8a779f0.dtsi14 * located in the control domain
26 * Using domain 0 as Linux
45 * Control domain security has to be released to access gpio4 controller
/Zephyr-latest/tests/kernel/device/boards/
Dhifive_unmatched_fu740_s7.overlay69 #power-domain-cells = <0>;
76 #power-domain-cells = <0>;
83 #power-domain-cells = <0>;
Dhifive_unmatched_fu740_u74.overlay69 #power-domain-cells = <0>;
76 #power-domain-cells = <0>;
83 #power-domain-cells = <0>;
/Zephyr-latest/tests/net/lib/mdns_responder/src/
Dmain.c36 char domain[DNS_SD_DOMAIN_MAX_SIZE + NULL_CHAR_SIZE]; member
203 records[i].domain = services[i].domain; in test_setup()
247 service->domain[0] = '\0'; in free_service()
333 const char *proto, const char *domain, uint8_t *txt, in alloc_ext_record() argument
343 strcpy(services[i].domain, domain); in alloc_ext_record()
/Zephyr-latest/subsys/logging/
Dlog_output_dict.c23 output_hdr.domain = msg->hdr.desc.domain; in log_dict_output_msg_process()
Dlog_output.c301 const char *domain, in ids_print() argument
321 if (domain) { in ids_print()
322 total += print_formatted(output, "%s/", domain); in ids_print()
443 const char *domain, in syslog_print() argument
577 const char *domain, in prefix_print() argument
620 length += syslog_print(output, level_on, func_on, &thread_on, domain, in prefix_print()
626 length += ids_print(output, level_on, func_on, thread_on, domain, in prefix_print()
642 const char *domain, in log_output_process() argument
657 domain, source, tid, level); in log_output_process()
/Zephyr-latest/boards/nordic/thingy53/
DKconfig18 The board which will be used for CPUNET domain when creating a multi
31 The board which will be used for CPUAPP domain when creating a multi
/Zephyr-latest/dts/xtensa/intel/
Dintel_adsp_ace15_mtpm.dtsi398 compatible = "intel,adsp-power-domain";
400 #power-domain-cells = <0>;
403 compatible = "intel,adsp-power-domain";
405 #power-domain-cells = <0>;
408 compatible = "intel,adsp-power-domain";
410 #power-domain-cells = <0>;
413 compatible = "intel,adsp-power-domain";
415 #power-domain-cells = <0>;
418 compatible = "intel,adsp-power-domain";
420 #power-domain-cells = <0>;
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Dintel_adsp_ace20_lnl.dtsi330 compatible = "intel,adsp-power-domain";
332 #power-domain-cells = <0>;
335 compatible = "intel,adsp-power-domain";
337 #power-domain-cells = <0>;
340 compatible = "intel,adsp-power-domain";
342 #power-domain-cells = <0>;
345 compatible = "intel,adsp-power-domain";
347 #power-domain-cells = <0>;
350 compatible = "intel,adsp-power-domain";
352 #power-domain-cells = <0>;
[all …]
/Zephyr-latest/arch/arm/core/mmu/
Darm_mmu_priv.h93 uint32_t domain : 4; member
109 uint32_t domain : 4; member
199 uint32_t domain : 4; member
/Zephyr-latest/boards/panasonic/pan1783/
DKconfig14 The board which will be used for CPUNET domain when creating a multi
27 The board which will be used for CPUAPP domain when creating a multi
/Zephyr-latest/boards/nordic/nrf7002dk/
DKconfig26 The board which will be used for CPUNET domain when creating a multi
43 The board which will be used for CPUAPP domain when creating a multi
/Zephyr-latest/snippets/xen_dom0/boards/
Drcar_salvator_xs.overlay16 * Xen passes actual values for setup in domain device tree, but Zephyr
34 * Xen passes actual values for setup in domain device tree, but Zephyr
Drcar_h3ulcb_r8a77951_a57.overlay16 * Xen passes actual values for setup in domain device tree, but Zephyr
34 * Xen passes actual values for setup in domain device tree, but Zephyr
Dqemu_cortex_a53.overlay20 * Xen passes actual values for setup in domain device tree, but Zephyr
38 * Xen passes actual values for setup in domain device tree, but Zephyr
Drcar_spider_s4_r8a779f0_a55.overlay18 * Xen passes actual values for setup in domain device tree, but Zephyr
36 * Xen passes actual values for setup in domain device tree, but Zephyr
/Zephyr-latest/drivers/pwm/
Dpwm_rcar.c259 .mod_clk.domain = DT_INST_CLOCKS_CELL_BY_IDX(n, 0, domain), \
261 .core_clk.domain = DT_INST_CLOCKS_CELL_BY_IDX(n, 1, domain), \
/Zephyr-latest/tests/benchmarks/sched_userspace/src/
Dmain.c57 ret = k_mem_domain_init(&thread->domain, ARRAY_SIZE(parts), parts); in yielder_entry()
64 k_mem_domain_add_thread(&thread->domain, k_current_get()); in yielder_entry()
/Zephyr-latest/subsys/net/lib/ptp/
Dptp.c95 const struct ptp_clock *domain = ptp_clock_init(); in ptp_init() local
98 if (!domain) { in ptp_init()

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