Searched refs:design (Results 151 – 175 of 208) sorted by relevance
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321 …https://www.analog.com/en/design-center/evaluation-hardware-and-software/evaluation-boards-kits/MA…
215 https://docs.mcuboot.com/design.html#image-slots217 documentation https://docs.mcuboot.com/design.html#image-format
12 HiFi 1 DSP. This removes the need for an external sensor hub, reducing system design complexity,
10 The STM32H7B3I-DK Discovery kit is used as a reference design for user
345 …https://www.analog.com/en/design-center/evaluation-hardware-and-software/evaluation-boards-kits/ma…
256 …https://www.nxp.com/design/development-boards/i.mx-evaluation-and-development-boards/evaluation-ki…
227 …https://www.nxp.com/design/development-boards/freedom-development-boards/mcu-boards/freedom-develo…
131 like a design flaw).213 intended to be used similarly. The intent of the design is that at
79 involvement. Such changes should not change the logic or the design of a90 Any changes that touch the logic or the original design of a subsystem or
56 When targeting a custom design without a slow crystal, be sure
43 with it's multiple clients support design.
229 BabbleSim is fully deterministic by design and the results are not affected by
59 When targeting a custom design without a slow crystal, be sure
51 When targeting a custom design without a slow crystal, be sure
6 Zephyr's memory protection design is geared towards microcontrollers with MPU69 mode; disabling this may free 1-2 MPU regions depending on the MPU design.
310 …https://www.nxp.com/design/development-boards/i-mx-evaluation-and-development-boards/i-mx-rt595-ev…
18 Information about the hardware and design resources can be found at
45 the same `design guidelines laid out by Linux`_.
353 …https://www.analog.com/en/design-center/evaluation-hardware-and-software/evaluation-boards-kits/ma…
7 enables design and debug of the Cypress PSOC 63 BLE MCU.
330 …https://www.nxp.com/design/development-boards/i-mx-evaluation-and-development-boards/evaluation-ki…
161 Please follow the existing conventions and do not design one-off bespoke runners (e.g. a python
126 interrupt priority level, in all Cortex-M variants. The main reasons for that design are221 By design, system fault exceptions have the highest priority level. In300 design was to reserve the HardFault exception for handling exceptional error conditions
199 2. **Sensor/Actuator interface**. In this design, the sensor or actuator200 communicates with the SoC via a bus, such as SPI. The hardware design
369 …https://www.nxp.com/design/development-boards/i-mx-evaluation-and-development-boards/i-mx-rt1160-e…
