Searched refs:cores (Results 76 – 100 of 158) sorted by relevance
1234567
| /Zephyr-latest/arch/arc/ |
| D | Kconfig | 38 v2 ISA for the ARC-HS & ARC-EM cores
223 multi cores.
252 ARC EM cores w/o secure shield 2+2 mode support might be configured
261 Disable current Thread Local Storage for ARC. For cores with more then one
|
| /Zephyr-latest/boards/nxp/imx95_evk/doc/ |
| D | index.rst | 18 - The processor integrates up to six Arm Cortex-A55 cores, and supports
19 functional safety with built-in Arm Cortex-M33 and -M7 cores
241 aspects of the hardware such as isolation mechanisms and then starts other cores in the
242 system. After starting these cores, it enters a service mode where it provides access
|
| /Zephyr-latest/boards/qemu/malta/doc/ |
| D | index.rst | 8 This configuration provides support for an MIPS 4Kc/24Kc CPU cores and these devices:
|
| /Zephyr-latest/samples/subsys/ipc/ipc_service/static_vrings/ |
| D | README.rst | 5 Send messages between two cores using the IPC service and static vrings backend.
|
| /Zephyr-latest/samples/subsys/ipc/openamp/ |
| D | README.rst | 5 Send messages between two cores using OpenAMP.
|
| /Zephyr-latest/samples/drivers/ipm/ipm_mhu_dual_core/ |
| D | README.rst | 10 the processor cores. This sample is a simple dual-core example for a
|
| /Zephyr-latest/boards/snps/nsim/arc_classic/doc/ |
| D | index.rst | 33 * ``nsim/nsim_hs5x/smp/12cores`` - SMP 12 cores 32-bit ARCv3 HS platform
34 * ``nsim/nsim_hs6x/smp/12cores`` - SMP 12 cores 64-bit ARCv3 HS platform
222 ARC cores which don't share any memory regions with each other and so SMP-enabled code won't
|
| /Zephyr-latest/boards/seagate/faze/doc/ |
| D | index.rst | 98 …ble-entry-level-32-bit-microcontroller-mcu-based-on-arm-cortex-m0-plus-and-cortex-m0-cores:LPC11U00
|
| /Zephyr-latest/dts/arm/st/h7/ |
| D | stm32h745.dtsi | 86 * The RAM memories placed here can be used by both cores M4/M7
|
| /Zephyr-latest/samples/drivers/mbox_data/ |
| D | README.rst | 13 Sample will ping-pong up to 4 bytes of data between two cores via two mbox channels.
|
| /Zephyr-latest/boards/openisa/rv32m1_vega/doc/ |
| D | index.rst | 18 coprocessor for applications running on RI5CY. The two cores can
265 The RI5CY and ZERO-RISCY cores are configured to use the slow internal
275 connected to the LPUART0 peripheral which the RI5CY and ZERO-RISCY cores use by
280 The OpenSDA chip cannot be used to flash or debug the RISC-V cores.
283 RISC-V cores using an external JTAG dongle.
294 - a `SEGGER J-Link`_ debug probe to debug the RISC-V cores
415 The RV32M1 SoC on the VEGAboard has multiple cores, any of which can
|
| /Zephyr-latest/boards/enjoydigital/litex_vexriscv/doc/ |
| D | index.rst | 23 common cores, and CPU wrappers to create SoCs easily. The tool contains
121 1. Install Migen/LiteX and the LiteX's cores:
|
| /Zephyr-latest/boards/andestech/adp_xc7k_ae350/doc/ |
| D | index.rst | 29 The ADP-XC7K AE350 platform integrates 1 ~ 4 cores 32/64-bit 60MHz RISC-V CPUs, DSP,
34 - 1 ~ 4 cores 32/64-bit 60MHz AndeStar v5 RISC-V CPUs
|
| /Zephyr-latest/arch/arm/core/ |
| D | Kconfig | 84 high code density instruction set for ARM microprocessor cores, to
122 When only the Thumb-2 ISA is supported (i.e. on Cortex-M cores), the
126 and Cortex-R cores), the assembler must use the ARM instruction set
|
| /Zephyr-latest/subsys/logging/frontends/ |
| D | Kconfig | 113 be interleaved because they may come from multiple cores (majors).
|
| /Zephyr-latest/tests/drivers/watchdog/wdt_error_cases/ |
| D | README.txt | 45 other cores are not affected.
|
| /Zephyr-latest/boards/gaisler/generic_leon3/doc/ |
| D | index.rst | 63 Use command 'info sys' to print a detailed report of attached cores
|
| /Zephyr-latest/dts/arm/nxp/ |
| D | nxp_lpc54xxx.dtsi | 63 * to allocate memory to the different cores of the dual-core platforms.
|
| /Zephyr-latest/samples/subsys/ipc/openamp_rsc_table/ |
| D | README.rst | 5 Send messages between two cores using OpenAMP and a resource table.
|
| /Zephyr-latest/samples/subsys/ipc/rpmsg_service/ |
| D | README.rst | 5 Send messages between cores using RPMsg service.
|
| /Zephyr-latest/boards/nordic/nrf9280pdk/ |
| D | nrf9280pdk_nrf9280_cpuapp.dts | 128 /* The following bells on this bellboard are rang by these cores
|
| /Zephyr-latest/boards/nxp/lpcxpresso11u68/doc/ |
| D | index.rst | 147 …ble-entry-level-32-bit-microcontroller-mcu-based-on-arm-cortex-m0-plus-and-cortex-m0-cores:LPC11U00
|
| /Zephyr-latest/samples/modules/tflite-micro/hello_world/ |
| D | README.rst | 109 Kconfig option is only set for Arm Cortex-M cores, i.e. option CPU_CORTEX_M is set.
|
| /Zephyr-latest/boards/renesas/ek_ra4m1/doc/ |
| D | index.rst | 7 cores that share a common set of Renesas peripherals to facilitate design scalability
|
| /Zephyr-latest/doc/connectivity/bluetooth/autopts/ |
| D | autopts-linux.rst | 55 Create Windows virtual machine instance. Make sure it has at least 2 cores and
377 It means your virtual machine has not enough processor cores or memory. Try to add more in
|
1234567
