Searched refs:cores (Results 26 – 50 of 158) sorted by relevance
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| /Zephyr-latest/samples/subsys/ipc/ipc_service/static_vrings/ |
| D | sysbuild.cmake | 20 # This is required because some primary cores need information from the
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| /Zephyr-latest/boards/renesas/rcar_h3ulcb/doc/ |
| D | rcar_h3ulcb_a57.rst | 15 * four 1.5-GHz ARM Cortex-A57 MPCore cores;
16 * four 1.2-GHz ARM Cortex-A53 MPCore cores;
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| /Zephyr-latest/boards/snps/em_starterkit/support/ |
| D | openocd.cfg | 17 # EM11D reportedly requires 5 MHz. Other cores and board can work faster.
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| /Zephyr-latest/boards/phytec/phyboard_electra/doc/ |
| D | index.rst | 29 dual Cortex-A53 cluster and two dual Cortex-R5F cores in the MAIN domain as
94 cores of the SoM. These cores will then load the zephyr binary on the M4 core
104 Therefore, the testing requires the binary to be copied to the SD card to allow the A53 cores to
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| /Zephyr-latest/boards/arduino/opta/doc/ |
| D | index.rst | 15 For Zephyr RTOS, both cores are supported. It is also possible to run only on
46 Both the M7 and M4 cores have access to the 9 GPIO controllers. These
87 two cores. This is done in 3 ways:
93 to both cores at the same time.
95 accessed by both cores at run time. Accesses are protected by a hardware semaphore
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| /Zephyr-latest/tests/subsys/ipc/ipc_sessions/ |
| D | Kconfig | 23 Some of the cores cannot be safely restarted.
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| /Zephyr-latest/soc/raspberrypi/rpi_pico/rp2350/ |
| D | Kconfig | 33 # Currently the IDF only supports using the Cortex-M33 cores. Enforce
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| /Zephyr-latest/samples/sysbuild/hello_world/ |
| D | README.rst | 11 SoCs with multiple cores as each core is exposed as a board target. Other
33 :ref:`nrf54h20dk_nrf54h20`, using application and radio cores:
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| /Zephyr-latest/boards/cdns/xt-sim/doc/ |
| D | index.rst | 16 The following Xtensa cores are officially supported:
23 Xtensa cores can be configured to use either internal or external timers.
94 Add your own core to the list of supported cores as follows:
99 …ch echo) -e "config ${XTENSA_CORE}\n\tbool \"${XTENSA_CORE} core\"\n" >> "soc/xtensa/Kconfig.cores"
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| /Zephyr-latest/drivers/interrupt_controller/ |
| D | Kconfig.clic | 19 Interrupt controller for Nordic VPR cores.
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| /Zephyr-latest/samples/drivers/ipm/ipm_esp32/ |
| D | sysbuild.cmake | 22 # This is required because some primary cores need information from the
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| /Zephyr-latest/boards/beagle/beaglebone_ai64/doc/ |
| D | index.rst | 58 The J721E does not have a separate flash for the R5 cores. Because of this
59 the A72 core has to load the program for the R5 cores to the right memory
70 the R5 cores always see their local ATCM at address 0x00000000 and their BTCM
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| /Zephyr-latest/dts/common/nordic/ |
| D | nrf5340_shared_sram_partition.dtsi | 8 * communication between the application and network cores.
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| /Zephyr-latest/boards/openisa/rv32m1_vega/support/ |
| D | openocd_rv32m1_vega_ri5cy.cfg | 117 # All cores are available, CM4 & RI5CY boot first
135 # All cores are available, CM0 & ZERO_RISCY boot first
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| /Zephyr-latest/boards/arduino/portenta_h7/doc/ |
| D | index.rst | 57 two cores. This is done in 3 ways:
63 to both cores at the same time.
65 accessed by both cores at run time. Accesses are protected by a hardware semaphore
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| /Zephyr-latest/boards/arduino/nicla_vision/doc/ |
| D | index.rst | 56 two cores. This is done in 3 ways:
62 to both cores at the same time.
64 accessed by both cores at run time. Accesses are protected by a hardware semaphore
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| /Zephyr-latest/boards/ti/sk_am62/doc/ |
| D | index.rst | 61 onto an SD-card. This will boot Linux on the A53 application cores of the EVM.
62 These cores will then load the zephyr binary on the M4 core using remoteproc.
72 The testing requires the binary to be copied to the SD card to allow the A53 cores to load it while…
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| /Zephyr-latest/drivers/timer/ |
| D | Kconfig.cavs | 29 a common and synchronized counter for all CPU cores (which
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| /Zephyr-latest/soc/snps/nsim/arc_classic/ |
| D | linker.ld | 30 /* SRAM - memory available for all cores in cluster. Can be used for both instructions and data */
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| /Zephyr-latest/boards/arduino/giga_r1/doc/ |
| D | index.rst | 52 two cores. This is done in 3 ways:
58 to both cores at the same time.
60 accessed by both cores at run time. Accesses are protected by a hardware semaphore
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| /Zephyr-latest/kernel/ |
| D | Kconfig.smp | 33 bool "Delay booting secondary cores"
42 int "Maximum number of CPUs/cores"
46 Maximum number of multiprocessing-capable cores available to the
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| /Zephyr-latest/boards/beagle/beaglev_fire/doc/ |
| D | index.rst | 21 * ``beaglev_fire/polarfire/u54``: Uses the U54 cores
22 * ``beaglev_fire/polarfire/u54/smp``: Uses the U54 cores with CONFIG_SMP=y
94 # Define the entry point address for each hart (U54 cores)
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| /Zephyr-latest/boards/phytec/phyboard_lyra/doc/ |
| D | phyboard_lyra_am62xx_m4.rst | 88 cores of the SoM. These cores will then load the zephyr binary on the M4 core
98 Therefore, the testing requires the binary to be copied to the SD card to allow the A53 cores to
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| /Zephyr-latest/doc/ |
| D | glossary.rst | 84 A group of one or more :term:`CPU cores <CPU core>`, all executing the same image
86 Only :term:`CPU cores <CPU core>` of the same :term:`architecture` can be in a single
87 cluster. Multiple CPU clusters (each of one or more cores) can coexist in
92 instructions sequentially. CPU cores are part of a :term:`CPU cluster`,
93 which can contain one or more cores.
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| /Zephyr-latest/samples/boards/nordic/coresight_stm/ |
| D | README.rst | 23 Application, Radio, PPR and FLPR cores send logs to an ETR buffer.
30 Application, Radio, PPR and FLPR cores send logs to the ETR buffer.
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