Searched refs:core (Results 201 – 225 of 877) sorted by relevance
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| /Zephyr-latest/samples/bluetooth/ccp_call_control_client/ |
| D | Kconfig.sysbuild | 13 bool "HCI IPC image on network core"
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| /Zephyr-latest/samples/bluetooth/ccp_call_control_server/ |
| D | Kconfig.sysbuild | 13 bool "HCI IPC image on network core"
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| /Zephyr-latest/samples/bluetooth/central_hr/ |
| D | Kconfig.sysbuild | 13 bool "HCI IPC image on network core"
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| /Zephyr-latest/samples/bluetooth/pbp_public_broadcast_sink/ |
| D | Kconfig.sysbuild | 13 bool "HCI IPC image on network core"
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| /Zephyr-latest/samples/bluetooth/pbp_public_broadcast_source/ |
| D | Kconfig.sysbuild | 13 bool "HCI IPC image on network core"
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| /Zephyr-latest/samples/bluetooth/peripheral_hr/ |
| D | Kconfig.sysbuild | 13 bool "HCI IPC image on network core"
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| /Zephyr-latest/boards/arduino/opta/doc/ |
| D | index.rst | 16 the M4 making the M7 run the PLC tasks while the M4 core under Zephyr acts as
86 The dual core nature of STM32H747 SoC requires sharing HW resources between the
89 - **Compilation**: Clock configuration is only accessible to M7 core. M4 core only
133 Here is an example for the :zephyr:code-sample:`blinky` application on M7 core.
146 Here is an example for the :zephyr:code-sample:`blinky` application on M4 core.
181 both flashing and debugging are available via ST-LINK (M7 core only).
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| /Zephyr-latest/boards/phytec/phyboard_lyra/doc/ |
| D | phyboard_lyra_am62xx_m4.rst | 11 for the ARM Cortex-M4F MCU core and the following features:
29 quad Cortex-A53 cluster and a single Cortex-M4 core in the MCU domain. Zephyr
30 is ported to run on the M4F core and the following listed hardware
88 cores of the SoM. These cores will then load the zephyr binary on the M4 core
101 To test the M4F core, we build the :zephyr:code-sample:`hello_world` sample with the following comm…
121 The SD card can now be used for booting. The binary will now be loaded onto the M4F core on boot.
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| /Zephyr-latest/tests/bsim/bluetooth/samples/central_hr_peripheral_hr/ |
| D | Kconfig.sysbuild | 10 # otherwise by default they would have gone to the net core.
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| /Zephyr-latest/boards/arduino/portenta_h7/doc/ |
| D | index.rst | 56 The dual core nature of STM32H747 SoC requires sharing HW resources between the
59 - **Compilation**: Clock configuration is only accessible to M7 core. M4 core only
71 Applications for the ``arduino_portenta_h7`` board should be built per core target,
115 Here is an example for the :zephyr:code-sample:`blinky` application on M4 core.
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| /Zephyr-latest/soc/microchip/mec/mec172x/ |
| D | Kconfig.soc | 1 # Microchip MEC172x MCU core series
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| /Zephyr-latest/soc/microchip/mec/mec174x/ |
| D | Kconfig.soc | 4 # Microchip MEC174x MCU core series
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| /Zephyr-latest/soc/microchip/mec/mec175x/ |
| D | Kconfig.soc | 4 # Microchip MEC175x MCU core series
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| /Zephyr-latest/soc/microchip/mec/mech172x/ |
| D | Kconfig.soc | 4 # Microchip MECH172x MCU core series
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| /Zephyr-latest/scripts/west_commands/runners/ |
| D | xtensa.py | 9 from runners.core import RunnerCaps, ZephyrBinaryRunner
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| /Zephyr-latest/boards/infineon/cy8cproto_062_4343w/ |
| D | board.cmake | 4 # During gdb session, by default connect to CM4 core.
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| /Zephyr-latest/boards/nxp/frdm_mcxn947/doc/ |
| D | index.rst | 114 | CPU0 | 0x10000000[1856K] | primary core flash |
116 | CPU1 | 0x101d0000[192K] | secondary core flash |
134 only enables the first core. CPU0 is the only target that can run standalone.
139 second core with config :kconfig:option:`CONFIG_SECOND_CORE_MCUX`.
246 Building a dual-core image
249 The dual-core samples are run using ``frdm_mcxn947/mcxn947/cpu0`` target.
252 and executed on the second core when :kconfig:option:`CONFIG_SECOND_CORE_MCUX` is selected.
320 Debugging a dual-core image
323 For dual core builds, the secondary core should be placed into a loop,
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| /Zephyr-latest/boards/firefly/roc_rk3568_pc/doc/ |
| D | index.rst | 11 RK3568 quad-core 64-bit Cortex-A55 processor, with brand new ARM v8.2-A architecture,
112 Secondary CPU core 1 (MPID:0x100) is up
113 Secondary CPU core 2 (MPID:0x200) is up
114 Secondary CPU core 3 (MPID:0x300) is up
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| /Zephyr-latest/boards/oct/osd32mp1_brk/doc/ |
| D | osd32mp1_brk.rst | 8 Zephyr OS is ported to run on the Cortex®-M4 core of the STM32MP157F.
15 - Dual-core Arm® Cortex®-A7 up to 800 MHz, 32 bits
48 - 32-bit dual-core Arm® Cortex®-A7
50 - L1 32-Kbyte I / 32-Kbyte D for each core
182 by the Linux Remoteproc Framework on Cortex®-A7 core. To enable the USART2 console, modify
190 started by the Cortex®-A7 core. The Cortex®-A7 core is responsible for loading the
209 Refer to following instructions to boot Zephyr on the Cortex®-M4 core:
229 4. Boot Zephyr on the Cortex®-M4 core:
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| /Zephyr-latest/boards/96boards/meerkat96/doc/ |
| D | index.rst | 9 96Boards Meerkat96 board is based on NXP i.MX7 Hybrid multi-core processor,
10 composed of a dual Cortex®-A7 and a single Cortex®-M4 core.
11 Zephyr OS is ported to run on the Cortex®-M4 core.
50 - Dual Cortex A7 (800MHz/1.0GHz) core and Single Cortex M4 (200MHz) core
153 to be started by the A7 core. The A7 core is responsible to load the M4 binary
274 1. Put the M4 core in reset
278 5. Get the M4 core out of reset
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| /Zephyr-latest/snippets/nordic-flpr/ |
| D | README.rst | 10 (Fast Lightweight Peripheral Processor) from application core.
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| /Zephyr-latest/scripts/west_commands/fetchers/ |
| D | __init__.py | 10 from fetchers.core import ZephyrBlobFetcher
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| /Zephyr-latest/drivers/clock_control/ |
| D | Kconfig.renesas_rz_cpg | 12 The PLLs and core clocks are not configured by the CPG driver.
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| /Zephyr-latest/boards/st/stm32h745i_disco/doc/ |
| D | index.rst | 7 platform for STMicroelectronics Arm |reg| Cortex |reg|‑M7 and Cortex |reg|‑M4 core-based STM32H745X…
20 - Arm |reg| Cortex |reg| core-based microcontroller with 2 Mbytes of flash memory and 1 Mbyte of RA…
95 The dual core nature of STM32H745 SoC requires sharing HW resources between the
98 - **Compilation**: Clock configuration is only accessible to M7 core. M4 core only
112 Applications for the ``stm32h745i_disco`` board should be built per core target,
125 The target core is detected automatically.
189 Here is an example for the :zephyr:code-sample:`blinky` application on M4 core.
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| /Zephyr-latest/boards/st/stm32mp157c_dk2/doc/ |
| D | stm32mp157_dk2.rst | 7 multi-core processor,composed of a dual Cortex®-A7 and a single Cortex®-M4 core.
8 Zephyr OS is ported to run on the Cortex®-M4 core.
56 - 32-bit dual-core Arm® Cortex®-A7
58 - L1 32-Kbyte I / 32-Kbyte D for each core
183 by the Linux Remoteproc Framework on Cortex®-A7 core. In order to keep the UART7
193 started by the Cortex®-A7 core. The Cortex®-A7 core is responsible to load the
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