| /Zephyr-latest/dts/arm/renesas/ra/ra6/ |
| D | r7fa6m3ax.dtsi | 67 channel = <5>;
81 channel = <6>;
95 channel = <7>;
102 channel = <2>;
122 channel-count = <13>;
123 channel-available-mask = <0x1f00ff>;
127 channel-count = <11>;
128 channel-available-mask = <0xf00ef>;
134 channel = <RA_PWM_CHANNEL_13>;
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| /Zephyr-latest/drivers/serial/ |
| D | uart_renesas_ra_sci.c | 1057 #define _ELC_EVENT_SCI_RXI(channel) ELC_EVENT_SCI##channel##_RXI argument
1058 #define _ELC_EVENT_SCI_TXI(channel) ELC_EVENT_SCI##channel##_TXI argument
1059 #define _ELC_EVENT_SCI_TEI(channel) ELC_EVENT_SCI##channel##_TEI argument
1060 #define _ELC_EVENT_SCI_ERI(channel) ELC_EVENT_SCI##channel##_ERI argument
1062 #define ELC_EVENT_SCI_RXI(channel) _ELC_EVENT_SCI_RXI(channel) argument
1063 #define ELC_EVENT_SCI_TXI(channel) _ELC_EVENT_SCI_TXI(channel) argument
1064 #define ELC_EVENT_SCI_TEI(channel) _ELC_EVENT_SCI_TEI(channel) argument
1065 #define ELC_EVENT_SCI_ERI(channel) _ELC_EVENT_SCI_ERI(channel) argument
1140 ELC_EVENT_SCI_RXI(DT_INST_PROP(index, channel)); \
1142 ELC_EVENT_SCI_TXI(DT_INST_PROP(index, channel)); \
[all …]
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| /Zephyr-latest/dts/arm/renesas/ra/ra2/ |
| D | r7fa2a1xh.dtsi | 33 channel = <RA_PWM_CHANNEL_1>;
43 channel = <RA_PWM_CHANNEL_2>;
53 channel = <RA_PWM_CHANNEL_3>;
63 channel = <RA_PWM_CHANNEL_4>;
73 channel = <RA_PWM_CHANNEL_5>;
83 channel = <RA_PWM_CHANNEL_6>;
|
| /Zephyr-latest/dts/arm/renesas/rz/rzg/ |
| D | r9a08g045.dtsi | 230 channel = <0>;
238 channel = <1>;
246 channel = <2>;
254 channel = <3>;
262 channel = <4>;
270 channel = <5>;
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| /Zephyr-latest/subsys/net/lib/wifi_credentials/ |
| D | wifi_credentials.c | 194 size_t password_len, uint32_t flags, uint8_t channel, in wifi_credentials_set_personal() argument
227 header->channel = channel; in wifi_credentials_set_personal()
264 uint32_t *flags, uint8_t *channel, uint32_t *timeout) in wifi_credentials_get_by_ssid_personal() argument
298 *channel = header->channel; in wifi_credentials_get_by_ssid_personal()
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| /Zephyr-latest/drivers/pwm/ |
| D | pwm_mchp_xec_bbled.c | 174 uint32_t channel, uint64_t *cycles) in pwm_bbled_xec_get_cycles_per_sec() argument
179 if (channel > 0) { in pwm_bbled_xec_get_cycles_per_sec()
212 static int pwm_bbled_xec_set_cycles(const struct device *dev, uint32_t channel, in pwm_bbled_xec_set_cycles() argument
220 if (channel > 0) { in pwm_bbled_xec_set_cycles()
221 LOG_ERR("Invalid channel: %u", channel); in pwm_bbled_xec_set_cycles()
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| D | pwm_rpi_pico.c | 41 static inline uint32_t pwm_rpi_channel_to_slice(uint32_t channel) in pwm_rpi_channel_to_slice() argument
43 return channel / 2; in pwm_rpi_channel_to_slice()
46 static inline uint32_t pwm_rpi_channel_to_pico_channel(uint32_t channel) in pwm_rpi_channel_to_pico_channel() argument
48 return channel % 2; in pwm_rpi_channel_to_pico_channel()
|
| /Zephyr-latest/tests/drivers/can/host/pytest/ |
| D | can_shell.py | 26 def __init__(self, dut: DeviceAdapter, shell: Shell, channel: str,
30 self._device = channel
46 super().__init__(channel=channel, can_filters=can_filters, **kwargs)
188 channel=self._device, check=True)
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| /Zephyr-latest/samples/boards/st/power_mgmt/suspend_to_ram/boards/ |
| D | nucleo_wba55cg.overlay | 31 /* adjust channel number according to pinmux in board.dts */
45 channel@8 {
|
| /Zephyr-latest/boards/actinius/icarus_som_dk/ |
| D | arduino_connector.dtsi | 39 #io-channel-cells = <1>;
40 io-channel-map = <0 &adc 2>, /* A0 = P0.15 = AIN2 */
|
| /Zephyr-latest/tests/drivers/regulator/voltage/boards/ |
| D | frdm_mcxn947_mcxn947_cpu0.overlay | 10 /* To do this test, connect LPADC0 channel 2A(J8 pin 28) to VREF_OUT (TP1) */
38 channel@0 {
|
| D | frdm_mcxn947_mcxn947_cpu0_qspi.overlay | 10 /* To do this test, connect LPADC0 channel 2A(J8 pin 28) to VREF_OUT (TP1) */
38 channel@0 {
|
| D | frdm_mcxn236.overlay | 10 /* To do this test, connect LPADC0 channel 2A(J8 pin 12) to VREF_OUT (J2 pin 19) */
38 channel@0 {
|
| /Zephyr-latest/tests/drivers/mbox/mbox_data/remote/src/ |
| D | main.c | 41 static void callback(const struct device *dev, uint32_t channel, void *user_data, in callback() argument
46 g_mbox_received_channel = channel; in callback()
|
| /Zephyr-latest/drivers/counter/ |
| D | counter_timer_shell.c | 103 unsigned long channel = 0; in cmd_timer_oneshot() local
123 channel = shell_strtoul(argv[ARGV_CHN], 10, &err); in cmd_timer_oneshot()
127 } else if (channel > MAX_CHANNEL) { in cmd_timer_oneshot()
138 err = counter_set_channel_alarm(timer_dev, (uint8_t)channel, &alarm_cfg); in cmd_timer_oneshot()
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| /Zephyr-latest/drivers/spi/ |
| D | spi_max32.c | 33 const uint32_t channel; member
430 static void spi_max32_dma_callback(const struct device *dev, void *arg, uint32_t channel, in spi_max32_dma_callback() argument
439 LOG_ERR("DMA callback error with channel %d.", channel); in spi_max32_dma_callback()
442 if (channel == config->tx_dma.channel) { in spi_max32_dma_callback()
444 } else if (channel == config->rx_dma.channel) { in spi_max32_dma_callback()
483 ret = dma_config(config->tx_dma.dev, config->tx_dma.channel, &dma_cfg); in spi_max32_tx_dma_load()
488 return dma_start(config->tx_dma.dev, config->tx_dma.channel); in spi_max32_tx_dma_load()
517 ret = dma_config(config->rx_dma.dev, config->rx_dma.channel, &dma_cfg); in spi_max32_rx_dma_load()
522 return dma_start(config->rx_dma.dev, config->rx_dma.channel); in spi_max32_rx_dma_load()
542 ret = dma_get_status(cfg->tx_dma.dev, cfg->tx_dma.channel, &status); in transceive_dma()
[all …]
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| /Zephyr-latest/samples/basic/blinky_pwm/boards/ |
| D | nrf52840dk_nrf52840.overlay | 7 channel-gpios = <&gpio0 13 PWM_POLARITY_INVERTED>;
|
| D | nrf5340dk_nrf5340_cpuapp.overlay | 7 channel-gpios = <&gpio0 28 PWM_POLARITY_INVERTED>;
|
| D | nrf9160dk_nrf9160.overlay | 7 channel-gpios = <&gpio0 2 PWM_POLARITY_INVERTED>;
|
| /Zephyr-latest/samples/drivers/dac/boards/ |
| D | lpcxpresso55s36.overlay | 10 dac-channel-id = <0>;
|
| D | gd32f450i_eval.overlay | 10 dac-channel-id = <0>;
|
| D | longan_nano.overlay | 10 dac-channel-id = <0>;
|
| D | longan_nano_gd32vf103_lite.overlay | 10 dac-channel-id = <0>;
|
| /Zephyr-latest/drivers/gpio/ |
| D | gpio_xlnx_axi.c | 40 uint8_t channel; member
69 return sys_read32(config->base + (config->channel * GPIO2_OFFSET) + GPIO_DATA_OFFSET); in gpio_xlnx_axi_read_data()
76 sys_write32(val, config->base + (config->channel * GPIO2_OFFSET) + GPIO_DATA_OFFSET); in gpio_xlnx_axi_write_data()
83 sys_write32(val, config->base + (config->channel * GPIO2_OFFSET) + GPIO_TRI_OFFSET); in gpio_xlnx_axi_write_tri()
213 const uint32_t chan_mask = BIT(config->channel); in gpio_xlnx_axi_pin_interrupt_configure()
285 const uint32_t chan_mask = BIT(config->channel); in gpio_xlnx_axi_get_pending_int()
405 .channel = 1, \
435 .channel = 0, \
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| /Zephyr-latest/dts/arm/nxp/ |
| D | nxp_rt11xx_cm4.dtsi | 68 nxp,tx-dma-channel = <0>;
69 nxp,rx-dma-channel = <1>;
75 nxp,tx-dma-channel = <3>;
76 nxp,rx-dma-channel = <4>;
82 nxp,tx-dma-channel = <5>;
83 nxp,rx-dma-channel = <6>;
89 nxp,tx-dma-channel = <7>;
90 nxp,rx-dma-channel = <8>;
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