| /Zephyr-latest/drivers/sdhc/ |
| D | sdhc_renesas_ra.c | 56 uint8_t channel; member
594 #define _ELC_EVENT_SDMMC_ACCS(channel) ELC_EVENT_SDHIMMC##channel##_ACCS argument
595 #define _ELC_EVENT_SDMMC_CARD(channel) ELC_EVENT_SDHIMMC##channel##_CARD argument
596 #define _ELC_EVENT_SDMMC_DMA_REQ(channel) ELC_EVENT_SDHIMMC##channel##_DMA_REQ argument
598 #define ELC_EVENT_SDMMC_ACCS(channel) _ELC_EVENT_SDMMC_ACCS(channel) argument
599 #define ELC_EVENT_SDMMC_CARD(channel) _ELC_EVENT_SDMMC_CARD(channel) argument
600 #define ELC_EVENT_SDMMC_DMA_REQ(channel) _ELC_EVENT_SDMMC_DMA_REQ(channel) argument
607 ELC_EVENT_SDMMC_ACCS(DT_INST_PROP(index, channel)); \
609 ELC_EVENT_SDMMC_CARD(DT_INST_PROP(index, channel)); \
611 ELC_EVENT_SDMMC_DMA_REQ(DT_INST_PROP(index, channel)); \
[all …]
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| /Zephyr-latest/drivers/pwm/ |
| D | pwm_renesas_ra.c | 184 LOG_DBG("channel %u, pin %u, pulse %u, period %u, prescaler: %u.", data->fsp_cfg.channel, in pwm_renesas_ra_set_cycles()
488 #define _ELC_EVENT_GPT_CAPTURE_COMPARE_A(channel) ELC_EVENT_GPT##channel##_CAPTURE_COMPARE_A argument
489 #define _ELC_EVENT_GPT_COUNTER_OVERFLOW(channel) ELC_EVENT_GPT##channel##_COUNTER_OVERFLOW argument
491 #define ELC_EVENT_GPT_CAPTURE_COMPARE_A(channel) _ELC_EVENT_GPT_CAPTURE_COMPARE_A(channel) argument
492 #define ELC_EVENT_GPT_COUNTER_OVERFLOW(channel) _ELC_EVENT_GPT_COUNTER_OVERFLOW(channel) argument
544 .channel = DT_INST_PROP(index, channel), \
549 .capture_a_event = ELC_EVENT_GPT_CAPTURE_COMPARE_A(DT_INST_PROP(index, channel)), \
550 .overflow_event = ELC_EVENT_GPT_COUNTER_OVERFLOW(DT_INST_PROP(index, channel)), \
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| D | pwm_fake.c | 40 static int fake_pwm_get_cycles_per_sec(const struct device *dev, uint32_t channel, uint64_t *cycles) in fake_pwm_get_cycles_per_sec() argument
42 ARG_UNUSED(channel); in fake_pwm_get_cycles_per_sec()
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| /Zephyr-latest/drivers/display/ |
| D | display_rm67162.c | 188 uint8_t channel; member
226 ret = mipi_dsi_attach(config->mipi_dsi, config->channel, &mdev); in rm67162_init()
271 ret = mipi_dsi_dcs_write(config->mipi_dsi, config->channel, in rm67162_init()
290 ret = mipi_dsi_dcs_write(config->mipi_dsi, config->channel, in rm67162_init()
298 ret = mipi_dsi_dcs_write(config->mipi_dsi, config->channel, in rm67162_init()
348 return mipi_dsi_dcs_write(config->mipi_dsi, config->channel, in rm67162_init()
373 wlen = mipi_dsi_transfer(config->mipi_dsi, config->channel, &msg); in rm67162_write_fb()
414 ret = mipi_dsi_dcs_write(config->mipi_dsi, config->channel, in rm67162_write()
428 ret = mipi_dsi_dcs_write(config->mipi_dsi, config->channel, in rm67162_write()
541 return mipi_dsi_dcs_write(config->mipi_dsi, config->channel, in rm67162_set_pixel_format()
[all …]
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| /Zephyr-latest/dts/arm/nxp/ |
| D | nxp_rt10xx.dtsi | 175 channel = <0>;
180 channel = <1>;
185 channel = <2>;
190 channel = <3>;
202 channel = <0>;
207 channel = <1>;
212 channel = <2>;
217 channel = <3>;
229 channel = <0>;
234 channel = <1>;
[all …]
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| D | nxp_rt5xx_common.dtsi | 440 pdmc0: dmic-channel@0 {
441 compatible = "nxp,dmic-channel";
447 pdmc1: dmic-channel@1 {
448 compatible = "nxp,dmic-channel";
454 pdmc2: dmic-channel@2 {
455 compatible = "nxp,dmic-channel";
461 pdmc3: dmic-channel@3 {
462 compatible = "nxp,dmic-channel";
468 pdmc4: dmic-channel@4 {
469 compatible = "nxp,dmic-channel";
[all …]
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| /Zephyr-latest/drivers/ieee802154/ |
| D | ieee802154_rf2xx.c | 139 static void rf2xx_set_rssi_base(const struct device *dev, uint16_t channel) in rf2xx_set_rssi_base() argument
145 base = channel == 0 in rf2xx_set_rssi_base()
149 base = channel == 0 in rf2xx_set_rssi_base()
378 static int rf2xx_configure_sub_channel(const struct device *dev, uint16_t channel) in rf2xx_configure_sub_channel() argument
385 cc_mask = channel == 0 in rf2xx_configure_sub_channel()
389 cc_mask = channel == 0 in rf2xx_configure_sub_channel()
431 static int rf2xx_set_channel(const struct device *dev, uint16_t channel) in rf2xx_set_channel() argument
436 LOG_DBG("Set Channel %d", channel); in rf2xx_set_channel()
441 && channel > 10) { in rf2xx_set_channel()
442 LOG_ERR("Unsupported channel %u", channel); in rf2xx_set_channel()
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| /Zephyr-latest/subsys/mgmt/ec_host_cmd/backends/ |
| D | ec_host_cmd_backend_spi_stm32.c | 150 uint32_t channel; member
184 static void dma_callback(const struct device *dev, void *arg, uint32_t channel, int status);
189 .channel = DT_DMAS_CELL_BY_NAME(id, dir, channel), \
306 static void dma_callback(const struct device *dev, void *arg, uint32_t channel, int status) in dma_callback() argument
311 if (channel == hc_spi->dma_tx->channel) { in dma_callback()
424 ret = dma_reload(hc_spi->dma_tx->dma_dev, hc_spi->dma_tx->channel, (uint32_t)hc_spi->tx_buf, in reload_dma_tx()
431 ret = dma_start(hc_spi->dma_tx->dma_dev, hc_spi->dma_tx->channel); in reload_dma_tx()
469 ret = dma_config(hc_spi->dma_tx->dma_dev, hc_spi->dma_tx->channel, &stream->dma_cfg); in spi_config_dma_tx()
485 ret = dma_reload(hc_spi->dma_rx->dma_dev, hc_spi->dma_rx->channel, dma_source_addr(spi), in reload_dma_rx()
491 ret = dma_start(hc_spi->dma_rx->dma_dev, hc_spi->dma_rx->channel); in reload_dma_rx()
[all …]
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| /Zephyr-latest/drivers/counter/ |
| D | Kconfig.mcux_ctimer | 14 bool "reserve a ctimer channel to set the top value"
18 This reserves a CTimer channel to set the top value. Without
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| /Zephyr-latest/samples/drivers/adc/adc_dt/boards/ |
| D | mimxrt1170_evk_mimxrt1176_cm7_A.overlay | 12 /* adjust channel number according to pinmux in board.dts */
26 channel@0 {
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| /Zephyr-latest/tests/drivers/adc/adc_api/boards/ |
| D | ek_ra4m3.overlay | 31 channel@0 {
40 channel@2 {
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| D | ek_ra6m1.overlay | 31 channel@0 {
40 channel@2 {
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| D | ek_ra6m2.overlay | 31 channel@0 {
40 channel@2 {
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| D | ek_ra6m3.overlay | 31 channel@0 {
40 channel@2 {
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| D | ek_ra6m4.overlay | 31 channel@0 {
40 channel@2 {
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| D | ek_ra6m5.overlay | 31 channel@0 {
40 channel@2 {
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| D | ek_ra8d1.overlay | 31 channel@0 {
40 channel@2 {
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| D | ek_ra8m1.overlay | 31 channel@0 {
40 channel@2 {
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| D | frdm_mcxn236.overlay | 19 channel@0 {
29 channel@1 {
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| D | frdm_mcxn947_mcxn947_cpu0.overlay | 19 channel@0 {
29 channel@1 {
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| D | mck_ra8t1.overlay | 31 channel@0 {
40 channel@2 {
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| /Zephyr-latest/drivers/dma/ |
| D | Kconfig.dw_axi_dmac | 20 creates number of descriptor per channel in a statically allocated pool.
21 Each channel has its own dedicated pool.
33 Max timeout to abort or disable the channel
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| D | dma_nios2_msgdma.c | 66 static int nios2_msgdma_config(const struct device *dev, uint32_t channel, in nios2_msgdma_config() argument
75 if (channel != 0U) { in nios2_msgdma_config()
152 uint32_t channel) in nios2_msgdma_transfer_start() argument
158 if (channel != 0U) { in nios2_msgdma_transfer_start()
176 uint32_t channel) in nios2_msgdma_transfer_stop() argument
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| /Zephyr-latest/boards/google/twinkie_v2/ |
| D | google_twinkie_v2.dts | 108 channel@1 {
117 channel@3 {
126 channel@f {
135 channel@11 {
144 channel@12 {
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| /Zephyr-latest/dts/arm/ti/ |
| D | cc32xx.dtsi | 12 #define INT_ADCCH0 30 // ADC channel 0
13 #define INT_ADCCH1 31 // ADC channel 1
14 #define INT_ADCCH2 32 // ADC channel 2
15 #define INT_ADCCH3 33 // ADC channel 3
124 #io-channel-cells = <1>;
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