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/Zephyr-latest/boards/others/esp32c3_supermini/doc/
Dindex.rst19 - 400 KB SRAM (16 KB for cache)
/Zephyr-latest/kernel/
Dinit.c665 _kernel.ready_q.cache = &z_main_thread; in prepare_multithreading()
/Zephyr-latest/dts/xtensa/intel/
Dintel_adsp_ace30.dtsi20 i-cache-line-size = <64>;
21 d-cache-line-size = <64>;
Dintel_adsp_ace30_ptl.dtsi20 i-cache-line-size = <64>;
21 d-cache-line-size = <64>;
Dintel_adsp_ace15_mtpm.dtsi20 i-cache-line-size = <64>;
21 d-cache-line-size = <64>;
/Zephyr-latest/soc/ite/ec/it8xxx2/
DKconfig196 Flash. This can significantly improve performance when under I-cache
/Zephyr-latest/dts/x86/intel/
Draptor_lake_p.dtsi20 d-cache-line-size = <64>;
Dapollo_lake.dtsi20 d-cache-line-size = <64>;
Draptor_lake_s.dtsi20 d-cache-line-size = <64>;
/Zephyr-latest/boards/espressif/esp32c3_rust/doc/
Dindex.rst21 - 400 KB SRAM (16 KB for cache)
/Zephyr-latest/boards/espressif/esp8684_devkitm/doc/
Dindex.rst15 32-bit, single-core processor, with 272 KB of SRAM (16 KB dedicated to cache) and 576 KB of ROM.
/Zephyr-latest/boards/mediatek/
Dindex.rst28 time there are fewer worries about the incoherent cache).
/Zephyr-latest/soc/nxp/imxrt/imxrt5xx/f1/
Dlinker.ld114 /* Various memory-map dependent cache attribute settings: */
/Zephyr-latest/drivers/wifi/esp32/
DKconfig.esp32161 int "Max number of WiFi cache TX buffers"
166 Set the number of WiFi cache TX buffer number.
/Zephyr-latest/boards/st/steval_stwinbx1/doc/
Dindex.rst97 - 8-Kbyte instruction cache allowing 0-wait-state execution from Flash and
99 - 4-Kbyte data cache for external memories
/Zephyr-latest/boards/st/sensortile_box_pro/doc/
Dindex.rst100 - 8-Kbyte instruction cache allowing 0-wait-state execution from Flash and
102 - 4-Kbyte data cache for external memories
/Zephyr-latest/soc/nxp/imxrt/imxrt7xx/hifi4/
Dlinker.ld117 /* Various memory-map dependent cache attribute settings: */
/Zephyr-latest/soc/nxp/imxrt/imxrt7xx/hifi1/
Dlinker.ld121 /* Various memory-map dependent cache attribute settings: */
/Zephyr-latest/doc/build/kconfig/
Dsetting.rst133 2. Any CMake cache entries prefix with ``CONFIG_``
150 3. From the CMake variable cache
/Zephyr-latest/doc/develop/west/
Drelease-notes.rst395 - ``west update`` now supports ``--narrow``, ``--name-cache``, and
396 ``--path-cache`` options. These can be influenced by the ``update.narrow``,
397 ``update.name-cache``, and ``update.path-cache`` :ref:`west-config` options.
/Zephyr-latest/doc/services/storage/zms/
Dzms.rst428 - When using the ZMS API directly, the recommendation for the cache size is to make it at least
430 - Each additional cache entry will add 8 bytes to your RAM usage. Cache size should be carefully
433 divided into two ZMS entries. The recommendation for the cache size is to make it at least
/Zephyr-latest/arch/xtensa/
DKconfig251 # plus MPU minus s32c1i) does not have cache or SMP capability.
/Zephyr-latest/boards/st/nucleo_u031r8/doc/
Dindex.rst59 - 1-Kbyte instruction cache allowing 0-wait-state execution from flash memory
/Zephyr-latest/cmake/modules/
Dextensions.cmake872 # Arguments given via the CMake cache come last of all. Users
910 # Arguments given via the CMake cache come last of all. Users
1112 # so we cache the capability test results in USER_CACHE_DIR (This
1124 # Locate the cache directory
1130 # The toolchain capability database/cache is maintained as a
1154 # Check the cache
1181 # Populate the cache
1187 # Delete the cache, add the sleep above and run twister with a
3150 # reading a cache scope FOO variable is identical to expand $CACHE{FOO}.
3185 # build settings that can be set from sysbuild, CMakeLists.txt, CMake cache, or
[all …]
/Zephyr-latest/soc/amd/acp_6_0/adsp/
Dlinker.ld164 /* Various memory-map dependent cache attribute settings: */

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