Searched refs:cache (Results 226 – 250 of 319) sorted by relevance
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/Zephyr-latest/boards/others/esp32c3_supermini/doc/ |
D | index.rst | 19 - 400 KB SRAM (16 KB for cache)
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/Zephyr-latest/kernel/ |
D | init.c | 665 _kernel.ready_q.cache = &z_main_thread; in prepare_multithreading()
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/Zephyr-latest/dts/xtensa/intel/ |
D | intel_adsp_ace30.dtsi | 20 i-cache-line-size = <64>; 21 d-cache-line-size = <64>;
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D | intel_adsp_ace30_ptl.dtsi | 20 i-cache-line-size = <64>; 21 d-cache-line-size = <64>;
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D | intel_adsp_ace15_mtpm.dtsi | 20 i-cache-line-size = <64>; 21 d-cache-line-size = <64>;
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/Zephyr-latest/soc/ite/ec/it8xxx2/ |
D | Kconfig | 196 Flash. This can significantly improve performance when under I-cache
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/Zephyr-latest/dts/x86/intel/ |
D | raptor_lake_p.dtsi | 20 d-cache-line-size = <64>;
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D | apollo_lake.dtsi | 20 d-cache-line-size = <64>;
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D | raptor_lake_s.dtsi | 20 d-cache-line-size = <64>;
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/Zephyr-latest/boards/espressif/esp32c3_rust/doc/ |
D | index.rst | 21 - 400 KB SRAM (16 KB for cache)
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/Zephyr-latest/boards/espressif/esp8684_devkitm/doc/ |
D | index.rst | 15 32-bit, single-core processor, with 272 KB of SRAM (16 KB dedicated to cache) and 576 KB of ROM.
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/Zephyr-latest/boards/mediatek/ |
D | index.rst | 28 time there are fewer worries about the incoherent cache).
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/Zephyr-latest/soc/nxp/imxrt/imxrt5xx/f1/ |
D | linker.ld | 114 /* Various memory-map dependent cache attribute settings: */
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/Zephyr-latest/drivers/wifi/esp32/ |
D | Kconfig.esp32 | 161 int "Max number of WiFi cache TX buffers" 166 Set the number of WiFi cache TX buffer number.
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/Zephyr-latest/boards/st/steval_stwinbx1/doc/ |
D | index.rst | 97 - 8-Kbyte instruction cache allowing 0-wait-state execution from Flash and 99 - 4-Kbyte data cache for external memories
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/Zephyr-latest/boards/st/sensortile_box_pro/doc/ |
D | index.rst | 100 - 8-Kbyte instruction cache allowing 0-wait-state execution from Flash and 102 - 4-Kbyte data cache for external memories
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/Zephyr-latest/soc/nxp/imxrt/imxrt7xx/hifi4/ |
D | linker.ld | 117 /* Various memory-map dependent cache attribute settings: */
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/Zephyr-latest/soc/nxp/imxrt/imxrt7xx/hifi1/ |
D | linker.ld | 121 /* Various memory-map dependent cache attribute settings: */
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/Zephyr-latest/doc/build/kconfig/ |
D | setting.rst | 133 2. Any CMake cache entries prefix with ``CONFIG_`` 150 3. From the CMake variable cache
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/Zephyr-latest/doc/develop/west/ |
D | release-notes.rst | 395 - ``west update`` now supports ``--narrow``, ``--name-cache``, and 396 ``--path-cache`` options. These can be influenced by the ``update.narrow``, 397 ``update.name-cache``, and ``update.path-cache`` :ref:`west-config` options.
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/Zephyr-latest/doc/services/storage/zms/ |
D | zms.rst | 428 - When using the ZMS API directly, the recommendation for the cache size is to make it at least 430 - Each additional cache entry will add 8 bytes to your RAM usage. Cache size should be carefully 433 divided into two ZMS entries. The recommendation for the cache size is to make it at least
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/Zephyr-latest/arch/xtensa/ |
D | Kconfig | 251 # plus MPU minus s32c1i) does not have cache or SMP capability.
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/Zephyr-latest/boards/st/nucleo_u031r8/doc/ |
D | index.rst | 59 - 1-Kbyte instruction cache allowing 0-wait-state execution from flash memory
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/Zephyr-latest/cmake/modules/ |
D | extensions.cmake | 872 # Arguments given via the CMake cache come last of all. Users 910 # Arguments given via the CMake cache come last of all. Users 1112 # so we cache the capability test results in USER_CACHE_DIR (This 1124 # Locate the cache directory 1130 # The toolchain capability database/cache is maintained as a 1154 # Check the cache 1181 # Populate the cache 1187 # Delete the cache, add the sleep above and run twister with a 3150 # reading a cache scope FOO variable is identical to expand $CACHE{FOO}. 3185 # build settings that can be set from sysbuild, CMakeLists.txt, CMake cache, or [all …]
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/Zephyr-latest/soc/amd/acp_6_0/adsp/ |
D | linker.ld | 164 /* Various memory-map dependent cache attribute settings: */
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