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/Zephyr-latest/dts/arm/infineon/cat1a/mpns/
DCY8C614ALQI_S2F42.dtsi26 arm,num-irq-priority-bits = <3>;
DCY8C6248LQI_S2D02.dtsi30 arm,num-irq-priority-bits = <3>;
DCY8C6248LQI_S2D42.dtsi30 arm,num-irq-priority-bits = <3>;
DCY8C6148LQI_S2F02.dtsi34 arm,num-irq-priority-bits = <3>;
DCY8C6148LQI_S2F42.dtsi34 arm,num-irq-priority-bits = <3>;
/Zephyr-latest/soc/st/stm32/common/
Dstm32_backup_sram.c58 .enr = DT_INST_CLOCKS_CELL(0, bits) },
/Zephyr-latest/dts/arm/raspberrypi/rpi_pico/
Dm33.dtsi21 arm,num-irq-priority-bits = <4>;
/Zephyr-latest/dts/arm/nordic/
Dnrf5340_cpuapp_peripherals.dtsi119 easydma-maxcnt-bits = <16>;
137 easydma-maxcnt-bits = <16>;
160 easydma-maxcnt-bits = <16>;
178 easydma-maxcnt-bits = <16>;
196 easydma-maxcnt-bits = <16>;
214 easydma-maxcnt-bits = <16>;
232 easydma-maxcnt-bits = <16>;
255 easydma-maxcnt-bits = <16>;
273 easydma-maxcnt-bits = <16>;
Dnrf52833.dtsi149 easydma-maxcnt-bits = <16>;
168 easydma-maxcnt-bits = <16>;
185 easydma-maxcnt-bits = <16>;
204 easydma-maxcnt-bits = <16>;
296 length-field-length-8-bits;
477 easydma-maxcnt-bits = <16>;
534 easydma-maxcnt-bits = <16>;
566 arm,num-irq-priority-bits = <3>;
Dnrf52840.dtsi137 easydma-maxcnt-bits = <16>;
156 easydma-maxcnt-bits = <16>;
173 easydma-maxcnt-bits = <16>;
192 easydma-maxcnt-bits = <16>;
284 length-field-length-8-bits;
464 easydma-maxcnt-bits = <16>;
531 easydma-maxcnt-bits = <16>;
571 arm,num-irq-priority-bits = <3>;
Dnrf52832.dtsi135 easydma-maxcnt-bits = <8>;
154 easydma-maxcnt-bits = <8>;
171 easydma-maxcnt-bits = <8>;
190 easydma-maxcnt-bits = <8>;
282 length-field-length-8-bits;
455 easydma-maxcnt-bits = <8>;
491 arm,num-irq-priority-bits = <3>;
/Zephyr-latest/samples/drivers/spi_flash/boards/
Dmec172xevb_assy6906.overlay24 /* 134217728 bits = 16 Mbytes */
/Zephyr-latest/boards/intel/socfpga/agilex_socdk/
Dintel_socfpga_agilex_socdk.dts36 size = <DT_SIZE_M(256*8)>; /* in bits */
/Zephyr-latest/arch/xtensa/core/
DREADME_WINDOWS.rst31 the top two bits of the return address placed in A0.
39 top two bits from the return address in A0 and subtracts that value
40 from WINDOWBASE before returning. This is why the CALLINC bits went
52 or 16 bits wide). The bit in windowstart corresponding to WINDOWBASE
54 until cleared by a function return (by RETW, see below). Other bits
57 followed by 0, 1 or 2 zero bits that tell you how "big" (how many
73 Finally: note that hardware checks the two bits of WINDOWSTART after
/Zephyr-latest/tests/drivers/build_all/gpio/
Diproc.overlay21 arm,num-irq-priority-bits = <3>;
/Zephyr-latest/dts/arm/ti/
Dmsp432p4xx.dtsi42 arm,num-irq-priority-bits = <3>;
/Zephyr-latest/samples/subsys/ipc/rpmsg_service/
DREADME.rst46 - Data: 8 bits
48 - Stop bits: 1
97 - Data: 8 bits
99 - Stop bits: 1
/Zephyr-latest/boards/altr/max10/
Daltera_max10.dts39 size = <DT_SIZE_M(64*8)>; /* in bits */
/Zephyr-latest/boards/arduino/mkrzero/doc/
Dindex.rst94 of 24 bits or 16 bits.
121 The SAMD21 MCU has a single channel DAC with 10 bits of resolution. On the
158 - Data: 8 bits
160 - Stop bits: 1
/Zephyr-latest/dts/arm/broadcom/
Dviper-m7.dtsi31 arm,num-irq-priority-bits = <3>;
/Zephyr-latest/drivers/pwm/
Dpwm_rcar.c75 static void pwm_rcar_write_bit(const struct pwm_rcar_cfg *config, uint32_t offs, uint32_t bits, in pwm_rcar_write_bit() argument
81 reg_val |= bits; in pwm_rcar_write_bit()
83 reg_val &= ~(bits); in pwm_rcar_write_bit()
/Zephyr-latest/boards/arduino/nano_33_iot/doc/
Dindex.rst92 of 24 bits or 16 bits. If :code:`CONFIG_PWM_SAM0_TCC` is enabled then LED0 is
146 - Data: 8 bits
148 - Stop bits: 1
/Zephyr-latest/tests/drivers/spi/spi_loopback/
DKconfig17 bool "Use 16 bits frames for tests"
/Zephyr-latest/samples/drivers/mbox/
DREADME.rst30 - Data: 8 bits
32 - Stop bits: 1
/Zephyr-latest/arch/arm/core/
Dvector_table.ld16 /* VTOR bits 0:7 are reserved (RES0). This requires that the base address
21 /* VTOR bits 0:6 are reserved (RES0). This requires that the base address

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