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/Zephyr-latest/drivers/i2c/
Di2c_lpc11u6x.h71 struct lpc11u6x_i2c_regs *base; member
/Zephyr-latest/kernel/
Dipi.c54 executable_on_cpu = ((thread->base.cpu_mask & BIT(i)) != 0); in ipi_mask_create()
Dmsg_q.c148 (void)memcpy(pending_thread->base.swap_data, data, msgq->msg_size); in z_impl_k_msgq_put()
172 _current->base.swap_data = (void *) data; in z_impl_k_msgq_put()
250 (void)memcpy(msgq->write_ptr, (char *)pending_thread->base.swap_data, in z_impl_k_msgq_get()
271 _current->base.swap_data = data; in z_impl_k_msgq_get()
/Zephyr-latest/drivers/dma/
Ddma_intel_adsp_hda_host_in.c27 .base = DT_INST_REG_ADDR(inst), \
Ddma_intel_adsp_hda_host_out.c31 .base = DT_INST_REG_ADDR(inst), \
Ddma_mcux_lpc.c28 DMA_Type *base; member
71 ((DMA_Type *)((const struct dma_mcux_lpc_config *const)(dev)->config)->base)
96 data->busy = DMA_ChannelIsBusy(data->dma_handle.base, channel); in nxp_lpc_dma_callback()
711 p_handle->base->CHANNEL[p_handle->channel].CFG = cfg_reg; in dma_mcux_lpc_configure()
713 DMA_EnableChannelPeriphRq(p_handle->base, p_handle->channel); in dma_mcux_lpc_configure()
715 DMA_DisableChannelPeriphRq(p_handle->base, p_handle->channel); in dma_mcux_lpc_configure()
717 DMA_SetChannelPriority(p_handle->base, p_handle->channel, config->channel_priority); in dma_mcux_lpc_configure()
888 .base = (DMA_Type *)DT_INST_REG_ADDR(n), \
/Zephyr-latest/arch/riscv/core/
Dthread.c84 && (thread->base.user_options & K_USER)) { in arch_new_thread()
210 if ((thread->base.user_options & K_USER) != K_USER) { in arch_thread_priv_stack_space_get()
/Zephyr-latest/soc/nxp/mcx/mcxw/
Dsoc.c195 VBAT_Type *base = (VBAT_Type *)DT_REG_ADDR(DT_NODELABEL(vbat)); in vbat_init() local
205 base->STATUSA |= VBAT_STATUSA_POR_DET_MASK; in vbat_init()
/Zephyr-latest/drivers/ps2/
Dps2_npcx_controller.c47 uintptr_t base; member
71 ((struct ps2_reg *)((const struct ps2_npcx_ctrl_config *)(dev)->config)->base)
321 .base = DT_INST_REG_ADDR(0),
/Zephyr-latest/drivers/sensor/nuvoton/nuvoton_tach_npcx/
Dtach_nuvoton_npcx.c56 uintptr_t base; member
79 ((struct tach_reg *)((const struct tach_npcx_config *)(dev)->config)->base)
375 .base = DT_INST_REG_ADDR(inst), \
/Zephyr-latest/drivers/flash/
Dflash_npcx_fiu_qspi.c23 ((struct fiu_reg *)((const struct npcx_qspi_fiu_config *)(dev)->config)->base)
28 uintptr_t base; member
309 .base = DT_INST_REG_ADDR(n), \
/Zephyr-latest/arch/arm/core/mpu/
Darm_mpu.c173 region_conf.base = new_region->start; in mpu_configure_region()
312 uint32_t base = mpu_region_get_base(i); in arm_core_mpu_mem_partition_config_update() local
314 if (base != partition->start) { in arm_core_mpu_mem_partition_config_update()
/Zephyr-latest/boards/others/stm32f401_mini/doc/
Dindex.rst8 More info about the board with schematics available `here <stm32-base-board-page_>`_
111 .. _stm32-base-board-page:
112 https://stm32-base.org/boards/STM32F401CCU6-STM32-Mini-F401
/Zephyr-latest/arch/x86/
Dgen_idt.py114 base = 32 + (prio * 16)
115 return range(base, base + 16)
/Zephyr-latest/soc/nxp/s32/s32k3/
DKconfig35 The offset address from flash base address for ivt header
/Zephyr-latest/drivers/watchdog/
Dwdt_ambiq.c21 uint32_t base; member
185 .base = DT_INST_REG_ADDR(n), \
Dwdt_nxp_s32.c81 #define REG_READ(r) sys_read32(config->base + (r))
82 #define REG_WRITE(r, v) sys_write32((v), config->base + (r))
102 mem_addr_t base; member
377 .base = DT_INST_REG_ADDR(n), \
/Zephyr-latest/drivers/interrupt_controller/
Dintc_gicv3_priv.h109 #define IROUTER(base, n) (base + GIC_DIST_IROUTER + (n) * 8) argument
/Zephyr-latest/subsys/net/lib/shell/
Dping.c204 int base; in parse_arg() local
217 base = 16; in parse_arg()
219 base = 10; in parse_arg()
223 res = shell_strtol(str, base, &err); in parse_arg()
/Zephyr-latest/soc/nxp/imx/imx6sx/
Dsoc_clk_freq.c13 uint32_t get_pwm_clock_freq(PWM_Type *base) in get_pwm_clock_freq() argument
/Zephyr-latest/drivers/usb/udc/
Dudc_dwc2.h45 struct usb_dwc2_reg *const base; member
/Zephyr-latest/arch/sparc/core/
Dthread.c51 if (thread->base.user_options & USER_FP_MASK) { in arch_new_thread()
/Zephyr-latest/arch/x86/zefi/
Defi.ld12 /* Pick a reasonable base address, EFI won't load us there anyway */
/Zephyr-latest/tests/drivers/gpio/gpio_ite_it8xxx2_v2/boards/
Dnative_sim.overlay38 wuc-base = <0xf01b20 0xf01b20 0xf01b20 0xf01b1c
/Zephyr-latest/include/zephyr/bluetooth/audio/
Dbap.h1941 int bt_bap_base_get_size(const struct bt_bap_base *base);
1951 int bt_bap_base_get_pres_delay(const struct bt_bap_base *base);
1961 int bt_bap_base_get_subgroup_count(const struct bt_bap_base *base);
1972 int bt_bap_base_get_bis_indexes(const struct bt_bap_base *base, uint32_t *bis_indexes);
1985 int bt_bap_base_foreach_subgroup(const struct bt_bap_base *base,
2378 void (*base_recv)(struct bt_bap_broadcast_sink *sink, const struct bt_bap_base *base,

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