| /Zephyr-latest/subsys/bluetooth/mesh/ |
| D | access.c | 51 } base; member
1743 static int mod_rel_register(const struct bt_mesh_model *base, in mod_rel_register() argument
1749 base->rt->elem_idx, in mod_rel_register()
1750 base->rt->mod_idx + get_sig_offset(base), in mod_rel_register()
1985 if (BT_MESH_ADDR_IS_VIRTUAL(pub.base.addr)) { in mod_set_pub()
1989 mod->pub->addr = pub.base.addr; in mod_set_pub()
1990 mod->pub->key = pub.base.key; in mod_set_pub()
1991 mod->pub->cred = pub.base.cred; in mod_set_pub()
1992 mod->pub->ttl = pub.base.ttl; in mod_set_pub()
1993 mod->pub->period = pub.base.period; in mod_set_pub()
[all …]
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| /Zephyr-latest/scripts/ |
| D | requirements-base.txt | 3 # While technically west isn't required it's considered in base since it's
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| /Zephyr-latest/soc/aspeed/ast10x0/ |
| D | Kconfig | 29 The non-cached SRAM base address. The default value comes from
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| /Zephyr-latest/drivers/dma/ |
| D | dma_intel_adsp_hda.h | 26 uint32_t base; member
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| D | dma_dw.c | 98 .base = DT_INST_REG_ADDR(inst), \
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| /Zephyr-latest/boards/snps/nsim/arc_classic/support/ |
| D | mdb_vpx5.args | 95 -prop=nsim_mem-dev=uart0,kind=dwuart,base=0xf0000000,irq=24
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| D | nsim_vpx5.props | 105 nsim_mem-dev=uart0,kind=dwuart,base=0xf0000000,irq=23
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| /Zephyr-latest/modules/trusted-firmware-m/psa/ |
| D | GNUARM.cmake | 16 set(TARGET_SWITCH "-march=armv8-m.base -mcmse")
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| /Zephyr-latest/arch/arm/core/cortex_a_r/ |
| D | fault.c | 181 && (arch_current_thread()->base.user_options & K_FP_REGS)) in z_arm_fault_undef_instruction_fp()
199 arch_current_thread()->base.user_options |= K_FP_REGS; in z_arm_fault_undef_instruction_fp()
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| /Zephyr-latest/dts/arm/nxp/ |
| D | nxp_rt1010.dtsi | 123 /* Fixup LPI2C1 and LPI2C2, they have different base addr on RT1010 */
156 /* Fixup LPSPI1 and LPSPI2, they have different base addr on RT1010 */
191 /* Fixup FlexPWM1 it has different base addr and interrupt numbers on RT1010 */
246 /* Fixup USB it has different base addr and interrupt numbers on RT1010 */
276 /* Fix SAI1, 3, it has different base addr on RT1010 */
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| /Zephyr-latest/drivers/spi/ |
| D | spi_mchp_mss.c | 102 mm_reg_t base; member
119 return sys_read32(cfg->base + offset); in mss_spi_read()
124 sys_write32(val, cfg->base + offset); in mss_spi_write()
471 .base = DT_INST_REG_ADDR(n), \
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| /Zephyr-latest/drivers/counter/ |
| D | counter_nxp_s32_sys_timer.c | 47 #define REG_READ(r) sys_read32(config->base + (r))
48 #define REG_WRITE(r, v) sys_write32((v), config->base + (r))
66 mem_addr_t base; member
407 .base = DT_INST_REG_ADDR(n), \
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| /Zephyr-latest/dts/riscv/ite/ |
| D | it82xx2.dtsi | 55 wuc-base = <0xf01b20 0xf01b20 0xf01b20 0xf01b1c
81 wuc-base = <0xf01b24 0xf01b24 0xf01b1c 0xf01b24
107 wuc-base = <0xf01b1c 0xf01b28 0xf01b20 0xf01b28
133 wuc-base = <0xf01b04 0xf01b04 0xf01b04 0xf01b28
159 wuc-base = <0xf01b18 0xf01b18 0xf01b18 0xf01b18
185 wuc-base = <0xf01b24 0xf01b24 0xf01b24 0xf01b24
211 wuc-base = <0xf01b2c 0xf01b2c 0xf01b2c 0xf01b30
237 wuc-base = <0xf01b14 0xf01b14 0xf01b14 0xf01b14
263 wuc-base = <0xf01b2c 0xf01b30 0xf01b30 0xf01b30
289 wuc-base = <0xf01b34 0xf01b34 0xf01b34 0xf01b34
[all …]
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| /Zephyr-latest/drivers/i2s/ |
| D | i2s_litex.h | 96 uint32_t base; member
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| /Zephyr-latest/drivers/ethernet/eth_nxp_enet_qos/ |
| D | nxp_enet_qos_priv.h | 91 enet_qos_t *base; member
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| /Zephyr-latest/samples/subsys/sensing/simple/boards/ |
| D | native_sim.overlay | 29 base_accel_gyro: base-accel-gyro {
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| /Zephyr-latest/arch/xtensa/include/ |
| D | kernel_arch_func.h | 98 if (old_thread->base.thread_state & _THREAD_DUMMY) { in arch_cohere_stacks()
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| /Zephyr-latest/tests/subsys/sensing/boards/ |
| D | native_sim.overlay | 29 base_accel_gyro: base-accel-gyro {
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| /Zephyr-latest/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/boards/ |
| D | f0_i2c1_hsi.overlay | 45 * Aim of this part is to provide a base working clock config
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| D | f3_i2c1_hsi.overlay | 45 * Aim of this part is to provide a base working clock config
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| /Zephyr-latest/drivers/gpio/ |
| D | gpio_andes_atcgpio100.c | 56 ((const struct gpio_atcgpio100_config * const)(dev)->config)->base
84 uint32_t base; member
365 .base = DT_INST_REG_ADDR(n), \
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| D | gpio_npcx.c | 33 uintptr_t base; member
50 ((struct gpio_reg *)((const struct gpio_npcx_config *)(dev)->config)->base)
410 .base = DT_INST_REG_ADDR(inst), \
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| /Zephyr-latest/boards/others/stm32f401_mini/doc/ |
| D | index.rst | 8 More info about the board with schematics available `here <stm32-base-board-page_>`_
139 .. _stm32-base-board-page:
140 https://stm32-base.org/boards/STM32F401CCU6-STM32-Mini-F401
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| /Zephyr-latest/tests/kernel/threads/thread_stack/src/ |
| D | main.c | 104 uintptr_t base; in stack_buffer_scenarios() local
114 base = (uintptr_t)stack_obj; in stack_buffer_scenarios()
161 zassert_true(base % alignment == 0, in stack_buffer_scenarios()
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| /Zephyr-latest/drivers/pcie/host/ |
| D | vc.h | 124 uint32_t base,
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