Searched +full:xtal +full:- +full:enable +full:- +full:delay +full:- +full:ms (Results 1 – 7 of 7) sorted by relevance
/Zephyr-latest/dts/bindings/clock/ |
D | microchip,xec-pcr.yaml | 2 # SPDX-License-Identifier: Apache-2.0 6 compatible: "microchip,xec-pcr" 8 include: [clock-controller.yaml, pinctrl-device.yaml, base.yaml] 14 core-clock-div: 17 description: Divide 96 MHz PLL clock to produce Cortex-M4 core clock 19 slow-clock-div: 25 pll-32k-src: 30 periph-32k-src: 35 xtal-single-ended: 39 clk32kmon-period-min: [all …]
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/Zephyr-latest/drivers/clock_control/ |
D | clock_control_mchp_xec.c | 4 * SPDX-License-Identifier: Apache-2.0 15 #include <zephyr/dt-bindings/clock/mchp_xec_pcr.h> 30 * 32KHz period counter minimum for pass/fail: 16-bit 31 * 32KHz period counter maximum for pass/fail: 16-bit 32 * 32KHz duty cycle variation max for pass/fail: 16-bit 33 * 32KHz valid count minimum: 8-bit 99 uint32_t RSVD4[(0x00c0 - 0x0094) / 4]; 154 #define XEC_CC_VBATR_CS_SO_EN BIT(0) /* enable and start silicon OSC */ 155 #define XEC_CC_VBATR_CS_XTAL_EN BIT(8) /* enable & start external crystal */ 157 #define XEC_CC_VBATR_CS_XTAL_DHC BIT(10) /* disable high XTAL startup current */ [all …]
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/Zephyr-latest/drivers/ieee802154/ |
D | ieee802154_dw1000_regs.h | 4 * SPDX-License-Identifier: Apache-2.0 7 * https://github.com/Decawave/mynewt-dw1000-core.git 14 * Copyright (C) 2017-2018, Decawave Limited, All Rights Reserved 24 * http://www.apache.org/licenses/LICENSE-2.0 73 /* Frame Filtering Enable. This bit enables the frame filtering functionality */ 75 /* Frame Filtering Behave as a Co-ordinator */ 114 /* Receive Wait Timeout Enable. */ 117 * Receiver Auto-Re-enable. 118 * This bit is used to cause the receiver to re-enable automatically 121 /* Automatic Acknowledgement Enable */ [all …]
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/Zephyr-latest/dts/arm/microchip/ |
D | mec1501hsz.dtsi | 4 * SPDX-License-Identifier: Apache-2.0 7 #include <arm/armv7-m.dtsi> 8 #include <zephyr/dt-bindings/adc/adc.h> 9 #include <zephyr/dt-bindings/clock/mchp_xec_pcr.h> 10 #include <zephyr/dt-bindings/i2c/i2c.h> 11 #include <zephyr/dt-bindings/gpio/gpio.h> 12 #include <zephyr/dt-bindings/gpio/microchip-xec-gpio.h> 16 #address-cells = <1>; 17 #size-cells = <0>; 21 compatible = "arm,cortex-m4"; [all …]
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D | mec172x_common.dtsi | 4 * SPDX-License-Identifier: Apache-2.0 11 compatible = "microchip,xec-pcr"; 13 reg-names = "pcrr", "vbatr"; 15 core-clock-div = <1>; 17 pll-32k-src = <MCHP_XEC_PLL_CLK32K_SRC_SIL_OSC>; 18 periph-32k-src = <MCHP_XEC_PERIPH_CLK32K_SRC_SO_SO>; 19 clk32kmon-period-min = <1435>; 20 clk32kmon-period-max = <1495>; 21 clk32kmon-duty-cycle-var-max = <132>; 22 clk32kmon-valid-min = <4>; [all …]
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/Zephyr-latest/doc/releases/ |
D | release-notes-1.14.rst | 17 * CVE-2020-10066 18 * CVE-2020-10069 19 * CVE-2020-13601 20 * CVE-2020-13602 32 * :github:`issuenumber` - issue title 34 * :github:`18334` - DNS resolution is broken for some addresses in master/2.0-pre 35 * :github:`19917` - Bluetooth: Controller: Missing LL_ENC_RSP after HCI LTK Negative Reply 36 * :github:`21107` - LL_ASSERT and 'Imprecise data bus error' in LL Controller 37 * :github:`21257` - tests/net/net_pkt failed on mimxrt1050_evk board. 38 * :github:`21299` - bluetooth: Controller does not release buffer on central side after peripheral … [all …]
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D | release-notes-3.3.rst | 14 * Introduced :ref:`USB-C <usbc_api>` device stack with PD (power delivery) 17 CMSIS-DSP as the default backend. 30 * CVE-2023-0359: Under embargo until 2023-04-20 32 * CVE-2023-0779: Under embargo until 2023-04-22 51 allow disabling sync reports, and enable sync report filtering. these two 56 added to enable the PAST implementation rather than 66 removed in favor of new :dtcompatible:`zephyr,flash-disk` devicetree binding. 71 * Starting from this release ``zephyr-`` prefixed tags won't be created 75 standard logging system. To enable debugging for a particular module in the 76 Bluetooth subsystem, enable `CONFIG_BT_(module name)_LOG_LEVEL_DBG` instead of [all …]
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