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/Zephyr-latest/dts/bindings/mbox/
Dnordic,mbox-nrf-ipc.yaml2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "nordic,mbox-nrf-ipc"
8 include: [base.yaml, mailbox-controller.yaml]
11 tx-mask:
14 description: TX supported channels mask
16 rx-mask:
19 description: RX supported channels mask
24 mbox-cells:
25 - channel
Dnordic,nrf-vevif-event-tx.yaml2 # SPDX-License-Identifier: Apache-2.0
5 Nordic VEVIF (VPR Event Interface) - EVENT TX MODE
7 VEVIF provides support for inter-domain software signaling. It implements a set of events
9 When used in the event tx mode, the VEVIF events are used to trigger IRQs from VPR
17 compatible = "nordic,nrf-vevif-event-tx";
18 #mbox-cells = <1>;
20 nordic,events-mask = <0x00008000>;
24 compatible: "nordic,nrf-vevif-event-tx"
26 include: [base.yaml, mailbox-controller.yaml]
34 nordic,events-mask:
[all …]
Dnordic,nrf-vevif-task-tx.yaml2 # SPDX-License-Identifier: Apache-2.0
5 Nordic VEVIF (VPR Event Interface) - TASK TX MODE
10 VEVIF provides support for inter-domain software signaling. It implements a set of tasks
12 When used in task tx mode, the VEVIF tasks are used to trigger IRQs on VPR core.
19 compatible = "nordic,nrf-vevif-task-tx";
21 #mbox-cells = <1>;
23 nordic,tasks-mask = <0xfffffff0>;
27 compatible: "nordic,nrf-vevif-task-tx"
29 include: [base.yaml, mailbox-controller.yaml]
37 nordic,tasks-mask:
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/Zephyr-latest/drivers/sensor/tdk/icm42688/
Dicm42688_spi.c4 * SPDX-License-Identifier: Apache-2.0
24 const struct spi_buf_set tx = { in spi_write_register() local
29 return spi_write_dt(bus, &tx); in spi_write_register()
42 const struct spi_buf_set tx = { in spi_read_register() local
63 return spi_transceive_dt(bus, &tx, &rx); in spi_read_register()
76 int icm42688_spi_update_register(const struct spi_dt_spec *bus, uint16_t reg, uint8_t mask, in icm42688_spi_update_register() argument
86 temp &= ~mask; in icm42688_spi_update_register()
87 temp |= FIELD_PREP(mask, data); in icm42688_spi_update_register()
/Zephyr-latest/drivers/ethernet/phy/
Dphy_dm8806_priv.h4 * SPDX-License-Identifier: Apache-2.0
9 /* 10 Mbit/s transfer with half duplex mask. */
11 /* 10 Mbit/s transfer with full duplex mask. */
13 /* 100 Mbit/s transfer with half duplex mask. */
15 /* 100 Mbit/s transfer with full duplex mask. */
38 /* Speed and duplex mode staus mask. */
40 /* Link status mask. */
53 /* Address Table Command Result flag mask */
78 /* Port number or port map mask*/
114 /* Interrupt Mask & Control Register PHY Address. */
[all …]
/Zephyr-latest/drivers/ieee802154/
Dieee802154_rf2xx_iface.c1 /* ieee802154_rf2xx_iface.c - ATMEL RF2XX IEEE 802.15.4 Interface */
4 * Copyright (c) 2019-2020 Gerson Fernando Budke
6 * SPDX-License-Identifier: Apache-2.0
29 const struct rf2xx_config *conf = dev->config; in rf2xx_iface_phy_rst()
32 gpio_pin_set_dt(&conf->reset_gpio, 0); in rf2xx_iface_phy_rst()
33 gpio_pin_set_dt(&conf->slptr_gpio, 0); in rf2xx_iface_phy_rst()
38 gpio_pin_set_dt(&conf->reset_gpio, 1); in rf2xx_iface_phy_rst()
40 gpio_pin_set_dt(&conf->reset_gpio, 0); in rf2xx_iface_phy_rst()
44 const struct rf2xx_config *conf = dev->config; in rf2xx_iface_phy_tx_start()
46 /* Start TX transmission at rise edge */ in rf2xx_iface_phy_tx_start()
[all …]
Dieee802154_dw1000_regs.h4 * SPDX-License-Identifier: Apache-2.0
7 * https://github.com/Decawave/mynewt-dw1000-core.git
14 * Copyright (C) 2017-2018, Decawave Limited, All Rights Reserved
24 * http://www.apache.org/licenses/LICENSE-2.0
69 /* Access mask to SYS_CFG_ID */
75 /* Frame Filtering Behave as a Co-ordinator */
110 /* Disable Smart TX Power control */
117 * Receiver Auto-Re-enable.
118 * This bit is used to cause the receiver to re-enable automatically
126 /* System Time Counter (40-bit) */
[all …]
/Zephyr-latest/drivers/sensor/st/lsm6dsl/
Dlsm6dsl_spi.c1 /* lsm6dsl_spi.c - SPI routines for LSM6DSL driver
7 * SPDX-License-Identifier: Apache-2.0
26 const struct lsm6dsl_config *cfg = dev->config; in lsm6dsl_raw_read()
32 const struct spi_buf_set tx = { in lsm6dsl_raw_read() local
53 return -EIO; in lsm6dsl_raw_read()
56 if (spi_transceive_dt(&cfg->bus_cfg.spi, &tx, &rx)) { in lsm6dsl_raw_read()
57 return -EIO; in lsm6dsl_raw_read()
66 const struct lsm6dsl_config *cfg = dev->config; in lsm6dsl_raw_write()
78 const struct spi_buf_set tx = { in lsm6dsl_raw_write() local
85 return -EIO; in lsm6dsl_raw_write()
[all …]
/Zephyr-latest/drivers/sensor/adi/adxl372/
Dadxl372_spi.c1 /* adxl372_spi.c - SPI routines for ADXL372 driver
7 * SPDX-License-Identifier: Apache-2.0
24 const struct adxl372_dev_config *config = dev->config; in adxl372_bus_access()
36 struct spi_buf_set tx = { in adxl372_bus_access() local
46 tx.count = 1; in adxl372_bus_access()
48 return spi_transceive_dt(&config->spi, &tx, &rx); in adxl372_bus_access()
51 tx.count = 2; in adxl372_bus_access()
53 return spi_write_dt(&config->spi, &tx); in adxl372_bus_access()
81 uint32_t mask, in adxl372_spi_reg_write_mask() argument
92 tmp &= ~mask; in adxl372_spi_reg_write_mask()
[all …]
/Zephyr-latest/drivers/sensor/adi/adxl367/
Dadxl367_spi.c1 /* adxl367_spi.c - SPI routines for ADXL367 driver
7 * SPDX-License-Identifier: Apache-2.0
22 const struct adxl367_dev_config *config = dev->config; in adxl367_bus_access()
45 struct spi_buf_set tx = { in adxl367_bus_access() local
55 tx.count = 1; in adxl367_bus_access()
57 return spi_transceive_dt(&config->spi, &tx, &rx); in adxl367_bus_access()
60 tx.count = 2; in adxl367_bus_access()
62 return spi_write_dt(&config->spi, &tx); in adxl367_bus_access()
90 uint32_t mask, in adxl367_spi_reg_write_mask() argument
101 tmp &= ~mask; in adxl367_spi_reg_write_mask()
[all …]
/Zephyr-latest/drivers/serial/
Duart_xlnx_ps.c1 /* uart_xlnx_ps.c - Xilinx Zynq family serial driver */
6 * SPDX-License-Identifier: Apache-2.0
19 * - the following macro for the number of bytes between register addresses:
42 * Comp. Xilinx Zynq-7000 Technical Reference Manual (ug585), chap. B.33
50 #define XUARTPS_IMR_OFFSET 0x0010U /**< Interrupt Mask [12:0] */
61 #define XUARTPS_TXWM_OFFSET 0x0044U /**< TX FIFO Trigger Level [5:0] */
68 #define XUARTPS_CR_TX_DIS 0x00000020U /**< TX disabled. */
69 #define XUARTPS_CR_TX_EN 0x00000010U /**< TX enabled */
72 #define XUARTPS_CR_EN_DIS_MASK 0x0000003CU /**< Enable/disable Mask */
73 #define XUARTPS_CR_TXRST 0x00000002U /**< TX logic reset */
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Duart_mcux_flexcomm.c2 * Copyright (c) 2017, 2022-2023 NXP
4 * SPDX-License-Identifier: Apache-2.0
93 const struct mcux_flexcomm_config *config = dev->config; in mcux_flexcomm_poll_in()
94 uint32_t flags = USART_GetStatusFlags(config->base); in mcux_flexcomm_poll_in()
95 int ret = -1; in mcux_flexcomm_poll_in()
98 *c = USART_ReadByte(config->base); in mcux_flexcomm_poll_in()
108 const struct mcux_flexcomm_config *config = dev->config; in mcux_flexcomm_poll_out()
110 /* Wait until space is available in TX FIFO */ in mcux_flexcomm_poll_out()
111 while (!(USART_GetStatusFlags(config->base) & kUSART_TxFifoEmptyFlag)) { in mcux_flexcomm_poll_out()
114 USART_WriteByte(config->base, c); in mcux_flexcomm_poll_out()
[all …]
/Zephyr-latest/drivers/sensor/st/lis2dh/
Dlis2dh_spi.c1 /* ST Microelectronics LIS2DH 3-axis accelerometer driver
5 * SPDX-License-Identifier: Apache-2.0
29 const struct lis2dh_config *cfg = dev->config; in lis2dh_raw_read()
35 const struct spi_buf_set tx = { in lis2dh_raw_read() local
56 return -EIO; in lis2dh_raw_read()
63 if (spi_transceive_dt(&cfg->bus_cfg.spi, &tx, &rx)) { in lis2dh_raw_read()
64 return -EIO; in lis2dh_raw_read()
73 const struct lis2dh_config *cfg = dev->config; in lis2dh_raw_write()
85 const struct spi_buf_set tx = { in lis2dh_raw_write() local
92 return -EIO; in lis2dh_raw_write()
[all …]
/Zephyr-latest/drivers/gpio/
Dgpio_sn74hc595.c4 * SPDX-License-Identifier: Apache-2.0
46 const struct gpio_sn74hc595_config *config = dev->config; in sn74hc595_spi_write()
52 const struct spi_buf_set tx = { .buffers = tx_buf, .count = 1 }; in sn74hc595_spi_write() local
54 return spi_write_dt(&config->bus, &tx); in sn74hc595_spi_write()
67 struct gpio_sn74hc595_drv_data *drv_data = dev->data; in gpio_sn74hc595_port_get_raw()
69 k_mutex_lock(&drv_data->lock, K_FOREVER); in gpio_sn74hc595_port_get_raw()
71 *value = drv_data->output; in gpio_sn74hc595_port_get_raw()
73 k_mutex_unlock(&drv_data->lock); in gpio_sn74hc595_port_get_raw()
78 static int gpio_sn74hc595_port_set_masked_raw(const struct device *dev, uint32_t mask, in gpio_sn74hc595_port_set_masked_raw() argument
81 struct gpio_sn74hc595_drv_data *drv_data = dev->data; in gpio_sn74hc595_port_set_masked_raw()
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/Zephyr-latest/drivers/ipm/
Dipm_stm32_ipcc.c4 * SPDX-License-Identifier: Apache-2.0
24 ((const struct stm32_ipcc_mailbox_config * const)(dev)->config)->uconf.base)
53 #define IPCC_ReadReg(hipcc, reg) READ_REG(hipcc->C1##reg)
55 #define IPCC_ReadReg_SR(hipcc) READ_REG(hipcc->C1TOC2SR)
56 #define IPCC_ReadOtherInstReg_SR(hipcc) READ_REG(hipcc->C2TOC1SR)
81 #define IPCC_ReadReg(hipcc, reg) READ_REG(hipcc->C2##reg)
83 #define IPCC_ReadReg_SR(hipcc) READ_REG(hipcc->C2TOC1SR)
84 #define IPCC_ReadOtherInstReg_SR(hipcc) READ_REG(hipcc->C1TOC2SR)
104 struct stm32_ipcc_mbx_data *data = dev->data; in stm32_ipcc_mailbox_rx_isr()
105 const struct stm32_ipcc_mailbox_config *cfg = dev->config; in stm32_ipcc_mailbox_rx_isr()
[all …]
/Zephyr-latest/subsys/canbus/isotp/
DKconfig1 # ISO-TP configuration options
4 # SPDX-License-Identifier: Apache-2.0
7 bool "ISO-TP Transport [EXPERIMENTAL]"
18 module-str = ISOTP
34 Timeout for the reception of the next FC frame. ISO 15765-2: 1000ms
42 ISO 15765-2: 1000ms
50 ISO 15765-2: 1000ms
83 CAN_MAX_DLEN - 1 (for classic CAN : 8 - 1 = 7, for CAN FD : 64 - 1 = 63).
92 Each buffer will occupy CAN_MAX_DLEN - 1 byte + header (sizeof(struct net_buf))
96 bool "Buffer tx writes"
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/Zephyr-latest/drivers/ethernet/
Deth_adin2111_priv.h4 * SPDX-License-Identifier: Apache-2.0
92 /* Tx credits */
96 /* Interrupt Mask Register 0 */
98 /* Physical Layer Interrupt Mask */
101 /* Interrupt Mask Register 1 */
103 /* Mask Bit for P2_PHYINT */
105 /*!< Mask Bit for P2_RX_RDY. Generic SPI only.*/
107 /*!< Mask Bit for SPI_ERR. Generic SPI only. */
109 /*!< Mask Bit for P1_RX_RDY. Generic SPI only.*/
111 /*!< Mask Bit for TX_FRM_DONE. Generic SPI only.*/
[all …]
Deth_smsc91x_priv.h3 * SPDX-License-Identifier: Apache-2.0
20 #define TCR_PAD_EN 0x0080 /* Pad TX frames to 64 bytes */
24 #define EPHSR_TX_SUC 0x0001 /* Last TX was successful */
48 #define RPCR_DPLX 0x1000 /* Put PHY in full-duplex mode */
54 #define RPCR_LED_LINK_FDX 0x3 /* Full-duplex link detect */
56 #define RPCR_LED_ACT_ANY 0x4 /* TX or RX activity detected */
58 #define RPCR_LED_ACT_TX 0x7 /* TX activity detected */
78 #define CTR_AUTO_RELEASE 0x0800 /* Automatically release TX packets */
83 #define MMUCR_CMD_MASK GENMASK(7, 5) /* MMU command mask */
84 #define MMUCR_CMD_TX_ALLOC 1 /* Alloc TX memory (256b chunks) */
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/Zephyr-latest/drivers/usb_c/tcpc/
Ducpd_stm32_priv.h4 * SPDX-License-Identifier: Apache-2.0
17 * @brief The packet type(SOP*) consists of 2-bytes
22 * @brief The message header consists of 2-bytes
34 * @brief UCPD alert mask used for enabling alerts
43 * @brief UCPD alert mask used for clearing alerts
52 * @brief UCPD alert mask used for enabling alerts
62 * @brief UCPD alert mask used for clearing alerts
71 * @brief UCPD alert mask for all alerts
98 #define UCPD_ANASUB_TO_RP(r) ((r - 1) & 0x3)
173 * @brief States for managing TX messages
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/Zephyr-latest/include/zephyr/dt-bindings/pinctrl/
Dgecko-pinctrl-s1.h3 * SPDX-License-Identifier: Apache-2.0
10 * The whole GECKO_pin configuration information is encoded in a 32-bit bitfield
13 * - 31..24: Pin function.
14 * - 23..16: Reserved.
15 * - 15..8: Port for UART_RX/UART_TX functions.
16 * - 7..0: Pin number for UART_RX/UART_TX functions.
17 * - 15..8: Reserved for UART_LOC function.
18 * - 7..0: Loc for UART_LOC function.
28 /** Mask for the function field. */
33 /** Mask for the pin field. */
[all …]
/Zephyr-latest/drivers/dai/nxp/esai/
Desai.h4 * SPDX-License-Identifier: Apache-2.0
13 #include <zephyr/dt-bindings/dai/esai.h>
32 /* used to fetch the depth of the FIFO. If the "fifo-depth" property is
40 /* used to fetch the TX FIFO watermark value. If the "tx-fifo-watermark"
46 /* used to fetch the RX FIFO watermark value. If the "rx-fifo-watermark"
61 /* used to fetch the word width. If the "word-width" property is not specified,
76 #define _ESAI_SLOT_WORD_WIDTH_IS_VALID(width) (!(((width) - 8) % 4))
88 ((w) < 24 ? ((s) - (w) + (((w) - 8) / 4)) : ((s) < 32 ? 0x1e : 0x1f))
94 #define ESAI_WORD_ALIGNMENT(word_width) ((32 - (word_width)) / 4)
96 #define _ESAI_RX_FIFO_USAGE_EN(mask)\ argument
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/Zephyr-latest/dts/riscv/nordic/
Dnrf54l_05_10_15_cpuflpr.dtsi4 * SPDX-License-Identifier: Apache-2.0
10 /delete-node/ &cpuapp;
11 /delete-node/ &cpuapp_rram;
12 /delete-node/ &cpuapp_ppb;
13 /delete-node/ &cpuapp_sram;
17 compatible = "simple-bus";
18 interrupt-parent = <&cpuflpr_clic>;
25 compatible = "nordic,nrf-vevif-task-rx";
27 interrupt-parent = <&cpuflpr_clic>;
35 #mbox-cells = <1>;
[all …]
/Zephyr-latest/dts/bindings/serial/
Dst,stm32-uart-base.yaml2 # SPDX-License-Identifier: Apache-2.0
5 description: STM32 UART-BASE
8 - name: uart-controller.yaml
9 property-blocklist:
10 - clock-frequency
11 - name: pinctrl-device.yaml
12 - name: reset-device.yaml
13 - name: uart-controller-pin-inversion.yaml
28 single-wire:
31 Enable the single wire half-duplex communication.
[all …]
/Zephyr-latest/include/zephyr/drivers/firmware/scmi/
Dutil.h4 * SPDX-License-Identifier: Apache-2.0
44 * @idx channel index. Should be 0 for TX channels and 1 for
56 * @brief Declare a TX SCMI channel
59 * TX channel statically bound to said protocol via the "extern"
74 * @brief Declare SCMI TX/RX channels
77 * SCMI TX and RX channels statically bound to said protocol via
80 * Despite this, users should opt for this macro instead of the TX-specific
89 * @brief Declare SCMI TX/RX channels using node instance number
100 * @brief Get a reference to a protocol's SCMI TX channel
103 * reference to an SCMI TX channel statically bound to said
[all …]
/Zephyr-latest/boards/m5stack/m5stack_core2/
Dgrove_connectors.dtsi4 * SPDX-License-Identifier: Apache-2.0
9 compatible = "grove-header";
10 #gpio-cells = <2>;
11 gpio-map-mask = <0xffffffff 0xffffffc0>;
12 gpio-map-pass-thru = <0 0x3f>;
13 gpio-map = <0 0 &gpio1 1 0>, /* D0/SCL/RX */
14 <1 0 &gpio1 0 0>; /* D1/SDA/TX */

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