Searched +full:qemu +full:- +full:system +full:- +full:arm (Results 1 – 25 of 63) sorted by relevance
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| /Zephyr-latest/boards/qemu/cortex_m3/doc/ |
| D | index.rst | 6 This board configuration will use QEMU to emulate the TI LM3S6965 platform.
8 This configuration provides support for an ARM Cortex-M3 CPU and these devices:
11 * System Tick System Clock
16 with an actual ti_lm3s6965 hardware system, or any other hardware system.
25 +--------------+------------+----------------------+
28 | NVIC | on-chip | nested vectored |
30 +--------------+------------+----------------------+
31 | Stellaris | on-chip | serial port |
33 +--------------+------------+----------------------+
34 | SYSTICK | on-chip | system clock |
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| /Zephyr-latest/boards/qemu/cortex_m0/doc/ |
| D | index.rst | 6 This board configuration will use QEMU to emulate the
9 This configuration provides support for an ARM Cortex-M0 CPU and these devices:
12 * TIMER (nRF TIMER System Clock)
16 with an actual nRF51 Microbit hardware system, or any other hardware system.
25 +--------------+------------+----------------------+
28 | NVIC | on-chip | nested vectored |
30 +--------------+------------+----------------------+
31 | nRF | on-chip | serial port |
33 +--------------+------------+----------------------+
34 | nRF TIMER | on-chip | system clock |
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| /Zephyr-latest/doc/connectivity/networking/ |
| D | networking_with_host.rst | 3 Networking with the host system
21 exchange data with the host system like a Linux desktop computer.
25 * QEMU using SLIP (Serial Line Internet Protocol).
27 * Here IP packets are exchanged between Zephyr and the host system via serial
31 * QEMU using built-in Ethernet driver.
33 * Here IP packets are exchanged between Zephyr and the host system via QEMU's
34 built-in Ethernet driver. Not all QEMU boards support built-in Ethernet so
38 * QEMU using SLIRP (Qemu User Networking).
40 * QEMU User Networking is implemented using "slirp", which provides a full TCP/IP
41 stack within QEMU and uses that stack to implement a virtual NAT'd network. As
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| /Zephyr-latest/boards/qemu/cortex_a53/doc/ |
| D | index.rst | 6 This board configuration will use QEMU to emulate a generic Cortex-A53 hardware
9 This configuration provides support for an ARM Cortex-A53 CPU and these
12 * GIC-400 interrupt controller
13 * ARM architected timer
23 +--------------+------------+----------------------+
26 | GIC | on-chip | interrupt controller |
27 +--------------+------------+----------------------+
28 | PL011 UART | on-chip | serial port |
29 +--------------+------------+----------------------+
30 | ARM TIMER | on-chip | system clock |
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| /Zephyr-latest/boards/qemu/cortex_r5/doc/ |
| D | index.rst | 6 This board configuration will use QEMU to emulate the Xilinx Zynq UltraScale+
9 This configuration provides support for an ARM Cortex-R5 CPU and these devices:
11 * ARM PL-390 Generic Interrupt Controller
17 with an actual ZCU102 hardware system, or any other hardware system.
26 +--------------+------------+----------------------+
29 | GIC | on-chip | generic interrupt |
31 +--------------+------------+----------------------+
32 | TTC | on-chip | system timer |
33 +--------------+------------+----------------------+
34 | UART | on-chip | serial port |
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| /Zephyr-latest/boards/qemu/nios2/doc/ |
| D | index.rst | 6 This board configuration will use QEMU to emulate the Altera MAX 10 platform.
8 This configuration provides support for an Altera Nios-II CPU and these devices:
16 with an actual ti_lm3s6965 hardware system, or any other hardware system.
25 +--------------+------------+----------------------+
28 | IIC | on-chip | Internal interrupt |
30 +--------------+------------+----------------------+
31 | NS16550 | on-chip | serial port |
33 +--------------+------------+----------------------+
34 | TIMER | on-chip | system clock |
35 +--------------+------------+----------------------+
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| /Zephyr-latest/doc/develop/debug/ |
| D | index.rst | 11 This section is a quick hands-on reference to start debugging your
12 application with QEMU. Most content in this section is already covered in
13 `QEMU`_ and `GNU_Debugger`_ reference manuals.
15 .. _QEMU: http://wiki.qemu.org/Main_Page
23 The simplest way to debug an application running in QEMU is using the GNU
24 Debugger and setting a local GDB server in your development system through QEMU.
27 debugging purposes. The build system generates the image in the build
37 QEMU instance with the processor halted at startup and with a GDB server
40 Running QEMU directly
43 You can run QEMU to listen for a "gdb connection" before it starts executing any
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| /Zephyr-latest/soc/ti/lm3s6965/ |
| D | soc.h | 2 * Copyright (c) 2013-2015 Wind River Systems, Inc.
4 * SPDX-License-Identifier: Apache-2.0
9 * @brief Board configuration macros for the QEMU for arm platform
11 * This header file is used to specify and describe board-level aspects for
12 * the 'QEMU' platform.
21 /* default system clock */
|
| /Zephyr-latest/doc/develop/ |
| D | beyond-GSG.rst | 1 .. _beyond-gsg:
6 The :ref:`getting_started` gives a straight-forward path to set up
11 .. _python-pip:
21 Depending on your operating system, you may need to provide the
22 ``--user`` flag to the ``pip3`` command when installing new packages. This is
25 information about pip\ [#pip]_, including `information on -\\-user`_.
27 - On Linux, make sure ``~/.local/bin`` is at the front of your :envvar:`PATH`
28 :ref:`environment variable <env_vars>`, or programs installed with ``--user``
29 won't be found. Installing with ``--user`` avoids conflicts between pip
30 and the system package manager, and is the default on Debian-based
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| /Zephyr-latest/boards/arm/mps3/doc/ |
| D | index.rst | 3 ARM MPS3
12 - Nested Vectored Interrupt Controller (NVIC)
13 - System Tick System Clock (SYSTICK)
14 - Cortex-M System Design Kit GPIO
15 - Cortex-M System Design Kit UART
16 - Ethos-U55 NPU
17 - AN547 and AN552 support Arm Cortex-M55 CPU
18 - AN555 support Arm Cortex-M85 CPU
22 :alt: ARM MPS3
24 `Corstone-300 FVP`_/`Corstone-310 FVP`_ (Fixed Virtual Platforms) is a complete
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| /Zephyr-latest/arch/common/ |
| D | Kconfig | 4 # SPDX-License-Identifier: Apache-2.0
7 bool "Semihosting support for ARM and RISC-V targets"
8 depends on ARM || ARM64 || RISCV
10 Semihosting is a mechanism that enables code running on an ARM or
11 RISC-V target to communicate and use the Input/Output facilities on
14 https://developer.arm.com/documentation/dui0471/m/what-is-semihosting-
15 https://github.com/riscv/riscv-semihosting-spec/blob/main/riscv-semihosting-spec.adoc
16 This option is compatible with hardware and with QEMU, through the
17 (automatic) use of the -semihosting-config switch when invoking it.
28 bool "ARM MPU Support"
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| /Zephyr-latest/boards/qemu/kvm_arm64/doc/ |
| D | index.rst | 6 This board configuration will use QEMU to run a KVM guest on an AArch64
9 This configuration provides support for an AArch64 Cortex-A CPU and these
13 * ARM architected timer
23 +--------------+------------+----------------------+
26 | GIC | on-chip | interrupt controller |
27 +--------------+------------+----------------------+
28 | PL011 UART | on-chip | serial port |
29 +--------------+------------+----------------------+
30 | ARM TIMER | on-chip | system clock |
31 +--------------+------------+----------------------+
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| /Zephyr-latest/tests/arch/arm/arm_no_multithreading/ |
| D | README.txt | 1 Title: Test to verify the no multithreading use-case (ARM Only)
7 ARM Cortex-M targets. In detail the test verifies that
8 - system boots to main()
9 - PSP points to the main stack
10 - PSPLIM is set to the main stack base (if applicable)
11 - FPU state is reset (if applicable)
12 - Interrupts are enabled when switching to main()
13 - Interrupts may be registered and serviced
14 - Activating PendSV triggers a Reserved Exception error
16 ---------------------------------------------------------------------------
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| /Zephyr-latest/samples/tfm_integration/tfm_ipc/ |
| D | README.rst | 1 .. zephyr:code-sample:: tfm_ipc
2 :name: TF-M IPC
4 Implement communication between the secure and non-secure images using IPC.
9 This is a simple TF-M integration example that can be used with an ARMv8-M
12 It uses **IPC Mode** for communication, where TF-M API calls are made to the
16 Zephyr uses Trusted Firmware (TF-M) Platform Security Architecture (PSA) APIs
18 non-secure configuration.
20 The sample prints test info to the console either as a single-thread or
21 multi-thread application.
23 The sample reboots after 5 seconds to demonstrate rebooting with TF-M.
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| /Zephyr-latest/boards/arm/mps2/doc/ |
| D | mps2_armv7m.rst | 3 ARM V2M MPS2 Armv7-m (AN385/AN386/AN500)
10 the mps2 Armv7-m based board targets supported in Zephyr. This document
11 provides details about the support provided for these three Armv7-m mps2 board targets
14 - Nested Vectored Interrupt Controller (NVIC)
15 - System Tick System Clock (SYSTICK)
16 - Cortex-M System Design Kit UART
20 :alt: ARM V2M MPS2
29 - AN385 can be found at `Application Note AN385`_
30 - AN386 can be found at `Application Note AN386`_
31 - AN500 can be found at `Application Note AN500`_
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| /Zephyr-latest/tests/arch/arm/arm_thread_swap/ |
| D | README.txt | 1 Title: Test suite to verify the thread-swap (context-switch) and system-calls
2 mechanisms (ARM Only)
6 Thread-swap test:
8 This test verifies that the ARM thread context-switch mechanism
10 - the callee-saved registers are saved and restored, properly,
11 at thread swap-out and swap-in, respectively
12 - the floating-point callee-saved registers are saved and
13 restored, properly, at thread swap-out and swap-in, respectively,
14 when the thread is using the floating-point registers
15 - the thread execution priority (BASEPRI) is saved and restored,
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| /Zephyr-latest/doc/releases/ |
| D | release-notes-1.7.rst | 10 nano- and micro-kernel APIs found in the 1.5.0 release and earlier.
19 Device tree support for ARM based boards added. The initial
21 support includes NXP Kinetis based SoCs, ARM Beetle, TI CC3200 LaunchXL, and
42 * ARM: Added support for device tree
43 * ARM: Fixed exception priority access on Cortex M0(+)
44 * ARM: Refactored to use CMSIS
49 * Added ARM MPS2_AN385 board
52 * Added NXP FRDM-KW41Z board
53 * Added ST Nucleo-F334R8, Nucleo-L476G, STM3210C-EVAL, and STM32373C-EVAL boards
56 * Added Qemu target for RISC V and a simulator target for the Xtensa architecture.
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| D | release-notes-1.5.rst | 7 1.5.0. This is the first release to follow the 3-month release cadence.
13 - TCP Support
14 - Integration of the Paho MQTT Library support with QoS
15 - Flash Filesystem Support
16 - Integration of the mbedTLS library for encryption
17 - Improved BR/EDR support (for L2CAP, in particular).
18 - Support for the Altera Nios II/f soft CPU architecture
25 - Added nano_fifo_put_list() APIs, which allows queuing a list of elements
27 - Removed unused memory pool structure field.
28 - Enhanced memory pool code.
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| /Zephyr-latest/tests/arch/arm/arm_irq_vector_table/src/ |
| D | arm_irq_vector_table.c | 4 * SPDX-License-Identifier: Apache-2.0
21 /* For the nRF51-based QEMU Cortex-M0 platform, the first set of consecutive
23 * the TIMER0 IRQ line, which is used by the system timer.
27 /* For nRF54L Series, use SWI00-02 interrupt lines. */
30 /* For nRF54H and nRF92 Series, use BELLBOARD_0-2 interrupt lines. */
33 /* For other nRF targets, use TIMER0-2 interrupt lines. */
88 * @details Test validates the arm irq vector table. We create a
99 printk("Test Cortex-M IRQs installed directly in the vector table\n"); in ZTEST()
113 /* the QEMU does not simulate the in ZTEST()
118 NVIC->STIR = _ISR_OFFSET + ii; in ZTEST()
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| /Zephyr-latest/doc/develop/toolchains/ |
| D | zephyr_sdk.rst | 8 as custom QEMU and OpenOCD.
11 certain conditions (for example, running tests in QEMU for some architectures).
18 * ARC (32-bit and 64-bit; ARCv1, ARCv2, ARCv3)
19 * ARM (32-bit and 64-bit; ARMv6, ARMv7, ARMv8; A/R/M Profiles)
20 * MIPS (32-bit and 64-bit)
22 * RISC-V (32-bit and 64-bit; RV32I, RV32E, RV64I)
23 * x86 (32-bit and 64-bit)
34 script. Additional OS-specific instructions are described in the sections below.
36 If no toolchain is selected, the build system looks for Zephyr SDK and uses the toolchain
41 the operating system specific instructions below) and you want automatic discovery
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| /Zephyr-latest/tests/arch/arm/arm_hardfault_validation/ |
| D | README.txt | 1 Title: Test to verify the behavior of HardFault (ARM Only)
5 This test verifies the Cortex-M HardFault escalation. Only for
6 ARM Cortex-M targets.
8 ---------------------------------------------------------------------------
12 This project outputs to the console. It can be built and executed on QEMU as
17 ---------------------------------------------------------------------------
21 Problems caused by out-dated project information can be addressed by
28 # and restore pre-defined configuration info
30 ---------------------------------------------------------------------------
34 *** Booting Zephyr OS build zephyr-v2.6.0-482-g9daa69b212cd ***
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| /Zephyr-latest/dts/arm64/qemu/ |
| D | qemu-virt-arm64.dtsi | 4 * SPDX-License-Identifier: Apache-2.0
10 * qemu-system-aarch64 -machine virt,gic-version=host,accel=kvm
11 * -cpu cortex-a53 -nographic -machine dumpdtb=virt.dtb
13 * dtc -I dtb -O dts virt.dtb
17 #include <arm64/armv8-a.dtsi>
18 #include <zephyr/dt-bindings/interrupt-controller/arm-gic.h>
19 #include <zephyr/dt-bindings/pcie/pcie.h>
22 #address-cells = <2>;
23 #size-cells = <2>;
26 #address-cells = <1>;
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| D | qemu-virt-a53.dtsi | 4 * SPDX-License-Identifier: Apache-2.0
10 * qemu-system-aarch64 -machine virt -cpu cortex-a53 -nographic
11 * -machine dumpdtb=virt.dtb
13 * dtc -I dtb -O dts virt.dtb
17 #include <arm64/armv8-a.dtsi>
18 #include <zephyr/dt-bindings/interrupt-controller/arm-gic.h>
19 #include <zephyr/dt-bindings/pcie/pcie.h>
22 #address-cells = <2>;
23 #size-cells = <2>;
26 #address-cells = <1>;
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| /Zephyr-latest/doc/develop/getting_started/ |
| D | installation_linux.rst | 25 Update Your Operating System
28 Ensure your host system is up to date.
32 .. group-tab:: Ubuntu
34 .. code-block:: console
36 sudo apt-get update
37 sudo apt-get upgrade
39 .. group-tab:: Fedora
41 .. code-block:: console
45 .. group-tab:: Clear Linux
47 .. code-block:: console
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| /Zephyr-latest/samples/tfm_integration/psa_protected_storage/ |
| D | README.rst | 1 .. zephyr:code-sample:: psa_protected_storage
2 :name: TF-M PSA Protected Storage
12 optional authentication and rollback protection. The default crypto algorithm is ``AES-128-GCM``.
16 Using the PS API, this sample stores data to non-volatile storage. The sample shows how data can
19 TF-M includes a maximum number of PS records, set via ``PS_NUM_ASSETS`` (default 10 as of
20 TF-M 1.3.0), and a maximum record size, set via ``PS_MAX_ASSET_SIZE`` (default of 2048 as of
21 TF-M 1.3.0). These defaults may be different depending on the platform being used, the current
22 value will be printed by the build system during the TF-M compilation step.
25 Secure Storage API: https://developer.arm.com/architectures/architecture-security-features/platform…
27 This sample is available for platforms that are supported in the trusted-firmware-m repo:
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