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/Zephyr-latest/drivers/pinctrl/
Dpinctrl_b91.c4 * SPDX-License-Identifier: Apache-2.0
9 #include <zephyr/dt-bindings/pinctrl/b91-pinctrl.h>
17 * gpio_en: PORT_A[0-7]
18 * gpio_en + 1*8: PORT_B[0-7]
19 * gpio_en + 2*8: PORT_C[0-7]
20 * gpio_en + 3*8: PORT_D[0-7]
21 * gpio_en + 4*8: PORT_E[0-7]
22 * gpio_en + 5*8: PORT_F[0-7]
24 #define reg_gpio_en(pin) (*(volatile uint8_t *)((uint32_t)DT_INST_REG_ADDR_BY_NAME(0, gpio_en) + \ argument
25 ((pin >> 8) * 8)))
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/Zephyr-latest/dts/bindings/pinctrl/
Dti,k3-pinctrl.yaml2 # SPDX-License-Identifier: Apache-2.0
7 Pins can be configured using the following macro "K3_PINMUX(offset, value, mux_mode)".
8 offset - the pin attribute register offset from the base address.
9 value - one of the following:
16 mux_mode - The mux mode for the pin, MUX_MODE_0 -> MUX_MODE_9.
18 The default UART0_RX pin is located at 0x000f41c8 (mux mode 0).
21 compatible: "ti,k3-pinctrl"
29 child-binding:
32 pin configuration.
39 TI K3 pin configuration.
Dnuvoton,npcx-pinctrl.yaml2 # SPDX-License-Identifier: Apache-2.0
5 The Nuvoton pin controller is a singleton node responsible for controlling
6 pin function selection and pin properties. For example, you can use these
7 nodes to select peripheral pin functions.
9 Here is a list of supported standard pin properties:
10 - bias-pull-down: Enable pull-down resistor.
11 - bias-pull-up: Enable pull-up resistor.
12 - drive-open-drain: Output driver is open-drain.
14 Custom pin properties for npcx series are available also:
15 - pinmux-locked: Lock pinmux configuration for peripheral device
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/Zephyr-latest/drivers/pinctrl/renesas/rcar/
Dpfc_rcar.c2 * Copyright (c) 2021-2023 IoT.bzh
4 * SPDX-License-Identifier: Apache-2.0
43 /* POC Control Register can control IO voltage level that is supplied to the pin */
45 uint32_t offset; member
68 /* Set the pin either in gpio or peripheral */
70 uint16_t pin, bool peripheral) in pfc_rcar_set_gpsr() argument
74 uint8_t bank = pin / 32; in pfc_rcar_set_gpsr()
79 uint8_t bit = pin % 32; in pfc_rcar_set_gpsr()
95 uint16_t reg_offs = PFC_RCAR_IPSR + rcar_func->bank * sizeof(uint32_t); in pfc_rcar_set_ipsr()
98 val &= ~(0xFU << rcar_func->shift); in pfc_rcar_set_ipsr()
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/Zephyr-latest/include/zephyr/dt-bindings/pinctrl/
Dsilabs-pinctrl-dbus.h3 * SPDX-License-Identifier: Apache-2.0
9 #include <zephyr/dt-bindings/dt-util.h>
12 * Silabs Series 2 DBUS configuration is encoded in a 32-bit bitfield organized as follows:
15 * 28..24: Route register offset in words from peripheral config (offset of <fun>ROUTE
17 * 23..19: Enable bit (offset into ROUTEEN register for given function)
18 * 18 : Enable bit presence (some inputs are auto-enabled)
19 * 17..8 : Peripheral config offset in words from DBUS base within GPIO (offset of <periph>ROUTE[n]
20 * register in GPIO_TypeDef minus offset of first route register [DBGROUTEPEN, 0x440])
21 * 7..4 : GPIO pin
32 #define SILABS_DBUS(port, pin, periph_base, en_present, en_bit, route) \ argument
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/Zephyr-latest/drivers/gpio/
Dgpio_dw.c4 * SPDX-License-Identifier: Apache-2.0
13 #include <zephyr/dt-bindings/gpio/snps-designware-gpio.h>
38 static inline uint32_t dw_read(uint32_t base_addr, uint32_t offset) in dw_read() argument
40 return sys_in32(base_addr + offset); in dw_read()
43 static inline void dw_write(uint32_t base_addr, uint32_t offset, in dw_write() argument
46 sys_out32(val, base_addr + offset); in dw_write()
49 static void dw_set_bit(uint32_t base_addr, uint32_t offset, in dw_set_bit() argument
53 sys_io_clear_bit(base_addr + offset, bit); in dw_set_bit()
55 sys_io_set_bit(base_addr + offset, bit); in dw_set_bit()
59 static inline uint32_t dw_read(uint32_t base_addr, uint32_t offset) in dw_read() argument
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Dgpio_stellaris.c4 * SPDX-License-Identifier: Apache-2.0
34 #define GPIO_REG_ADDR(base, offset) (base + offset) argument
36 #define GPIO_RW_ADDR(base, offset, p) \ argument
37 (GPIO_REG_ADDR(base, offset) | (1 << (p + 2)))
39 #define GPIO_RW_MASK_ADDR(base, offset, mask) \ argument
40 (GPIO_REG_ADDR(base, offset) | (mask << 2))
56 const struct gpio_stellaris_config * const cfg = dev->config; in gpio_stellaris_isr()
57 struct gpio_stellaris_runtime *context = dev->data; in gpio_stellaris_isr()
58 uint32_t base = cfg->base; in gpio_stellaris_isr()
61 gpio_fire_callbacks(&context->cb, dev, int_stat); in gpio_stellaris_isr()
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Dgpio_ambiq.c5 * SPDX-License-Identifier: Apache-2.0
24 uint32_t offset; member
36 static int ambiq_gpio_pin_configure(const struct device *dev, gpio_pin_t pin, gpio_flags_t flags) in ambiq_gpio_pin_configure() argument
38 const struct ambiq_gpio_config *const dev_cfg = dev->config; in ambiq_gpio_pin_configure()
42 pin += dev_cfg->offset; in ambiq_gpio_pin_configure()
74 am_hal_gpio_state_write(pin, AM_HAL_GPIO_OUTPUT_SET); in ambiq_gpio_pin_configure()
78 am_hal_gpio_state_write(pin, AM_HAL_GPIO_OUTPUT_CLEAR); in ambiq_gpio_pin_configure()
81 pin += (dev_cfg->offset >> 2); in ambiq_gpio_pin_configure()
113 am_hal_gpio_state_write(pin, AM_HAL_GPIO_OUTPUT_SET); in ambiq_gpio_pin_configure()
117 am_hal_gpio_state_write(pin, AM_HAL_GPIO_OUTPUT_CLEAR); in ambiq_gpio_pin_configure()
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Dgpio_intel.c2 * Copyright (c) 2018-2019 Intel Corporation
4 * SPDX-License-Identifier: Apache-2.0
17 * Due to GPIO callback only allowing 32 pins (as a 32-bit mask) at once,
18 * each set is further sub-divided into multiple devices, so
30 #include <zephyr/dt-bindings/interrupt-controller/intel-ioapic.h>
92 ((const struct gpio_intel_config *)(_dev)->config)
93 #define DEV_DATA(_dev) ((struct gpio_intel_data *)(_dev)->data)
130 #define REG_GPI_INT_STS_BASE_GET(data) (data)->intr_stat_reg
132 #define REG_GPI_INT_EN_BASE_GET(data) (data)->intr_stat_reg + 0x20
136 #define GPIO_PAD_OWNERSHIP_GET(data, pin, offset) (data)->pad_owner_reg + (((pin) / 8) * 0x4) argument
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Dgpio_brcmstb.c4 * SPDX-License-Identifier: Apache-2.0
18 #define DEV_CFG(dev) ((const struct gpio_brcmstb_config *)(dev)->config)
19 #define DEV_DATA(dev) ((struct gpio_brcmstb_data *)(dev)->data)
25 mem_addr_t offset; member
35 static int gpio_brcmstb_pin_configure(const struct device *port, gpio_pin_t pin, gpio_flags_t flags) in gpio_brcmstb_pin_configure() argument
37 struct gpio_brcmstb_data *data = port->data; in gpio_brcmstb_pin_configure()
40 return -ENOTSUP; in gpio_brcmstb_pin_configure()
44 sys_set_bit(data->base + GIO_IODIR, pin); in gpio_brcmstb_pin_configure()
46 sys_clear_bit(data->base + GIO_IODIR, pin); in gpio_brcmstb_pin_configure()
49 sys_set_bit(data->base + GIO_DATA, pin); in gpio_brcmstb_pin_configure()
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Dgpio_bcm2711.c3 * SPDX-License-Identifier: Apache-2.0
42 #define DEV_CFG(dev) ((const struct gpio_bcm2711_config *const)(dev)->config)
43 #define DEV_DATA(dev) ((struct gpio_bcm2711_data *const)(dev)->data)
45 #define RPI_PIN_NUM(dev, n) (DEV_CFG(dev)->offset + n)
56 uint8_t offset; member
69 static int gpio_bcm2711_pin_configure(const struct device *port, gpio_pin_t pin, gpio_flags_t flags) in gpio_bcm2711_pin_configure() argument
77 return -ENOTSUP; in gpio_bcm2711_pin_configure()
82 group = GPIO_REG_GROUP(RPI_PIN_NUM(port, pin), FSEL_GROUPS); in gpio_bcm2711_pin_configure()
83 shift = GPIO_REG_SHIFT(RPI_PIN_NUM(port, pin), FSEL_GROUPS, FSEL_BITS); in gpio_bcm2711_pin_configure()
85 regval = sys_read32(GPFSEL(data->base, group)); in gpio_bcm2711_pin_configure()
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Dgpio_lpc11u6x.c5 * SPDX-License-Identifier: Apache-2.0
27 /* Offset from syscon base address. */
37 * @note The byte and word pin registers are not included because they are
38 * not used by this driver. A 0x2000 offset is applied to skip them.
45 volatile uint32_t pin[3]; member
78 * This structure is included by all the per-port private configuration.
106 gpio_pin_t pin, gpio_flags_t flags) in gpio_lpc11u6x_pin_configure() argument
108 const struct gpio_lpc11u6x_config *config = port->config; in gpio_lpc11u6x_pin_configure()
110 (config->shared->gpio_base + LPC11U6X_GPIO_REGS); in gpio_lpc11u6x_pin_configure()
111 uint8_t port_num = config->port_num; in gpio_lpc11u6x_pin_configure()
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/Zephyr-latest/dts/bindings/display/
Dsolomon,ssd1306fb-common.yaml2 # SPDX-License-Identifier: Apache-2.0
4 include: display-controller.yaml
7 segment-offset:
10 description: 8-bit column start address for Page Addressing Mode
12 page-offset:
17 display-offset:
22 multiplex-ratio:
27 segment-remap:
31 com-invdir:
35 com-sequential:
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Distech,ist3931.yaml2 # SPDX-License-Identifier: Apache-2.0
8 include: [i2c-device.yaml, display-controller.yaml]
11 reset-gpios:
12 type: phandle-array
15 RESET pin.
17 The RESET pin of IST3931 is active low.
18 If connected directly the MCU pin should be configured
21 x-offset:
24 description: The column offset in pixels of the LCD to the controller memory
26 y-offset:
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/Zephyr-latest/dts/bindings/gpio/
Dintel,gpio.yaml1 # Copyright (c) 2018-2019 Intel Corporation
2 # SPDX-License-Identifier: Apache-2.0
8 include: [acpi.yaml, gpio-controller.yaml, base.yaml]
14 group-index:
24 pin-offset:
26 description: Pin offset of this GPIO entry
28 "#gpio-cells":
31 gpio-cells:
32 - pin
33 - flags
Dambiq,gpio-bank.yaml3 # SPDX-License-Identifier: Apache-2.0
7 compatible: "ambiq,gpio-bank"
9 include: [gpio-controller.yaml, base.yaml]
15 This property indicates the register address offset of each GPIO child node
16 under the "ambiq,gpio" parent node. The register address of pin described in
17 gpio-cells can be obtained by: base address + child address offset + (pin << 2).
19 "#gpio-cells":
22 gpio-cells:
23 - pin
24 - flags
Dambiq,gpio.yaml2 # SPDX-License-Identifier: Apache-2.0
5 Ambiq GPIO provides the GPIO pin mapping for GPIO child nodes.
8 It uses 128 continuous 32-bit registers to configure the GPIO pins.
9 This binding provides a pin mapping to solve the limitation of the maximum
13 devicetree and some child nodes which are compatible with "ambiq,gpio-bank"
21 gpio-map-mask = <0xffffffe0 0xffffffc0>;
22 gpio-map-pass-thru = <0x1f 0x3f>;
23 gpio-map = <
30 #gpio-cells = <2>;
31 #address-cells = <1>;
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/Zephyr-latest/subsys/bluetooth/controller/ll_sw/nordic/hal/nrf5/radio/
Dradio_nrf5_fem_nrf21540.h4 * SPDX-License-Identifier: Apache-2.0
10 * "nordic,nrf21540-fem".
17 * --------- --------
18 * PA pin tx-en-gpios
19 * PA offset tx-en-settle-time-us
20 * LNA pin rx-en-gpios
21 * LNA offset rx-en-settle-time-us
22 * PDN pin pdn-gpios
23 * PDN offset pdn-settle-time-us
25 * The spi-if property may point at a SPI device node representing the
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Dradio_nrf5_fem_generic.h4 * SPDX-License-Identifier: Apache-2.0
10 * "generic-fem-two-ctrl-pins".
17 * --------- --------
18 * PA pin ctx-gpios
19 * PA offset ctx-settle-time-us
20 * LNA pin crx-gpios
21 * LNA offset crx-settle-time-us
24 #define HAL_RADIO_GPIO_PA_PROP_NAME "ctx-gpios"
25 #define HAL_RADIO_GPIO_PA_OFFSET_PROP_NAME "ctx-settle-time-us"
26 #define HAL_RADIO_GPIO_LNA_PROP_NAME "crx-gpios"
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/Zephyr-latest/dts/bindings/sensor/
Dst,lis2mdl-common.yaml2 # SPDX-License-Identifier: Apache-2.0
4 include: sensor-device.yaml
7 irq-gpios:
8 type: phandle-array
9 description: IRQ pin
11 This pin defaults to active high when produced by the sensor.
15 single-mode:
21 cancel-offset:
24 Set to enable the offset cancellation. Otherwise it would be
/Zephyr-latest/dts/x86/intel/
Draptor_lake_p.dtsi3 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/interrupt-controller/intel-ioapic.h>
8 #include <zephyr/dt-bindings/pcie/pcie.h>
9 #include <zephyr/dt-bindings/gpio/gpio.h>
10 #include <zephyr/dt-bindings/i2c/i2c.h>
14 #address-cells = <1>;
15 #size-cells = <0>;
18 compatible = "intel,raptor-lake", "intel,x86_64";
20 d-cache-line-size = <64>;
33 interrupt-controller;
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Delkhart_lake.dtsi4 * SPDX-License-Identifier: Apache-2.0
8 #include <zephyr/dt-bindings/interrupt-controller/intel-ioapic.h>
9 #include <zephyr/dt-bindings/i2c/i2c.h>
10 #include <zephyr/dt-bindings/pcie/pcie.h>
14 #address-cells = <1>;
15 #size-cells = <0>;
19 compatible = "intel,elkhart-lake", "intel,x86_64";
20 d-cache-line-size = <64>;
38 #address-cells = <1>;
39 #interrupt-cells = <3>;
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Draptor_lake_s.dtsi3 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/interrupt-controller/intel-ioapic.h>
8 #include <zephyr/dt-bindings/i2c/i2c.h>
9 #include <zephyr/dt-bindings/pcie/pcie.h>
10 #include <zephyr/dt-bindings/gpio/gpio.h>
14 #address-cells = <1>;
15 #size-cells = <0>;
19 compatible = "intel,raptor-lake", "intel,x86_64";
20 d-cache-line-size = <64>;
33 #address-cells = <1>;
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/Zephyr-latest/boards/lilygo/ttgo_lora32/
Dttgo_lora32_esp32_procpu.dts4 * SPDX-License-Identifier: Apache-2.0
6 /dts-v1/;
9 #include "ttgo_lora32-pinctrl.dtsi"
10 #include <zephyr/dt-bindings/input/input-event-codes.h>
15 compatible = "lilygo,ttgo-lora32";
19 uart-0 = &uart0;
20 i2c-0 = &i2c0;
29 zephyr,shell-uart = &uart0;
31 zephyr,code-partition = &slot0_partition;
37 compatible = "gpio-leds";
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/Zephyr-latest/drivers/serial/
Duart_rpi_pico_pio.c4 * SPDX-License-Identifier: Apache-2.0
38 0x0642, /* 3: jmp x--, 2 [6] */
44 0x2020, /* 0: wait 0 pin, 0 */
47 0x0642, /* 3: jmp x--, 2 [6] */
48 0x00c8, /* 4: jmp pin, 8 */
50 0x20a0, /* 6: wait 1 pin, 0 */
58 uint32_t offset; in pio_uart_tx_init() local
62 return -EBUSY; in pio_uart_tx_init()
65 offset = pio_add_program(pio, RPI_PICO_PIO_GET_PROGRAM(uart_tx)); in pio_uart_tx_init()
75 offset + RPI_PICO_PIO_GET_WRAP_TARGET(uart_tx), in pio_uart_tx_init()
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