Lines Matching +full:pin +full:- +full:offset
5 * SPDX-License-Identifier: Apache-2.0
24 uint32_t offset; member
36 static int ambiq_gpio_pin_configure(const struct device *dev, gpio_pin_t pin, gpio_flags_t flags) in ambiq_gpio_pin_configure() argument
38 const struct ambiq_gpio_config *const dev_cfg = dev->config; in ambiq_gpio_pin_configure()
42 pin += dev_cfg->offset; in ambiq_gpio_pin_configure()
74 am_hal_gpio_state_write(pin, AM_HAL_GPIO_OUTPUT_SET); in ambiq_gpio_pin_configure()
78 am_hal_gpio_state_write(pin, AM_HAL_GPIO_OUTPUT_CLEAR); in ambiq_gpio_pin_configure()
81 pin += (dev_cfg->offset >> 2); in ambiq_gpio_pin_configure()
113 am_hal_gpio_state_write(pin, AM_HAL_GPIO_OUTPUT_SET); in ambiq_gpio_pin_configure()
117 am_hal_gpio_state_write(pin, AM_HAL_GPIO_OUTPUT_CLEAR); in ambiq_gpio_pin_configure()
121 if (am_hal_gpio_pinconfig(pin, pincfg) != AM_HAL_STATUS_SUCCESS) { in ambiq_gpio_pin_configure()
122 ret = -ENOTSUP; in ambiq_gpio_pin_configure()
129 static int ambiq_gpio_get_config(const struct device *dev, gpio_pin_t pin, gpio_flags_t *out_flags) in ambiq_gpio_get_config() argument
131 const struct ambiq_gpio_config *const dev_cfg = dev->config; in ambiq_gpio_get_config()
135 pin += dev_cfg->offset; in ambiq_gpio_get_config()
137 am_hal_gpio_pinconfig_get(pin, &pincfg); in ambiq_gpio_get_config()
168 pin += (dev_cfg->offset >> 2); in ambiq_gpio_get_config()
170 am_hal_gpio_pinconfig_get(pin, &pincfg); in ambiq_gpio_get_config()
209 const struct ambiq_gpio_config *const dev_cfg = dev->config; in ambiq_gpio_port_get_direction()
214 uint32_t pin_offset = dev_cfg->offset; in ambiq_gpio_port_get_direction()
217 for (int i = 0; i < dev_cfg->ngpios; i++) { in ambiq_gpio_port_get_direction()
228 for (int i = 0; i < dev_cfg->ngpios; i++) { in ambiq_gpio_port_get_direction()
240 uint32_t pin_offset = dev_cfg->offset >> 2; in ambiq_gpio_port_get_direction()
243 for (int i = 0; i < dev_cfg->ngpios; i++) { in ambiq_gpio_port_get_direction()
254 for (int i = 0; i < dev_cfg->ngpios; i++) { in ambiq_gpio_port_get_direction()
272 const struct ambiq_gpio_config *const dev_cfg = dev->config; in ambiq_gpio_port_get_raw()
276 pin_offset = dev_cfg->offset; in ambiq_gpio_port_get_raw()
278 pin_offset = dev_cfg->offset >> 2; in ambiq_gpio_port_get_raw()
288 const struct ambiq_gpio_config *const dev_cfg = dev->config; in ambiq_gpio_port_set_masked_raw()
290 uint32_t pin_offset = dev_cfg->offset; in ambiq_gpio_port_set_masked_raw()
292 uint32_t pin_offset = dev_cfg->offset >> 2; in ambiq_gpio_port_set_masked_raw()
294 for (int i = 0; i < dev_cfg->ngpios; i++) { in ambiq_gpio_port_set_masked_raw()
305 const struct ambiq_gpio_config *const dev_cfg = dev->config; in ambiq_gpio_port_set_bits_raw()
307 uint32_t pin_offset = dev_cfg->offset; in ambiq_gpio_port_set_bits_raw()
309 uint32_t pin_offset = dev_cfg->offset >> 2; in ambiq_gpio_port_set_bits_raw()
312 for (int i = 0; i < dev_cfg->ngpios; i++) { in ambiq_gpio_port_set_bits_raw()
323 const struct ambiq_gpio_config *const dev_cfg = dev->config; in ambiq_gpio_port_clear_bits_raw()
325 uint32_t pin_offset = dev_cfg->offset; in ambiq_gpio_port_clear_bits_raw()
327 uint32_t pin_offset = dev_cfg->offset >> 2; in ambiq_gpio_port_clear_bits_raw()
330 for (int i = 0; i < dev_cfg->ngpios; i++) { in ambiq_gpio_port_clear_bits_raw()
341 const struct ambiq_gpio_config *const dev_cfg = dev->config; in ambiq_gpio_port_toggle_bits()
343 uint32_t pin_offset = dev_cfg->offset; in ambiq_gpio_port_toggle_bits()
345 uint32_t pin_offset = dev_cfg->offset >> 2; in ambiq_gpio_port_toggle_bits()
348 for (int i = 0; i < dev_cfg->ngpios; i++) { in ambiq_gpio_port_toggle_bits()
359 const struct ambiq_gpio_config *cfg_##n = dev_##n->config; \
360 struct ambiq_gpio_data *const data_##n = dev_##n->data; \
361 uint32_t status_##n = (uint32_t)(ui64Status >> cfg_##n->offset); \
363 gpio_fire_callbacks(&data_##n->cb, dev_##n, status_##n); \
368 struct ambiq_gpio_data *const data_##n = dev_##n->data; \
369 if (pGpioIntStatusMask->U.Msk[n]) { \
370 gpio_fire_callbacks(&data_##n->cb, dev_##n, pGpioIntStatusMask->U.Msk[n]); \
392 struct ambiq_gpio_data *const data = dev->data; in ambiq_gpio_isr()
393 const struct ambiq_gpio_config *const dev_cfg = dev->config; in ambiq_gpio_isr()
395 am_hal_gpio_interrupt_irq_status_get(dev_cfg->irq_num, false, &int_status); in ambiq_gpio_isr()
396 am_hal_gpio_interrupt_irq_clear(dev_cfg->irq_num, int_status); in ambiq_gpio_isr()
398 gpio_fire_callbacks(&data->cb, dev, int_status); in ambiq_gpio_isr()
402 static int ambiq_gpio_pin_interrupt_configure(const struct device *dev, gpio_pin_t pin, in ambiq_gpio_pin_interrupt_configure() argument
405 const struct ambiq_gpio_config *const dev_cfg = dev->config; in ambiq_gpio_pin_interrupt_configure()
406 struct ambiq_gpio_data *const data = dev->data; in ambiq_gpio_pin_interrupt_configure()
411 int gpio_pin = pin + dev_cfg->offset; in ambiq_gpio_pin_interrupt_configure()
419 k_spinlock_key_t key = k_spin_lock(&data->lock); in ambiq_gpio_pin_interrupt_configure()
424 k_spin_unlock(&data->lock, key); in ambiq_gpio_pin_interrupt_configure()
428 return -ENOTSUP; in ambiq_gpio_pin_interrupt_configure()
446 irq_enable(dev_cfg->irq_num); in ambiq_gpio_pin_interrupt_configure()
448 k_spinlock_key_t key = k_spin_lock(&data->lock); in ambiq_gpio_pin_interrupt_configure()
453 k_spin_unlock(&data->lock, key); in ambiq_gpio_pin_interrupt_configure()
457 int gpio_pin = pin + (dev_cfg->offset >> 2); in ambiq_gpio_pin_interrupt_configure()
466 k_spinlock_key_t key = k_spin_lock(&data->lock); in ambiq_gpio_pin_interrupt_configure()
468 ret = am_hal_gpio_interrupt_irq_status_get(dev_cfg->irq_num, false, &int_status); in ambiq_gpio_pin_interrupt_configure()
469 ret = am_hal_gpio_interrupt_irq_clear(dev_cfg->irq_num, int_status); in ambiq_gpio_pin_interrupt_configure()
473 k_spin_unlock(&data->lock, key); in ambiq_gpio_pin_interrupt_configure()
477 return -ENOTSUP; in ambiq_gpio_pin_interrupt_configure()
489 * ERR008: GPIO: Dual-edge interrupts are not vectoring in ambiq_gpio_pin_interrupt_configure()
491 return -ENOTSUP; in ambiq_gpio_pin_interrupt_configure()
493 return -EINVAL; in ambiq_gpio_pin_interrupt_configure()
497 irq_enable(dev_cfg->irq_num); in ambiq_gpio_pin_interrupt_configure()
499 k_spinlock_key_t key = k_spin_lock(&data->lock); in ambiq_gpio_pin_interrupt_configure()
501 ret = am_hal_gpio_interrupt_irq_status_get(dev_cfg->irq_num, false, &int_status); in ambiq_gpio_pin_interrupt_configure()
502 ret = am_hal_gpio_interrupt_irq_clear(dev_cfg->irq_num, int_status); in ambiq_gpio_pin_interrupt_configure()
506 k_spin_unlock(&data->lock, key); in ambiq_gpio_pin_interrupt_configure()
515 struct ambiq_gpio_data *const data = dev->data; in ambiq_gpio_manage_callback()
517 return gpio_manage_callback(&data->cb, callback, set); in ambiq_gpio_manage_callback()
541 const struct ambiq_gpio_config *const dev_cfg = port->config; in ambiq_gpio_init()
543 NVIC_ClearPendingIRQ(dev_cfg->irq_num); in ambiq_gpio_init()
548 dev_cfg->cfg_func(); in ambiq_gpio_init()
595 .offset = DT_INST_REG_ADDR(n), \