2  * Copyright (c) 2018-2019 Intel Corporation
4  * SPDX-License-Identifier: Apache-2.0
17  * Due to GPIO callback only allowing 32 pins (as a 32-bit mask) at once,
18  * each set is further sub-divided into multiple devices, so
30 #include <zephyr/dt-bindings/interrupt-controller/intel-ioapic.h>
92 	((const struct gpio_intel_config *)(_dev)->config)
93 #define DEV_DATA(_dev) ((struct gpio_intel_data *)(_dev)->data)
130 #define REG_GPI_INT_STS_BASE_GET(data) (data)->intr_stat_reg
132 #define REG_GPI_INT_EN_BASE_GET(data) (data)->intr_stat_reg + 0x20
136 #define GPIO_PAD_OWNERSHIP_GET(data, pin, offset) (data)->pad_owner_reg + (((pin) / 8) * 0x4)  argument
138 #define REG_PAD_HOST_SW_OWNER_GET(data) (data)->host_owner_reg
144 #define GPIO_GET_PIN_MAX(dev) ((struct gpio_intel_data *)(dev)->data)->num_pins
145 #else /* Non-ACPI */
152 #define PIN_OFFSET_GET(dev) ((const struct gpio_intel_config *)(dev)->config)->pin_offset
154 #define GPIO_PAD_OWNERSHIP_GET(data, pin, offset) GPIO_PAD_OWNERSHIP(pin, offset)  argument
158 #define GPIO_BASE_GET(cdf) GPIO_BASE(((const struct gpio_intel_config *)(dev)->config))
162 #define GPIO_GET_PIN_MAX(dev) ((const struct gpio_intel_config *)(dev)->config)->num_pins
179  * @brief Check if host has permission to alter this GPIO pin.
182  * @param "uint32_t raw_pin" Raw GPIO pin
184  * @return true if host owns the GPIO pin, false otherwise
188 	struct gpio_intel_data *data = dev->data;  in check_perm()
189 	uint32_t offset, val, pin_offset;  in check_perm()  local
192 	/* First is to establish that host software owns the pin */  in check_perm()
194 	/* read the Pad Ownership register related to the pin */  in check_perm()
195 	offset = GPIO_PAD_OWNERSHIP_GET(data, raw_pin, pin_offset);  in check_perm()
197 	val = sys_read32(regs(dev) + offset);  in check_perm()
200 	offset = GPIO_OWNERSHIP_BIT(raw_pin);  in check_perm()
201 	val = (val >> offset) & PAD_OWN_MASK;  in check_perm()
208 	offset = data->pad_base + (raw_pin << 4);  in check_perm()
209 	val = sys_read32(regs(dev) + offset);  in check_perm()
235 	cfg = dev->config;  in gpio_intel_isr()
236 	data = dev->data;  in gpio_intel_isr()
242 	SYS_SLIST_FOR_EACH_CONTAINER_SAFE(&data->cb, cb, tmp, node) {  in gpio_intel_isr()
243 		cur_mask = int_sts & cb->pin_mask;  in gpio_intel_isr()
246 			__ASSERT(cb->handler, "No callback handler!");  in gpio_intel_isr()
247 			cb->handler(dev, cb, cur_mask);  in gpio_intel_isr()
256 			     gpio_pin_t pin, gpio_flags_t flags)  in gpio_intel_config()  argument
258 	struct gpio_intel_data *data = dev->data;  in gpio_intel_config()
261 	/* Only support push-pull mode */  in gpio_intel_config()
263 		return -ENOTSUP;  in gpio_intel_config()
266 	pin = k_array_index_sanitize(pin, GPIO_GET_PIN_MAX(dev) + 1);  in gpio_intel_config()
268 	raw_pin = GPIO_RAW_PIN(pin, PIN_OFFSET_GET(dev));  in gpio_intel_config()
271 		return -EINVAL;  in gpio_intel_config()
275 	reg = regs(dev) + data->pad_base + (raw_pin * PIN_OFFSET);  in gpio_intel_config()
292 		/* pin to output */  in gpio_intel_config()
294 		/* set pin output if desired */  in gpio_intel_config()
308 	/* pull-up or pull-down */  in gpio_intel_config()
329 					      gpio_pin_t pin,  in gpio_intel_pin_interrupt_configure()  argument
333 	struct gpio_intel_data *data = dev->data;  in gpio_intel_pin_interrupt_configure()
337 	/* no double-edge triggering according to data sheet */  in gpio_intel_pin_interrupt_configure()
339 		return -ENOTSUP;  in gpio_intel_pin_interrupt_configure()
342 	pin = k_array_index_sanitize(pin, GPIO_GET_PIN_MAX(dev) + 1);  in gpio_intel_pin_interrupt_configure()
344 	raw_pin = GPIO_RAW_PIN(pin, PIN_OFFSET_GET(dev));  in gpio_intel_pin_interrupt_configure()
347 		return -EINVAL;  in gpio_intel_pin_interrupt_configure()
356 	reg = regs(dev) + data->pad_base + (raw_pin * PIN_OFFSET);  in gpio_intel_pin_interrupt_configure()
377 		/* cannot enable interrupt without pin as input */  in gpio_intel_pin_interrupt_configure()
379 			return -ENOTSUP;  in gpio_intel_pin_interrupt_configure()
383 		 * Do not enable interrupt with pin as output.  in gpio_intel_pin_interrupt_configure()
390 			return -ENOTSUP;  in gpio_intel_pin_interrupt_configure()
401 		/* invert pin for active low triggering */  in gpio_intel_pin_interrupt_configure()
425 	struct gpio_intel_data *data = dev->data;  in gpio_intel_manage_callback()
427 	return gpio_manage_callback(&data->cb, callback, set);  in gpio_intel_manage_callback()
434 	struct gpio_intel_data *data = dev->data;  in port_get_raw()
435 	uint32_t pin, raw_pin, reg_addr, reg_val, cmp;  in port_get_raw()  local
445 		pin = find_lsb_set(mask) - 1;  in port_get_raw()
447 		if (pin >= GPIO_GET_PIN_MAX(dev)) {  in port_get_raw()
451 		mask &= ~BIT(pin);  in port_get_raw()
453 		raw_pin = GPIO_RAW_PIN(pin, PIN_OFFSET_GET(dev));  in port_get_raw()
459 		reg_addr = regs(dev) + data->pad_base + (raw_pin * PIN_OFFSET);  in port_get_raw()
463 			*value |= BIT(pin);  in port_get_raw()
473 	struct gpio_intel_data *data = dev->data;  in port_set_raw()
474 	uint32_t pin, raw_pin, reg_addr, reg_val;  in port_set_raw()  local
477 		pin = find_lsb_set(mask) - 1;  in port_set_raw()
479 		if (pin >= GPIO_GET_PIN_MAX(dev)) {  in port_set_raw()
483 		mask &= ~BIT(pin);  in port_set_raw()
485 		raw_pin = GPIO_RAW_PIN(pin, PIN_OFFSET_GET(dev));  in port_set_raw()
491 		reg_addr = regs(dev) + data->pad_base + (raw_pin * PIN_OFFSET);  in port_set_raw()
494 		if ((value & BIT(pin)) != 0) {  in port_set_raw()
571 	struct gpio_intel_data *data = dev->data;  in gpio_intel_acpi_enum()
578 	device_map(&data->reg_base, res.reg_base, res.len, K_MEM_CACHE_NONE);  in gpio_intel_acpi_enum()
580 	data->num_pins = res.num_pins;  in gpio_intel_acpi_enum()
581 	data->pad_owner_reg = res.pad_owner_reg;  in gpio_intel_acpi_enum()
582 	data->host_owner_reg = res.host_owner_reg;  in gpio_intel_acpi_enum()
583 	data->intr_stat_reg = res.intr_stat_reg;  in gpio_intel_acpi_enum()
584 	data->base_num = res.base_num;  in gpio_intel_acpi_enum()
585 	data->pad_base = res.pad_base;  in gpio_intel_acpi_enum()
625 	struct gpio_intel_data *data = dev->data;  in gpio_intel_dts_init()
632 	 * into 32-pin blocks so each block has a GPIO driver instance.  in gpio_intel_dts_init()
636 	 * So when mapping the address, the lowest 8-bit needs to be  in gpio_intel_dts_init()
641 	const struct gpio_intel_config *cfg = dev->config;  in gpio_intel_dts_init()
643 	device_map(&data->reg_base,  in gpio_intel_dts_init()
644 		   cfg->reg_base.phys_addr & ~0xFFU,  in gpio_intel_dts_init()
645 		   cfg->reg_base.size,  in gpio_intel_dts_init()
650 	data->pad_base = pad_base(dev);  in gpio_intel_dts_init()