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/Zephyr-latest/dts/bindings/fpga/
Dlattice,ice40-fpga-bitbang.yaml3 # SPDX-License-Identifier: Apache-2.0
7 compatible: "lattice,ice40-fpga-bitbang"
9 include: lattice,ice40-fpga-base.yaml
12 clk-gpios:
13 type: phandle-array
18 clk-gpios = <&gpio0 5 GPIO_PUSH_PULL>;
19 pico-gpios:
20 type: phandle-array
23 Peripheral-In Controller-Out GPIO input on iCE40.
25 pico-gpios = <&gpio0 7 GPIO_PUSH_PULL>;
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/Zephyr-latest/boards/st/stm32g071b_disco/
Dstm32g071b_disco.dts4 * SPDX-License-Identifier: Apache-2.0
7 /dts-v1/;
9 #include <st/g0/stm32g071r(6-8-b)tx-pinctrl.dtsi>
10 #include <zephyr/dt-bindings/sensor/ina230.h>
11 #include <zephyr/dt-bindings/input/input-event-codes.h>
15 compatible = "st,stm32g071-demo";
19 zephyr,shell-uart = &usart3;
25 compatible = "gpio-leds";
45 compatible = "gpio-keys";
74 compatible = "gpio-leds";
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/Zephyr-latest/modules/nrf_wifi/bus/
Dqspi_if.c4 * SPDX-License-Identifier: Apache-2.0
9 * Zephyr OS layer of the Wi-Fi driver.
68 * frequencies 2 - 32 MHz and the nRF53 one supports 6 - 96 MHz.
84 * the specification says that the peripheral "supports 192 MHz and 96 MHz
89 /* For requested SCK >= 96 MHz, use HFCLK192M / 1 / (2*1) = 96 MHz */
96 QSPI_IF_DEVICE_FREQUENCY) - 1)
98 /* For 96 MHz > SCK >= 48 MHz, use HFCLK192M / 2 / (2*1) = 48 MHz */
102 /* For 48 MHz > SCK >= 32 MHz, use HFCLK192M / 1 / (2*3) = 32 MHz */
106 /* For requested SCK < 32 MHz, use divider /2 for HFCLK192M. */
109 QSPI_IF_DEVICE_FREQUENCY) - 1)
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/Zephyr-latest/drivers/clock_control/
Dclock_control_mchp_xec.c4 * SPDX-License-Identifier: Apache-2.0
15 #include <zephyr/dt-bindings/clock/mchp_xec_pcr.h>
30 * 32KHz period counter minimum for pass/fail: 16-bit
31 * 32KHz period counter maximum for pass/fail: 16-bit
32 * 32KHz duty cycle variation max for pass/fail: 16-bit
33 * 32KHz valid count minimum: 8-bit
36 * HW count resolution is 48 MHz.
37 * One 32KHz clock pulse = 1464.84 48 MHz counts.
99 uint32_t RSVD4[(0x00c0 - 0x0094) / 4];
191 uint16_t period_max; /* monitor values in units of 48MHz (20.8 ns) */
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Dclock_stm32_ll_wb0.c4 * SPDX-License-Identifier: Apache-2.0
43 # error slow-clock source is not enabled
53 # error Invalid device selected as slow-clock
66 "clksys-prescaler cannot be 64 when SYSCLK source is Direct HSE");
73 /* When using HSI without PLL, the "16MHz" output is not actually 16MHz, since
75 * The CPU and MR_BLE must be running at 32MHz for MR_BLE to work with HSI.
78 "System clock frequency must be at least 32MHz to use LSI");
80 /* In PLL or Direct HSE mode, the clock is stable, so 16MHz can be used. */
82 "System clock frequency must be at least 16MHz to use LSI");
108 * NOTE: (size - 1) is required to get the correct count, in measure_lsi_frequency()
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/Zephyr-latest/drivers/ieee802154/
Dieee802154_dw1000_regs.h4 * SPDX-License-Identifier: Apache-2.0
7 * https://github.com/Decawave/mynewt-dw1000-core.git
14 * Copyright (C) 2017-2018, Decawave Limited, All Rights Reserved
24 * http://www.apache.org/licenses/LICENSE-2.0
75 /* Frame Filtering Behave as a Co-ordinator */
117 * Receiver Auto-Re-enable.
118 * This bit is used to cause the receiver to re-enable automatically
126 /* System Time Counter (40-bit) */
170 /* Transmit Pulse Repetition Frequency = 4 Mhz */
172 /* Transmit Pulse Repetition Frequency = 16 Mhz */
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Dieee802154_dw1000.c4 * SPDX-License-Identifier: Apache-2.0
79 uint8_t rx_ns_sfd; /* non-standard SFD */
81 * (tx_shr_nsync + 1 + SFD_length - rx_pac_l)
136 .rx_sfd_to = (129 + 8 - 8),
158 struct dwt_context *ctx = dev->data; in dwt_spi_read()
159 const struct dwt_hi_cfg *hi_cfg = dev->config; in dwt_spi_read()
166 .count = 1 in dwt_spi_read()
180 .count = 2 in dwt_spi_read()
187 if (spi_transceive(hi_cfg->bus.bus, ctx->spi_cfg, &tx, &rx)) { in dwt_spi_read()
189 return -EIO; in dwt_spi_read()
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/Zephyr-latest/drivers/mipi_dbi/
Dmipi_dbi_nxp_lcdic.c4 * SPDX-License-Identifier: Apache-2.0
47 /* Max reset pulse count */
153 const struct mipi_dbi_lcdic_config *config = dev->config; in mipi_dbi_lcdic_reset_state()
154 LCDIC_Type *base = config->base; in mipi_dbi_lcdic_reset_state()
156 base->CTRL &= ~LCDIC_CTRL_LCDIC_EN_MASK; in mipi_dbi_lcdic_reset_state()
158 base->CTRL |= LCDIC_CTRL_LCDIC_EN_MASK; in mipi_dbi_lcdic_reset_state()
168 const struct mipi_dbi_lcdic_config *config = dev->config; in mipi_dbi_lcdic_start_dma()
169 struct mipi_dbi_lcdic_data *data = dev->data; in mipi_dbi_lcdic_start_dma()
170 struct stream *stream = &data->dma_stream; in mipi_dbi_lcdic_start_dma()
171 uint32_t aligned_len = data->cmd_bytes & (~0x3); in mipi_dbi_lcdic_start_dma()
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/Zephyr-latest/drivers/serial/
Duart_npcx.c4 * SPDX-License-Identifier: Apache-2.0
33 /* int-mux configuration */
105 if (atomic_test_and_set_bit(data->pm_policy_state_flag, flag) == 0) { in uart_npcx_pm_policy_state_lock_get()
113 if (atomic_test_and_clear_bit(data->pm_policy_state_flag, flag) == 1) { in uart_npcx_pm_policy_state_lock_put()
124 * - 115200 in uart_set_npcx_baud_rate()
125 * - 3000000 in uart_set_npcx_baud_rate()
128 if (src_clk == MHZ(15)) { in uart_set_npcx_baud_rate()
129 inst->UPSR = 0x38; in uart_set_npcx_baud_rate()
130 inst->UBAUD = 0x01; in uart_set_npcx_baud_rate()
131 } else if (src_clk == MHZ(20)) { in uart_set_npcx_baud_rate()
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/Zephyr-latest/drivers/i2c/
Di2c_mchp_xec_v2.c5 * SPDX-License-Identifier: Apache-2.0
25 #include "i2c-priv.h"
47 /* I2C recovery bit bang delay */
49 /* I2C recovery SCL sample delay */
111 /* Recommended programming values based on 16MHz
112 * i2c_baud_clk_period/bus_clk_period - 2 = (low_period + hi_period)
113 * bus_clk_reg (16MHz/100KHz -2) = 0x4F + 0x4F
114 * (16MHz/400KHz -2) = 0x0F + 0x17
115 * (16MHz/1MHz -2) = 0x05 + 0x09
144 (const struct i2c_xec_config *const) (dev->config); in i2c_ctl_wr()
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Di2c_ll_stm32_v2.c5 * SPDX-License-Identifier: Apache-2.0
28 #include "i2c-priv.h"
39 #define STM32_I2C_SPEED_FREQ_FAST_PLUS 2U /* 1 MHz */
67 uint32_t tscldel; /* SCL delay */
68 uint32_t tsdadel; /* SDA delay */
124 const struct i2c_stm32_config *cfg = dev->config; in msg_init()
125 struct i2c_stm32_data *data = dev->data; in msg_init()
126 I2C_TypeDef *i2c = cfg->i2c; in msg_init()
129 LL_I2C_SetTransferSize(i2c, msg->len); in msg_init()
131 if (I2C_ADDR_10_BITS & data->dev_config) { in msg_init()
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/Zephyr-latest/soc/microchip/mec/mec172x/
Dsoc_espi_saf_v2.h4 * SPDX-License-Identifier: Apache-2.0
22 * poll interval is in AHB clock(48MHz) units.
25 * suspend check delay is in AHB clock(48MHz) periods.
40 * QMSPI master clock is either 96 or 48 MHz depending upon
41 * Boot-ROM OTP configuration.
70 /* QMSPI descriptors 12-15 for all SPI flash devices */
72 /* QMSPI descriptors 12-13 are exit continuous mode */
108 * QMSPI descriptors 14-15 are poll 16-bit flash status
130 /* SAF Pre-fetch optimization mode */
136 * SAF Opcode 32-bit register value.
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/Zephyr-latest/drivers/flash/
Dnrf_qspi_nor.c2 * Copyright (c) 2019-2024, Nordic Semiconductor ASA
4 * SPDX-License-Identifier: Apache-2.0
69 #error "No size specified. 'size' or 'size-in-bytes' must be set"
73 "Node " DT_NODE_PATH(DT_DRV_INST(0)) " has both size and size-in-bytes "
80 * frequencies 2 - 32 MHz and the nRF53 one supports 6 - 96 MHz.
96 * the specification says that the peripheral "supports 192 MHz and 96 MHz
101 /* For requested SCK >= 96 MHz, use HFCLK192M / 1 / (2*1) = 96 MHz */
108 INST_0_SCK_FREQUENCY) - 1)
110 /* For 96 MHz > SCK >= 48 MHz, use HFCLK192M / 2 / (2*1) = 48 MHz */
114 /* For 48 MHz > SCK >= 32 MHz, use HFCLK192M / 1 / (2*3) = 32 MHz */
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/Zephyr-latest/samples/drivers/espi/src/
Dmain.c4 * SPDX-License-Identifier: Apache-2.0
222 spi_cfg.cs.delay = 0; in spi_saf_init()
231 tx_bufs.count = 1U; in spi_saf_init()
237 rx_bufs.count = 1U; in spi_saf_init()
249 return -1; in spi_saf_init()
260 tx_bufs.count = 1U; in spi_saf_init()
266 rx_bufs.count = 1U; in spi_saf_init()
291 tx_bufs.count = 1U; in spi_saf_init()
294 rx_bufs.count = 0U; in spi_saf_init()
313 tx_bufs.count = 1U; in spi_saf_init()
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/Zephyr-latest/subsys/sd/
Dsdmmc.c4 * SPDX-License-Identifier: Apache-2.0
25 scr->flags = 0U; in sdmmc_decode_scr()
26 scr->scr_structure = (uint8_t)((raw_scr[0U] & 0xF0000000U) >> 28U); in sdmmc_decode_scr()
27 scr->sd_spec = (uint8_t)((raw_scr[0U] & 0xF000000U) >> 24U); in sdmmc_decode_scr()
29 scr->flags |= SD_SCR_DATA_STATUS_AFTER_ERASE; in sdmmc_decode_scr()
31 scr->sd_sec = (uint8_t)((raw_scr[0U] & 0x700000U) >> 20U); in sdmmc_decode_scr()
32 scr->sd_width = (uint8_t)((raw_scr[0U] & 0xF0000U) >> 16U); in sdmmc_decode_scr()
34 scr->flags |= SD_SCR_SPEC3; in sdmmc_decode_scr()
36 scr->sd_ext_sec = (uint8_t)((raw_scr[0U] & 0x7800U) >> 10U); in sdmmc_decode_scr()
37 scr->cmd_support = (uint8_t)(raw_scr[0U] & 0x3U); in sdmmc_decode_scr()
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/Zephyr-latest/drivers/adc/
Dadc_stm32.c9 * SPDX-License-Identifier: Apache-2.0
46 #include <zephyr/dt-bindings/adc/stm32_adc.h>
51 #include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
56 #include <zephyr/linker/linker-defs.h>
81 * compat st_stm32f1_adc -> STM32F1, F37x (ADC1_V2_5)
82 * compat st_stm32f4_adc -> STM32F2, F4, F7, L1
196 /* Allow ADC to create DMA request and set to one-shot mode as implemented in HAL drivers */ in adc_stm32_enable_dma_support()
213 const struct adc_stm32_cfg *config = dev->config; in adc_stm32_dma_start()
214 ADC_TypeDef *adc = config->base; in adc_stm32_dma_start()
215 struct adc_stm32_data *data = dev->data; in adc_stm32_dma_start()
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/Zephyr-latest/include/zephyr/drivers/i3c/
Dccc.h5 * SPDX-License-Identifier: Apache-2.0
117 /** Enter HDR Mode (HDR-DDR) (Broadcast) */
120 /** Enter HDR Mode 0 (HDR-DDR) (Broadcast) */
123 /** Enter HDR Mode 1 (HDR-TSP) (Broadcast) */
126 /** Enter HDR Mode 2 (HDR-TSL) (Broadcast) */
129 /** Enter HDR Mode 3 (HDR-BT) (Broadcast) */
171 /** Multi-Lane Data Transfer Control (Broadcast) */
243 * - For Write CCC, pointer to the byte array of data
244 * to be sent, which may contain the Sub-Command Byte
246 * - For Read CCC, pointer to the byte buffer for data
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/Zephyr-latest/doc/releases/
Drelease-notes-3.3.rst14 * Introduced :ref:`USB-C <usbc_api>` device stack with PD (power delivery)
17 CMSIS-DSP as the default backend.
30 * CVE-2023-0359: Under embargo until 2023-04-20
32 * CVE-2023-0779: Under embargo until 2023-04-22
66 removed in favor of new :dtcompatible:`zephyr,flash-disk` devicetree binding.
71 * Starting from this release ``zephyr-`` prefixed tags won't be created
82 image states). Use of a truncated hash or non-sha256 hash will still work
88 registration function at boot-up. If applications register this then
93 application code, these will now automatically be registered at boot-up (this
129 This may cause out-of-tree scripts or commands to fail if they have relied
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Drelease-notes-2.4.rst33 * CVE-2020-10060: UpdateHub Might Dereference An Uninitialized Pointer
34 * CVE-2020-10064: Improper Input Frame Validation in ieee802154 Processing
35 * CVE-2020-10066: Incorrect Error Handling in Bluetooth HCI core
36 * CVE-2020-10072: all threads can access all socket file descriptors
37 * CVE-2020-13598: FS: Buffer Overflow when enabling Long File Names in FAT_FS and calling fs_stat
38 * CVE-2020-13599: Security problem with settings and littlefs
39 * CVE-2020-13601: Under embargo until 2020/11/18
40 * CVE-2020-13602: Remote Denial of Service in LwM2M do_write_op_tlv
50 <https://github.com/zephyrproject-rtos/zephyr/issues?q=is%3Aissue+is%3Aopen+label%3Abug>`_.
62 * The :c:func:`wdt_feed` function will now return ``-EAGAIN`` if
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Drelease-notes-2.5.rst27 * CVE-2021-3323: Under embargo until 2021-04-14
28 * CVE-2021-3321: Under embargo until 2021-04-14
29 * CVE-2021-3320: Under embargo until 2021-04-14
39 <https://github.com/zephyrproject-rtos/zephyr/issues?q=is%3Aissue+is%3Aopen+label%3Abug>`_.
56 * Changed vcnl4040 dts binding default for property 'proximity-trigger'.
63 * The :c:func:`mqtt_keepalive_time_left` function now returns -1 if keep alive
67 timeout usage must use the new-style k_timeout_t type and not the
71 parameter, allowing to specify the maximum retransmission count of the
87 GPIO-only regulators a devicetree property ``supply-gpios`` is defined as a
101 * ARM Musca-A board and SoC support deprecated and planned to be removed in 2.6.0.
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