2  * Copyright (c) 2019-2024, Nordic Semiconductor ASA
4  * SPDX-License-Identifier: Apache-2.0
69 #error "No size specified. 'size' or 'size-in-bytes' must be set"
73 	     "Node " DT_NODE_PATH(DT_DRV_INST(0)) " has both size and size-in-bytes "
80  * frequencies 2 - 32 MHz and the nRF53 one supports 6 - 96 MHz.
96  * the specification says that the peripheral "supports 192 MHz and 96 MHz
101 /* For requested SCK >= 96 MHz, use HFCLK192M / 1 / (2*1) = 96 MHz */
108 				     INST_0_SCK_FREQUENCY) - 1)
110 /* For 96 MHz > SCK >= 48 MHz, use HFCLK192M / 2 / (2*1) = 48 MHz */
114 /* For 48 MHz > SCK >= 32 MHz, use HFCLK192M / 1 / (2*3) = 32 MHz */
118 /* For requested SCK < 32 MHz, use divider /2 for HFCLK192M. */
121 				     INST_0_SCK_FREQUENCY) - 1)
124  * setting to take effect. This value specifies the delay (in microseconds)
140 					 INST_0_SCK_FREQUENCY) - 1)
178 … "Driver only supports NONE, S1B6, S2B1v1, S2B1v4, S2B1v5 or S2B1v6 for quad-enable-requirements");
200  * If no data to transmit/receive - pass 0.
211  * @param op_code is a command value (i.e 0x9F - get Jedec ID)
229 #define QSPI_IS_SECTOR_ALIGNED(_ofs) (((_ofs) & (QSPI_SECTOR_SIZE - 1U)) == 0)
230 #define QSPI_IS_BLOCK_ALIGNED(_ofs) (((_ofs) & (QSPI_BLOCK_SIZE - 1U)) == 0)
242 		return -EINVAL;  in qspi_get_zephyr_ret_code()
244 		return -ECANCELED;  in qspi_get_zephyr_ret_code()
248 		LOG_ERR("Set the CPU clock to 64 MHz before starting QSPI operation");  in qspi_get_zephyr_ret_code()
249 		return -ECANCELED;  in qspi_get_zephyr_ret_code()
254 		return -EBUSY;  in qspi_get_zephyr_ret_code()
261 	struct qspi_nor_data *dev_data = dev->data;  in qspi_lock()
263 	k_sem_take(&dev_data->sem, K_FOREVER);  in qspi_lock()
270 	struct qspi_nor_data *dev_data = dev->data;  in qspi_unlock()
272 	k_sem_give(&dev_data->sem);  in qspi_unlock()
299 	struct qspi_nor_data *dev_data = dev->data;  in qspi_acquire()
308 	 * before calling qspi_release. Keeping count, so QSPI is deactivated  in qspi_acquire()
311 	atomic_inc(&dev_data->usage_count);  in qspi_acquire()
316 	if (!dev_data->xip_enabled) {  in qspi_acquire()
325 	struct qspi_nor_data *dev_data = dev->data;  in qspi_release()
331 	deactivate = atomic_dec(&dev_data->usage_count) == 1;  in qspi_release()
334 	if (!dev_data->xip_enabled) {  in qspi_release()
355 	struct qspi_nor_data *dev_data = dev->data;  in qspi_wait_for_completion()
359 		k_sem_take(&dev_data->sync, K_FOREVER);  in qspi_wait_for_completion()
363 		while (!dev_data->ready) {  in qspi_wait_for_completion()
367 		dev_data->ready = false;  in qspi_wait_for_completion()
376 	k_sem_give(&dev_data->sync);  in qspi_complete()
378 	dev_data->ready = true;  in qspi_complete()
408 		return -EINVAL;  in qspi_send_cmd()
415 	size_t xfer_len = sizeof(cmd->op_code);  in qspi_send_cmd()
417 	if (cmd->tx_buf) {  in qspi_send_cmd()
418 		tx_buf = cmd->tx_buf->buf;  in qspi_send_cmd()
419 		tx_len = cmd->tx_buf->len;  in qspi_send_cmd()
422 	if (cmd->rx_buf) {  in qspi_send_cmd()
423 		rx_buf = cmd->rx_buf->buf;  in qspi_send_cmd()
424 		rx_len = cmd->rx_buf->len;  in qspi_send_cmd()
429 			return -EINVAL;  in qspi_send_cmd()
440 			cmd->op_code, xfer_len);  in qspi_send_cmd()
441 		return -EINVAL;  in qspi_send_cmd()
445 		.opcode = cmd->op_code,  in qspi_send_cmd()
465 		return -EINVAL;  in qspi_rdsr()
510 		return -EINVAL;  in qspi_wrsr()
545 		return -EINVAL;  in qspi_wrsr()
575 	const struct qspi_nor_config *params = dev->config;  in qspi_erase()
586 		if (size == params->size) {  in qspi_erase()
609 			size -= adj;  in qspi_erase()
634 	const struct qspi_nor_config *dev_config = dev->config;  in configure_chip()
646 			&dev_config->nrfx_cfg.prot_if;  in configure_chip()
647 		bool qe_value = (prot_if->writeoc == NRF_QSPI_WRITEOC_PP4IO) ||  in configure_chip()
648 				(prot_if->writeoc == NRF_QSPI_WRITEOC_PP4O)  ||  in configure_chip()
649 				(prot_if->readoc == NRF_QSPI_READOC_READ4IO) ||  in configure_chip()
650 				(prot_if->readoc == NRF_QSPI_READOC_READ4O)  ||  in configure_chip()
651 				(prot_if->readoc == NRF_QSPI_READOC_READ2IO);  in configure_chip()
663 		return -EINVAL;  in configure_chip()
676 			(qe_state != qe_value) ? "updating" : "no-change");  in configure_chip()
794 	off_t flash_prefix = (WORD_SIZE - (addr % WORD_SIZE)) % WORD_SIZE;  in read_non_aligned()
800 	off_t dest_prefix = (WORD_SIZE - (off_t)dptr % WORD_SIZE) % WORD_SIZE;  in read_non_aligned()
806 	off_t flash_suffix = (size - flash_prefix) % WORD_SIZE;  in read_non_aligned()
807 	off_t flash_middle = size - flash_prefix - flash_suffix;  in read_non_aligned()
808 	off_t dest_middle = size - dest_prefix -  in read_non_aligned()
809 			    (size - dest_prefix) % WORD_SIZE;  in read_non_aligned()
813 		flash_suffix = size - flash_prefix - flash_middle;  in read_non_aligned()
835 		res = nrfx_qspi_read(buf, WORD_SIZE, addr -  in read_non_aligned()
836 				     (WORD_SIZE - flash_prefix));  in read_non_aligned()
841 		memcpy(dptr, buf + WORD_SIZE - flash_prefix, flash_prefix);  in read_non_aligned()
861 	const struct qspi_nor_config *params = dev->config;  in qspi_nor_read()
865 		return -EINVAL;  in qspi_nor_read()
868 	/* read size must be non-zero */  in qspi_nor_read()
875 	    (addr + size) > params->size) {  in qspi_nor_read()
879 		return -EINVAL;  in qspi_nor_read()
916 /* If enabled write using a stack-allocated aligned SRAM buffer as
938 				slen -= len;  in write_through_buffer()
953 	const struct qspi_nor_config *params = dev->config;  in qspi_nor_write()
957 		return -EINVAL;  in qspi_nor_write()
960 	/* write size must be non-zero, less than 4, or a multiple of 4 */  in qspi_nor_write()
963 		return -EINVAL;  in qspi_nor_write()
965 	/* address must be 4-byte aligned */  in qspi_nor_write()
967 		return -EINVAL;  in qspi_nor_write()
972 	    (addr + size) > params->size) {  in qspi_nor_write()
976 		return -EINVAL;  in qspi_nor_write()
1007 	const struct qspi_nor_config *params = dev->config;  in qspi_nor_erase()
1010 	/* address must be sector-aligned */  in qspi_nor_erase()
1012 		return -EINVAL;  in qspi_nor_erase()
1015 	/* size must be a non-zero multiple of sectors */  in qspi_nor_erase()
1017 		return -EINVAL;  in qspi_nor_erase()
1022 	    (addr + size) > params->size) {  in qspi_nor_erase()
1026 		return -EINVAL;  in qspi_nor_erase()
1047 		rc = -EIO;  in qspi_nor_write_protection_set()
1055 	const struct qspi_nor_config *dev_config = dev->config;  in qspi_init()
1060 	res = nrfx_qspi_init(&dev_config->nrfx_cfg, qspi_handler, dev->data);  in qspi_init()
1094 	if (memcmp(dev_config->id, id, SPI_NOR_MAX_ID_LEN) != 0) {  in qspi_init()
1096 			id[0], id[1], id[2], dev_config->id[0],  in qspi_init()
1097 			dev_config->id[1], dev_config->id[2]);  in qspi_init()
1098 		return -ENODEV;  in qspi_init()
1107 	const struct qspi_nor_config *dev_config = dev->config;  in qspi_nor_init()
1110 	rc = pinctrl_apply_state(dev_config->pcfg, PINCTRL_STATE_DEFAULT);  in qspi_nor_init()
1142 /* instance 0 page count */
1255 			return -EIO;  in exit_dpd()
1277 	const struct qspi_nor_config *dev_config = dev->config;  in qspi_suspend()
1283 		return -EBUSY;  in qspi_suspend()
1293 	return pinctrl_apply_state(dev_config->pcfg, PINCTRL_STATE_SLEEP);  in qspi_suspend()
1298 	const struct qspi_nor_config *dev_config = dev->config;  in qspi_resume()
1302 	rc = pinctrl_apply_state(dev_config->pcfg, PINCTRL_STATE_DEFAULT);  in qspi_resume()
1307 	res = nrfx_qspi_init(&dev_config->nrfx_cfg, qspi_handler, dev->data);  in qspi_resume()
1309 		return -EIO;  in qspi_resume()
1321 		return -EBUSY;  in qspi_nor_pm_action()
1337 		rc = -ENOTSUP;  in qspi_nor_pm_action()
1349 	struct qspi_nor_data *dev_data = dev->data;  in z_impl_nrf_qspi_nor_xip_enable()
1351 	if (dev_data->xip_enabled == enable) {  in z_impl_nrf_qspi_nor_xip_enable()
1363 	dev_data->xip_enabled = enable;  in z_impl_nrf_qspi_nor_xip_enable()