Lines Matching +full:mhz +full:- +full:delay +full:- +full:count
4 * SPDX-License-Identifier: Apache-2.0
9 * Zephyr OS layer of the Wi-Fi driver.
68 * frequencies 2 - 32 MHz and the nRF53 one supports 6 - 96 MHz.
84 * the specification says that the peripheral "supports 192 MHz and 96 MHz
89 /* For requested SCK >= 96 MHz, use HFCLK192M / 1 / (2*1) = 96 MHz */
96 QSPI_IF_DEVICE_FREQUENCY) - 1)
98 /* For 96 MHz > SCK >= 48 MHz, use HFCLK192M / 2 / (2*1) = 48 MHz */
102 /* For 48 MHz > SCK >= 32 MHz, use HFCLK192M / 1 / (2*3) = 32 MHz */
106 /* For requested SCK < 32 MHz, use divider /2 for HFCLK192M. */
109 QSPI_IF_DEVICE_FREQUENCY) - 1)
113 /* For 8 MHz, use HFCLK192M / 1 / (2*12) */
116 /* For 8 MHz, use HFCLK192M / 2 / (2*6) */
119 #error "Unsupported base clock divider for wake-up frequency."
123 * setting to take effect. This value specifies the delay (in microseconds)
142 QSPI_IF_DEVICE_FREQUENCY) - 1)
145 /* For 8 MHz, use PCLK32M / 4 */
164 * If no data to transmit/receive - pass 0.
175 * @param op_code is a command value (i.e 0x9F - get Jedec ID)
197 struct k_sem count; member
208 register int ret = -EINVAL; in qspi_get_mode()
216 __ASSERT(ret != -EINVAL, "Invalid QSPI mode"); in qspi_get_mode()
245 register int ret = -EINVAL; in qspi_get_lines_write()
264 __ASSERT(ret != -EINVAL, "Invalid QSPI write line"); in qspi_get_lines_write()
271 register int ret = -EINVAL; in qspi_get_lines_read()
293 __ASSERT(ret != -EINVAL, "Invalid QSPI read line"); in qspi_get_lines_read()
316 p_reg->IFTIMING |= qspi_cfg->RDC4IO; in _nrfx_qspi_init()
318 /* LOG_DBG("%04x : IFTIMING", p_reg->IFTIMING & qspi_cfg->RDC4IO); */ in _nrfx_qspi_init()
333 .count = Z_SEM_INITIALIZER(qspi_nor_memory_data.count, 0, K_SEM_MAX_LIMIT),
351 return -EINVAL; in qspi_get_zephyr_ret_code()
353 return -ECANCELED; in qspi_get_zephyr_ret_code()
357 LOG_ERR("Set the CPU clock to 64 MHz before starting QSPI operation"); in qspi_get_zephyr_ret_code()
358 return -ECANCELED; in qspi_get_zephyr_ret_code()
363 return -EBUSY; in qspi_get_zephyr_ret_code()
369 return dev->data; in get_dev_data()
377 k_sem_take(&dev_data->sem, K_FOREVER); in qspi_lock()
405 k_sem_give(&dev_data->sem); in qspi_unlock()
416 k_sem_take(&dev_data->trans, K_FOREVER); in qspi_trans_lock()
427 k_sem_give(&dev_data->trans); in qspi_trans_unlock()
439 k_sem_take(&dev_data->sync, K_FOREVER); in qspi_wait_for_completion()
443 while (!dev_data->ready) { in qspi_wait_for_completion()
448 dev_data->ready = false; in qspi_wait_for_completion()
457 k_sem_give(&dev_data->sync); in qspi_complete()
459 dev_data->ready = true; in qspi_complete()
465 if (!qspi_cfg->easydma) { in _qspi_complete()
473 if (!qspi_cfg->easydma) { in _qspi_wait_for_completion()
511 * before calling qspi_device_uninit. Keepping count, so QSPI is in qspi_device_init()
512 * uninitialized only at the last call (count == 0). in qspi_device_init()
515 k_sem_give(&dev_data->count); in qspi_device_init()
521 NRF_QSPI->IFTIMING |= qspi_cfg->RDC4IO; in qspi_device_init()
544 (void)k_sem_take(&dev_data->count, K_NO_WAIT); in qspi_device_uninit()
545 last = (k_sem_count_get(&dev_data->count) == 0); in qspi_device_uninit()
579 return -EINVAL; in qspi_send_cmd()
586 size_t xfer_len = sizeof(cmd->op_code); in qspi_send_cmd()
588 if (cmd->tx_buf) { in qspi_send_cmd()
589 tx_buf = cmd->tx_buf->buf; in qspi_send_cmd()
590 tx_len = cmd->tx_buf->len; in qspi_send_cmd()
593 if (cmd->rx_buf) { in qspi_send_cmd()
594 rx_buf = cmd->rx_buf->buf; in qspi_send_cmd()
595 rx_len = cmd->rx_buf->len; in qspi_send_cmd()
600 return -EINVAL; in qspi_send_cmd()
610 LOG_WRN("cinstr %02x transfer too long: %zu", cmd->op_code, xfer_len); in qspi_send_cmd()
612 return -EINVAL; in qspi_send_cmd()
616 .opcode = cmd->op_code, in qspi_send_cmd()
635 uint8_t sr = -1; in qspi_rdsr()
671 initstruct->xip_offset = 0; in qspi_fill_init_struct()
674 initstruct->skip_gpio_cfg = true, in qspi_fill_init_struct()
675 initstruct->skip_psel_cfg = true, in qspi_fill_init_struct()
678 initstruct->pins.sck_pin = QSPI_IF_BUS_SCK_PIN; in qspi_fill_init_struct()
679 initstruct->pins.csn_pin = QSPI_IF_BUS_CSN_PIN; in qspi_fill_init_struct()
680 initstruct->pins.io0_pin = QSPI_IF_BUS_IO0_PIN; in qspi_fill_init_struct()
681 initstruct->pins.io1_pin = QSPI_IF_BUS_IO1_PIN; in qspi_fill_init_struct()
683 initstruct->pins.io2_pin = QSPI_IF_BUS_IO2_PIN; in qspi_fill_init_struct()
684 initstruct->pins.io3_pin = QSPI_IF_BUS_IO3_PIN; in qspi_fill_init_struct()
686 initstruct->pins.io2_pin = NRF_QSPI_PIN_NOT_CONNECTED; in qspi_fill_init_struct()
687 initstruct->pins.io3_pin = NRF_QSPI_PIN_NOT_CONNECTED; in qspi_fill_init_struct()
691 initstruct->prot_if.addrmode = NRF_QSPI_ADDRMODE_24BIT; in qspi_fill_init_struct()
693 initstruct->prot_if.dpmconfig = false; in qspi_fill_init_struct()
696 initstruct->phy_if.sck_freq = INST_0_SCK_CFG; in qspi_fill_init_struct()
698 /* Using MHZ fails checkpatch constant check */ in qspi_fill_init_struct()
700 qspi_cfg->qspi_slave_latency = 1; in qspi_fill_init_struct()
702 initstruct->phy_if.sck_delay = QSPI_IF_DEVICE_RX_DELAY; in qspi_fill_init_struct()
703 initstruct->phy_if.spi_mode = qspi_get_mode(QSPI_IF_DEVICE_CPOL, QSPI_IF_DEVICE_CPHA); in qspi_fill_init_struct()
706 initstruct->prot_if.readoc = NRF_QSPI_READOC_READ4IO; in qspi_fill_init_struct()
707 initstruct->prot_if.writeoc = NRF_QSPI_WRITEOC_PP4IO; in qspi_fill_init_struct()
709 initstruct->prot_if.readoc = NRF_QSPI_READOC_FASTREAD; in qspi_fill_init_struct()
710 initstruct->prot_if.writeoc = NRF_QSPI_WRITEOC_PP; in qspi_fill_init_struct()
713 initstruct->phy_if.dpmen = false; in qspi_fill_init_struct()
720 return -ENXIO; in qspi_nrfx_configure()
723 struct qspi_nor_data *dev_data = dev->data; in qspi_nrfx_configure()
769 (qe_state != qe_value) ? "updating" : "no-change"); in qspi_nrfx_configure()
809 int flash_prefix = (WORD_SIZE - (addr % WORD_SIZE)) % WORD_SIZE; in read_non_aligned()
815 int dest_prefix = (WORD_SIZE - (int)dptr % WORD_SIZE) % WORD_SIZE; in read_non_aligned()
821 int flash_suffix = (size - flash_prefix) % WORD_SIZE; in read_non_aligned()
822 int flash_middle = size - flash_prefix - flash_suffix; in read_non_aligned()
823 int dest_middle = size - dest_prefix - (size - dest_prefix) % WORD_SIZE; in read_non_aligned()
827 flash_suffix = size - flash_prefix - flash_middle; in read_non_aligned()
850 res = _nrfx_qspi_read(buf, WORD_SIZE, addr - (WORD_SIZE - flash_prefix)); in read_non_aligned()
858 memcpy(dptr, buf + WORD_SIZE - flash_prefix, flash_prefix); in read_non_aligned()
880 return -EINVAL; in qspi_nor_read()
883 /* read size must be non-zero */ in qspi_nor_read()
932 return -EINVAL; in qspi_nor_write()
935 /* write size must be non-zero, less than 4, or a multiple of 4 */ in qspi_nor_write()
937 return -EINVAL; in qspi_nor_write()
940 /* address must be 4-byte aligned */ in qspi_nor_write()
942 return -EINVAL; in qspi_nor_write()
1023 const struct qspi_buf tx_buf = { .buf = (uint8_t *)&p_cfg->nonce[1], in qspi_cmd_encryption()
1024 .len = sizeof(p_cfg->nonce[1]) }; in qspi_cmd_encryption()
1088 return -1; in qspi_validate_rpu_wake_writecmd()
1141 return -1; in qspi_wait_while_rpu_awake()
1179 /* Waking RPU works reliably only with lowest frequency (8MHz) */ in qspi_cmd_wakeup_rpu()
1204 config->readoc = config->quad_spi ? NRF_QSPI_READOC_READ4IO : NRF_QSPI_READOC_FASTREAD; in qspi_init()
1205 config->writeoc = config->quad_spi ? NRF_QSPI_WRITEOC_PP4IO : NRF_QSPI_WRITEOC_PP; in qspi_init()
1209 k_sem_init(&qspi_cfg->lock, 1, 1); in qspi_init()
1220 if (!qspi_cfg->encryption) { in qspi_update_nonce()
1225 p_reg->DMA_ENC.NONCE2 = ++nonce_cnt; in qspi_update_nonce()
1227 p_reg->DMA_ENC.NONCE2 = ++nonce_cnt; in qspi_update_nonce()
1230 nonce_last_addr = addr + len - 4; in qspi_update_nonce()
1250 addr |= qspi_cfg->addrmask; in qspi_write()
1252 k_sem_take(&qspi_cfg->lock, K_FOREVER); in qspi_write()
1258 k_sem_give(&qspi_cfg->lock); in qspi_write()
1269 addr |= qspi_cfg->addrmask; in qspi_read()
1271 k_sem_take(&qspi_cfg->lock, K_FOREVER); in qspi_read()
1277 k_sem_give(&qspi_cfg->lock); in qspi_read()
1288 len = len + (4 * qspi_cfg->qspi_slave_latency); in qspi_hl_readw()
1294 return -ENOMEM; in qspi_hl_readw()
1299 k_sem_take(&qspi_cfg->lock, K_FOREVER); in qspi_hl_readw()
1305 k_sem_give(&qspi_cfg->lock); in qspi_hl_readw()
1307 *(uint32_t *)data = *(uint32_t *)(rxb + (len - 4)); in qspi_hl_readw()
1316 int count = 0; in qspi_hl_read() local
1320 while (count < (len / 4)) { in qspi_hl_read()
1321 qspi_hl_readw(addr + (4 * count), ((char *)data + (4 * count))); in qspi_hl_read()
1322 count++; in qspi_hl_read()
1365 if (qspi_cfg->encryption) { in qspi_enable_encryption()
1366 return -EALREADY; in qspi_enable_encryption()
1373 return -EIO; in qspi_enable_encryption()
1376 memcpy(qspi_cfg->p_cfg.key, key, 16); in qspi_enable_encryption()
1378 err = nrfx_qspi_dma_encrypt(&qspi_cfg->p_cfg); in qspi_enable_encryption()
1381 return -EIO; in qspi_enable_encryption()
1384 err = qspi_cmd_encryption(&qspi_perip, &qspi_cfg->p_cfg); in qspi_enable_encryption()
1387 return -EIO; in qspi_enable_encryption()
1390 qspi_cfg->encryption = true; in qspi_enable_encryption()
1396 return -ENOTSUP; in qspi_enable_encryption()