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/Zephyr-latest/dts/bindings/clock/
Dst,stm32g0-hsi-clock.yaml2 # SPDX-License-Identifier: Apache-2.0
5 STM32 HSI Clock node description for STM32G0 devices
6 On STM32G0, HSI is a 16MHz fixed clock.
9 source. In that case, a HSI divisor (ranges from 1 to 128) can be applied:
10 SYSCLK = HSI16 / HSI DIV
12 - 1 ==> HSISYS = 16MHZ
13 - 2 ==> HSISYS = 8MHZ
14 - 4 ==> HSISYS = 4MHZ
15 - 8 ==> HSISYS = 2MHZ
16 - 16 ==> HSISYS = 1MHZ
[all …]
Dst,stm32c0-hsi-clock.yaml2 # SPDX-License-Identifier: Apache-2.0
5 STM32 HSI Clock node description for STM32C0 devices
6 On STM32C0, HSI is a 48MHz fixed clock.
9 source. In that case, a HSI divisor (ranges from 1 to 128) can be applied:
10 SYSCLK = HSI48 / HSI DIV
12 - 1 ==> HSISYS = 48MHZ
13 - 2 ==> HSISYS = 24MHZ
14 - 4 ==> HSISYS = 12MHZ
15 - 8 ==> HSISYS = 6MHZ
16 - 16 ==> HSISYS = 3MHZ
[all …]
Dst,stm32h7-hsi-clock.yaml2 # SPDX-License-Identifier: Apache-2.0
4 description: STM32 HSI Clock
6 compatible: "st,stm32h7-hsi-clock"
8 include: [fixed-clock.yaml]
11 hsi-div:
15 HSI clock divider. Configures the output HSI clock frequency
17 - 1 # hsi_clk = 64MHz
18 - 2 # hsi_clk = 32MHz
19 - 4 # hsi_clk = 16MHz
20 - 8 # hsi_clk = 8MHz
/Zephyr-latest/tests/drivers/clock_control/stm32_clock_configuration/stm32h7_core/boards/
Dpll_hsi_96.overlay4 * SPDX-License-Identifier: Apache-2.0
13 hsi-div = <8>; /* HSI RC: 64MHz, hsi_clk = 8MHz */
18 div-m = <1>;
19 mul-n = <24>;
20 div-p = <2>;
21 div-q = <4>;
22 div-r = <2>;
29 clock-frequency = <DT_FREQ_M(96)>;
Dpll_hsi_fracn_550.overlay4 * SPDX-License-Identifier: Apache-2.0
13 hsi-div = <1>; /* HSI RC: 64MHz, hsi_clk = 64MHz */
18 div-m = <4>;
19 mul-n = <34>;
20 div-p = <1>;
21 div-q = <4>;
22 div-r = <2>;
30 clock-frequency = <DT_FREQ_M(550)>;
Dhsi_64.overlay4 * SPDX-License-Identifier: Apache-2.0
13 hsi-div = <1>; /* HSI RC: 64MHz, hsi_clk = 64MHz */
19 clock-frequency = <DT_FREQ_M(64)>;
Dclear_clocks.overlay4 * SPDX-License-Identifier: Apache-2.0
14 /delete-property/ hse-bypass;
15 /delete-property/ clock-frequency;
20 /delete-property/ hsi-div;
36 /delete-property/ div-m;
37 /delete-property/ mul-n;
38 /delete-property/ div-p;
39 /delete-property/ div-q;
40 /delete-property/ div-r;
41 /delete-property/ clocks;
[all …]
/Zephyr-latest/tests/drivers/clock_control/stm32_clock_configuration/stm32h5_core/boards/
Dpll_hsi_240.overlay5 * SPDX-License-Identifier: Apache-2.0
14 hsi-div = <1>; /* HSI RC: 64MHz, hsi_clk = 64MHz */
19 div-m = <4>;
20 mul-n = <30>;
21 div-p = <2>;
22 div-q = <2>;
23 div-r = <2>;
30 clock-frequency = <DT_FREQ_M(240)>;
31 ahb-prescaler = <1>;
32 apb1-prescaler = <1>;
[all …]
Dclear_clocks.overlay5 * SPDX-License-Identifier: Apache-2.0
13 /* Keep csi on to be the usart1-console clock */
25 /delete-property/ clock-frequency;
26 /delete-property/ hse-bypass;
31 /delete-property/ hsi-div;
39 /delete-property/ div-m;
40 /delete-property/ mul-n;
41 /delete-property/ div-p;
42 /delete-property/ div-q;
43 /delete-property/ div-r;
[all …]
/Zephyr-latest/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_core/boards/
Dpll_g0_64_hsi_16.overlay4 * SPDX-License-Identifier: Apache-2.0
14 hsi-div = <1>;
18 div-m = <1>;
19 mul-n = <8>;
20 div-q = <2>;
21 div-r = <2>;
28 clock-frequency = <DT_FREQ_M(64)>;
Dhsi_g0_16.overlay4 * SPDX-License-Identifier: Apache-2.0
12 &clk_hsi { /* HSI RC: 16MHz, hsi_clk = 16MHz */
14 hsi-div = <1>;
19 clock-frequency = <DT_FREQ_M(16)>;
Dclear_clocks.overlay4 * SPDX-License-Identifier: Apache-2.0
14 /delete-property/ hse-bypass;
15 /delete-property/ clock-frequency;
16 /delete-property/ hse-tcxo;
17 /delete-property/ hse-div2;
22 /delete-property/ hsi-div;
26 /delete-property/ div-m;
27 /delete-property/ mul-n;
28 /delete-property/ div-p;
29 /delete-property/ div-q;
[all …]
Dhsi_g0_16_div_2.overlay4 * SPDX-License-Identifier: Apache-2.0
15 hsi-div = <2>; /* HSISYS = 8Mhz */
21 ahb-prescaler = <1>;
22 clock-frequency = <DT_FREQ_M(8)>;
Dhsi_g0_16_div_4.overlay4 * SPDX-License-Identifier: Apache-2.0
15 hsi-div = <4>; /* HSISYS = 4Mhz */
21 ahb-prescaler = <1>;
22 clock-frequency = <DT_FREQ_M(4)>;
/Zephyr-latest/tests/drivers/clock_control/stm32_clock_configuration/stm32h7_devices/boards/
Dspi1_per_ck_hsi.overlay4 * SPDX-License-Identifier: Apache-2.0
14 hsi-div = <8>; /* HSI RC: 64MHz, hsi_clk = 8MHz */
23 /delete-property/ clocks;
Dcore_init.overlay4 * SPDX-License-Identifier: Apache-2.0
19 /delete-property/ hse-bypass;
20 /delete-property/ clock-frequency;
25 /delete-property/ hsi-div;
41 /delete-property/ div-m;
42 /delete-property/ mul-n;
43 /delete-property/ div-p;
44 /delete-property/ div-q;
45 /delete-property/ div-r;
46 /delete-property/ clocks;
[all …]
Dspi1_per_ck_d1ppre_1.overlay4 * SPDX-License-Identifier: Apache-2.0
14 hsi-div = <1>;
23 /delete-property/ clocks;
/Zephyr-latest/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/boards/
Dwb_i2c1_sysclk_lptim1_lsi.overlay4 * SPDX-License-Identifier: Apache-2.0
13 /delete-property/ hse-bypass;
14 /delete-property/ clock-frequency;
15 /delete-property/ hse-tcxo;
16 /delete-property/ hse-div2;
21 /delete-property/ hsi-div;
26 /delete-property/ msi-range;
30 /delete-property/ div-m;
31 /delete-property/ mul-n;
32 /delete-property/ div-p;
[all …]
Dwl_i2c1_hsi_lptim1_lse_adc1_pllp.overlay4 * SPDX-License-Identifier: Apache-2.0
13 /delete-property/ hse-bypass;
14 /delete-property/ clock-frequency;
15 /delete-property/ hse-tcxo;
16 /delete-property/ hse-div2;
21 /delete-property/ hsi-div;
26 /delete-property/ msi-range;
30 /delete-property/ div-m;
31 /delete-property/ mul-n;
32 /delete-property/ div-p;
[all …]
Dwl_i2c1_sysclk_lptim1_lsi.overlay4 * SPDX-License-Identifier: Apache-2.0
13 /delete-property/ hse-bypass;
14 /delete-property/ clock-frequency;
15 /delete-property/ hse-tcxo;
16 /delete-property/ hse-div2;
21 /delete-property/ hsi-div;
26 /delete-property/ msi-range;
30 /delete-property/ div-m;
31 /delete-property/ mul-n;
32 /delete-property/ div-p;
[all …]
Dwb_i2c1_hsi_lptim1_lse.overlay4 * SPDX-License-Identifier: Apache-2.0
13 /delete-property/ hse-bypass;
14 /delete-property/ clock-frequency;
15 /delete-property/ hse-tcxo;
16 /delete-property/ hse-div2;
21 /delete-property/ hsi-div;
26 /delete-property/ msi-range;
30 /delete-property/ div-m;
31 /delete-property/ mul-n;
32 /delete-property/ div-p;
[all …]
/Zephyr-latest/boards/st/stm32g081b_eval/
Dstm32g081b_eval.dts4 * SPDX-License-Identifier: Apache-2.0
7 /dts-v1/;
9 #include <st/g0/stm32g081rbtx-pinctrl.dtsi>
10 #include <zephyr/dt-bindings/input/input-event-codes.h>
14 compatible = "st,stm32g081-eval";
18 zephyr,shell-uart = &usart3;
24 compatible = "gpio-leds";
44 compatible = "gpio-keys";
83 volt-sensor0 = &vref;
84 volt-sensor1 = &vbat;
[all …]
/Zephyr-latest/boards/arduino/opta/
Darduino_opta_stm32h747xx_m7.dts5 * SPDX-License-Identifier: Apache-2.0
8 /dts-v1/;
10 #include <st/h7/stm32h747xihx-pinctrl.dtsi>
11 #include <zephyr/dt-bindings/input/input-event-codes.h>
12 #include "arduino_opta-common.dtsi"
16 compatible = "arduino,opta-m7";
21 zephyr,code-partition = &slot0_partition;
26 pinctrl-0 = <&usb_otg_fs_dm_pa11 &usb_otg_fs_dp_pa12>;
27 pinctrl-names = "default";
34 clock-frequency = <DT_FREQ_M(25)>;
[all …]
/Zephyr-latest/drivers/clock_control/
Dclock_stm32_ll_wba.c4 * SPDX-License-Identifier: Apache-2.0
62 return -ENOTSUP; in enabled_clock()
73 if (IN_RANGE(pclken->bus, STM32_PERIPH_BUS_MIN, STM32_PERIPH_BUS_MAX) == 0) { in stm32_clock_control_on()
75 return -ENOTSUP; in stm32_clock_control_on()
78 sys_set_bits(DT_REG_ADDR(DT_NODELABEL(rcc)) + pclken->bus, in stm32_clock_control_on()
79 pclken->enr); in stm32_clock_control_on()
81 temp = sys_read32(DT_REG_ADDR(DT_NODELABEL(rcc)) + pclken->bus); in stm32_clock_control_on()
94 if (IN_RANGE(pclken->bus, STM32_PERIPH_BUS_MIN, STM32_PERIPH_BUS_MAX) == 0) { in stm32_clock_control_off()
96 return -ENOTSUP; in stm32_clock_control_off()
99 sys_clear_bits(DT_REG_ADDR(DT_NODELABEL(rcc)) + pclken->bus, in stm32_clock_control_off()
[all …]
/Zephyr-latest/boards/st/stm32g071b_disco/
Dstm32g071b_disco.dts4 * SPDX-License-Identifier: Apache-2.0
7 /dts-v1/;
9 #include <st/g0/stm32g071r(6-8-b)tx-pinctrl.dtsi>
10 #include <zephyr/dt-bindings/sensor/ina230.h>
11 #include <zephyr/dt-bindings/input/input-event-codes.h>
15 compatible = "st,stm32g071-demo";
19 zephyr,shell-uart = &usart3;
25 compatible = "gpio-leds";
45 compatible = "gpio-keys";
74 compatible = "gpio-leds";
[all …]

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