Searched full:floating (Results 1 – 25 of 159) sorted by relevance
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| /Zephyr-latest/doc/kernel/services/other/ |
| D | float.rst | 3 Floating Point Services
6 The kernel allows threads to use floating point registers on board
10 Floating point services are currently available only for boards
11 based on ARM Cortex-M SoCs supporting the Floating Point Extension,
13 supporting the Floating Point Extension. The services provided
16 The kernel does not support the use of floating point registers by ISRs.
25 The kernel can be configured to provide only the floating point services
33 This mode is used when the application has no threads that use floating point
34 registers. It is the kernel's default floating point services mode.
36 If a thread uses any floating point register,
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| /Zephyr-latest/arch/arm/core/ |
| D | Kconfig.vfp | 16 This option signifies the support for a Vectored Floating-Point (VFP)
34 This option signifies the use of a VFP floating-point coprocessor
45 This option signifies the use of a VFP floating-point coprocessor
57 This option signifies the use of a VFP floating-point coprocessor
68 This option signifies the use of a VFP floating-point coprocessor
80 This option signifies the use of a VFP floating-point coprocessor
93 This option signifies the use of a VFP floating-point coprocessor
107 This option signifies the use of a VFP floating-point coprocessor
109 fused multiply-accumulate) and floating-point exception trapping with 16
121 This option signifies the use of a VFP floating-point coprocessor
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| D | Kconfig | 277 prompt "Floating point ABI"
282 bool "Floating point Hard ABI"
284 This option selects the Floating point ABI in which hardware floating
289 bool "Floating point Soft ABI"
291 This option selects the Floating point ABI in which hardware floating
297 bool "Half-precision floating point support"
300 This option enables the half-precision (16-bit) floating point support
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| /Zephyr-latest/include/zephyr/dsp/ |
| D | utils.h | 35 * There are separate functions for floating-point, Q7, Q15, and Q31 data types.
40 * @brief Convert a Q7 fixed-point value to a floating-point (float32_t) value with a left shift.
44 * @return The converted floating-point (float32_t) value.
49 * @brief Convert a Q15 fixed-point value to a floating-point (float32_t) value with a left shift.
53 * @return The converted floating-point (float32_t) value.
58 * @brief Convert a Q31 fixed-point value to a floating-point (float32_t) value with a left shift.
62 * @return The converted floating-point (float32_t) value.
67 * @brief Convert a Q7 fixed-point value to a floating-point (float64_t) value with a left shift.
71 * @return The converted floating-point (float64_t) value.
76 * @brief Convert a Q15 fixed-point value to a floating-point (float64_t) value with a left shift.
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| D | basicmath_f16.h | 8 * @brief Public APIs for DSP basicmath for 16 bit floating point
26 * @brief Floating-point vector multiplication.
37 * @brief Floating-point vector addition.
48 * @brief Floating-point vector subtraction.
59 * @brief Multiplies a floating-point vector by a scalar.
70 * @brief Floating-point vector absolute value.
79 * @brief Dot product of floating-point vectors.
90 * @brief Adds a constant offset to a floating-point vector.
101 * @brief Negates the elements of a floating-point vector.
110 * @brief Elementwise floating-point clipping
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| D | types.h | 45 * @brief 16-bit floating point type definition.
53 * @brief 32-bit floating-point type definition.
59 * @brief 64-bit floating-point type definition.
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| /Zephyr-latest/arch/x86/core/ia32/ |
| D | float.c | 9 * @brief Floating point register sharing routines
12 * floating point registers, by allowing the system to save FPU state info
15 * Note: If the kernel has been built without floating point register sharing
16 * support (CONFIG_FPU_SHARING), the floating point registers can still be used
21 * the floating point context is unconditionally saved/restored with every
24 * The floating point register sharing mechanism is designed for minimal
25 * intrusiveness. Floating point state saving is only performed for threads
29 * do require floating point state saving, a "lazy save/restore" mechanism
36 * The use of floating point instructions by ISRs is not supported by the
53 * @brief Disallow use of floating point capabilities
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| D | swap.S | 50 * Floating point registers are handled using a lazy save/restore mechanism
53 * 'current_fp' field to keep track of the thread that "owns" the floating
54 * point registers. Floating point registers consist of ST0->ST7 (x87 FPU and
57 * All floating point registers are considered 'volatile' thus they will only
60 * Floating point registers are currently NOT scrubbed, and are subject to
123 /* Eager floating point state restore logic
127 * sensitive data in the floating point/SIMD registers in a system
130 * Unconditionally save/restore floating point registers on context
149 * doesn't have floating point enabled) to prevent the "device not
155 * utilize floating point operations. However, the code responsible
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| /Zephyr-latest/tests/kernel/fpu_sharing/generic/src/ |
| D | load_store.c | 19 * The load/store test validates the floating point unit context
21 * priorities that each use the floating point registers. The context
23 * the floating point registers. The test also exercises the kernel's ability
24 * to automatically enable floating point support for a task, if supported.
121 * Initialize floating point load buffer to known values; in load_store_low()
134 * floating point values that have been saved. in load_store_low()
140 * floating point registers with known values. in load_store_low()
147 * using the floating point registers. in load_store_low()
150 * perform any floating point operations! in load_store_low()
162 * contents of all floating point registers to memory. in load_store_low()
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| D | float_regs_arm_gcc.h | 3 * @brief ARM GCC specific floating point register macros
49 * @brief Load all floating point registers
51 * This function loads ALL floating point registers pointed to by @a regs.
53 * will be issued to dump the floating point registers to memory.
75 * @brief Dump all floating point registers to memory
77 * This function stores ALL floating point registers to the memory buffer
79 * _load_all_float_registers() occurred to load all the floating point
98 * This function loads ALL floating point registers from the memory buffer
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| D | float_regs_arc_gcc.h | 3 * @brief ARC GCC specific floating point register macros
24 * @brief Load all floating point registers
26 * This function loads ALL floating point registers pointed to by @a regs.
28 * will be issued to dump the floating point registers to memory.
62 * @brief Dump all floating point registers to memory
64 * This function stores ALL floating point registers to the memory buffer
66 * _load_all_float_registers() occurred to load all the floating point
96 * This function loads ALL floating point registers from the memory buffer
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| D | float_regs_x86_gcc.h | 3 * @brief Intel x86 GCC specific floating point register macros
24 * @brief Load all floating point registers
26 * This function loads ALL floating point registers pointed to by @a regs.
28 * will be issued to dump the floating point registers to memory.
69 * This function loads ALL floating point registers from the memory buffer
74 * thread. Because the kernel doesn't save floating point context for
77 * floating point operations was also co-operatively switched out and simply
122 * @brief Dump all floating point registers to memory
124 * This function stores ALL floating point registers to the memory buffer
126 * _load_all_float_registers() occurred to load all the floating point
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| D | float_context.h | 40 * 8 x 80 bit floating point registers (ST[0] -> ST[7])
60 /* No non-volatile floating point registers */
102 /* No volatile floating point registers */
106 /* No non-volatile floating point registers */
143 /* No non-volatile floating point registers */
160 /* No non-volatile floating point registers */
181 /* No volatile floating point registers */
200 /* the set of ALL floating point registers */
212 * task, and the thread when loading up the floating point registers.
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| D | float_regs_arm64_gcc.h | 3 * @brief ARM64 GCC specific floating point register macros
20 * @brief Load all floating point registers
22 * This function loads ALL floating point registers pointed to by @a regs.
24 * will be issued to dump the floating point registers to memory.
60 * @brief Dump all floating point registers to memory
62 * This function stores ALL floating point registers to the memory buffer
64 * _load_all_float_registers() occurred to load all the floating point
98 * This function loads ALL floating point registers from the memory buffer
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| D | float_regs_xtensa.h | 15 * @brief Load all floating point registers
17 * This function loads ALL floating point registers pointed to by @a regs.
19 * will be issued to dump the floating point registers to memory.
53 * @brief Dump all floating point registers to memory
55 * This function stores ALL floating point registers to the memory buffer
57 * _load_all_float_registers() occurred to load all the floating point
88 * This function loads ALL floating point registers from the memory buffer
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| D | float_regs_riscv_gcc.h | 3 * @brief RISCV GCC specific floating point register macros
34 * @brief Load all floating point registers
36 * This function loads ALL floating point registers pointed to by @a regs.
38 * will be issued to dump the floating point registers to memory.
124 * @brief Dump all floating point registers to memory
126 * This function stores ALL floating point registers to the memory buffer
128 * _load_all_float_registers() occurred to load all the floating point
211 * This function loads ALL floating point registers from the memory buffer
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| /Zephyr-latest/arch/riscv/ |
| D | Kconfig.isa | 47 (F) - Standard Extension for Single-Precision Floating-Point
50 floating-point, which is named "F" and adds single-precision
51 floating-point computational instructions compliant with the IEEE
58 (D) - Standard Extension for Double-Precision Floating-Point
60 Standard double-precision floating-point instruction-set extension,
61 which is named "D" and adds double-precision floating-point
82 (Q) - Standard Extension for Quad-Precision Floating-Point
84 Standard extension for 128-bit binary floating-point instructions
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| /Zephyr-latest/lib/libc/picolibc/ |
| D | Kconfig | 40 bool "full support for integer/floating point values in printf/scanf"
42 Include full floating point and integer support in printf/scanf
49 Includes full integer with long long, but no floating
56 Include full integer other than long long, but no floating point
63 Include limited integer and no floating point support in
128 modifiers. C99 support is always included in the floating-point
138 floating-point variant.
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| /Zephyr-latest/lib/os/ |
| D | Kconfig.cbprintf | 67 bool "Floating point formatting in cbprintf"
71 Build the cbprintf utility function with support for floating
77 bool "Floating point %a conversions"
81 The %a hexadecimal format for floating point value conversion was
90 bool "Select %a format for all floating point specifications"
96 option implicitly uses %a (or %A) for all decimal floating
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| /Zephyr-latest/arch/x86/core/ |
| D | Kconfig.ia32 | 97 menu "Architecture Floating Point Options"
137 This hidden option allows multiple threads to use the floating point
138 registers, using logic to lazily save/restore the floating point
142 malware to read the contents of all floating point registers, see
151 Enable using software floating point operations.
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| /Zephyr-latest/subsys/modbus/ |
| D | Kconfig | 70 bool "Floating-Point extensions"
73 Enable Floating-Point extensions
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| /Zephyr-latest/include/zephyr/arch/x86/ia32/ |
| D | thread.h | 23 * Floating point register set alignment.
83 * saving/restoring of the traditional x87 floating point (and MMX) registers
91 /* definition of a single x87 (floating point / MMX) register */
98 * The following is the "normal" floating point register save area, or
125 /* definition of a single x87 (floating point / MMX) register */
139 * The following is the "extended" floating point register save area, or
180 /* empty floating point register definition */
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| /Zephyr-latest/tests/kernel/fpu_sharing/generic/ |
| D | README.txt | 1 Title: Shared Floating Point Support
5 The Shared Floating Point Support test uses two tasks to:
7 1) load and store floating point registers and check for corruption
10 This tests the ability of tasks to safely share floating point hardware
15 The demonstration utilizes semaphores, round robin scheduling, and floating
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| /Zephyr-latest/dts/bindings/power/ |
| D | st,stm32wb0-pwr.yaml | 83 smps-lp-floating:
86 Floating SMPS output in low-power state
89 is left floating when the SoC is in low-power state.
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| /Zephyr-latest/arch/arm/core/cortex_m/ |
| D | prep_c.c | 94 * Enable CP10 and CP11 Co-Processors to enable access to floating in z_arm_floating_point_init()
125 * the thread uses the floating point registers. Because of lazy state in z_arm_floating_point_init()
130 * out during context-switch or if an ISR attempts to execute floating in z_arm_floating_point_init()
142 /* Initialize the Floating Point Status and Control Register. */ in z_arm_floating_point_init()
157 * of floating point instructions. in z_arm_floating_point_init()
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