1# IA32-specific X86 subarchitecture options
2
3# Copyright (c) 2019 Intel Corp.
4# SPDX-License-Identifier: Apache-2.0
5
6if !X86_64
7
8config NESTED_INTERRUPTS
9	bool "Nested interrupts"
10	default y
11	help
12	  This option enables support for nested interrupts.
13
14menu "Memory Layout Options"
15
16config IDT_NUM_VECTORS
17	int "Number of IDT vectors"
18	default 256
19	range 32 256
20	help
21	  This option specifies the number of interrupt vector entries in the
22	  Interrupt Descriptor Table (IDT). By default all 256 vectors are
23	  supported in an IDT requiring 2048 bytes of memory.
24
25config SET_GDT
26	bool "Setup GDT as part of boot process"
27	default y
28	help
29	  This option sets up the GDT as part of the boot process. However,
30	  this may conflict with some security scenarios where the GDT is
31	  already appropriately set by an earlier bootloader stage, in which
32	  case this should be disabled. If disabled, the global _gdt pointer
33	  will not be available.
34
35config GDT_DYNAMIC
36	bool "Store GDT in RAM so that it can be modified"
37	depends on SET_GDT
38	help
39	  This option stores the GDT in RAM instead of ROM, so that it may
40	  be modified at runtime at the expense of some memory.
41
42config GDT_RESERVED_NUM_ENTRIES
43	int "Number of reserved GDT entry place holders"
44	depends on GDT_DYNAMIC
45	default 0
46	help
47	  This option defines the number of GDT entry place holders revserved
48	  that can be filled at runtime.
49
50endmenu
51
52menu "Processor Capabilities"
53
54config X86_ENABLE_TSS
55	bool
56	help
57	  This hidden option enables defining a Task State Segment (TSS) for
58	  kernel execution. This is needed to handle double-faults or
59	  do privilege elevation. It also defines a special TSS and handler
60	  for correctly handling double-fault exceptions, instead of just
61	  letting the system triple-fault and reset.
62
63config X86_STACK_PROTECTION
64	bool
65	default y if HW_STACK_PROTECTION
66	select THREAD_STACK_INFO
67	select SET_GDT
68	select GDT_DYNAMIC
69	select X86_ENABLE_TSS
70	imply THREAD_STACK_MEM_MAPPED if !DEMAND_PAGING
71	help
72	  This option leverages the MMU to cause a system fatal error if the
73	  bounds of the current process stack are overflowed. This is done
74	  by preceding all stack areas with a 4K guard page.
75
76config X86_USERSPACE
77	bool
78	default y if USERSPACE
79	select THREAD_STACK_INFO
80	select SET_GDT
81	select GDT_DYNAMIC
82	select X86_ENABLE_TSS
83	help
84	  This option enables APIs to drop a thread's privileges down to ring 3,
85	  supporting user-level threads that are protected from each other and
86	  from crashing the kernel.
87
88config X86_PAE
89	bool "Use PAE page tables"
90	default y
91	depends on X86_MMU
92	help
93	  If enabled, use PAE-style page tables instead of 32-bit page tables.
94	  The advantage is support for the Execute Disable bit, at a cost of
95	  more memory for paging structures.
96
97menu "Architecture Floating Point Options"
98
99if CPU_HAS_FPU
100
101config SSE
102	bool "SSE registers"
103	depends on FPU
104	select X86_SSE
105	help
106	  This option is deprecated. Please use CONFIG_X86_SSE instead.
107
108config SSE_FP_MATH
109	bool "Compiler-generated SSEx instructions"
110	depends on X86_SSE
111	select X86_SSE_FP_MATH
112	help
113	  This option is deprecated. Please use CONFIG_X86_SSE_FP_MATH instead.
114
115config EAGER_FPU_SHARING
116	bool
117	depends on FPU
118	depends on USERSPACE
119	default y if !X86_NO_LAZY_FP
120	help
121	  This hidden option unconditionally saves/restores the FPU/SIMD
122	  register state on every context switch.
123
124	  Mitigates CVE-2018-3665, but incurs a performance hit.
125
126	  For vulnerable systems that process sensitive information in the
127	  FPU register set, should be used any time CONFIG_FPU is
128	  enabled, regardless if the FPU is used by one thread or multiple.
129
130config LAZY_FPU_SHARING
131	bool
132	depends on FPU
133	depends on !EAGER_FPU_SHARING
134	depends on FPU_SHARING
135	default y if X86_NO_LAZY_FP || !USERSPACE
136	help
137	  This hidden option allows multiple threads to use the floating point
138	  registers, using logic to lazily save/restore the floating point
139	  register state on context switch.
140
141	  On Intel Core processors, may be vulnerable to exploits which allows
142	  malware to read the contents of all floating point registers, see
143	  CVE-2018-3665.
144
145endif # CPU_HAS_FPU
146
147config X86_FP_USE_SOFT_FLOAT
148	bool
149	default y if !FPU
150	help
151	  Enable using software floating point operations.
152
153endmenu
154
155config X86_DYNAMIC_IRQ_STUBS
156	int "Number of dynamic interrupt stubs"
157	depends on DYNAMIC_INTERRUPTS
158	default 4
159	help
160	  Installing interrupt handlers with irq_connect_dynamic() requires
161	  some stub code to be generated at build time, one stub per dynamic
162	  interrupt.
163
164endmenu
165
166config ARCH_HAS_STACKWALK
167	bool
168	default y
169	select DEBUG_INFO
170	select THREAD_STACK_INFO
171	depends on !OMIT_FRAME_POINTER
172	help
173	  Internal config to indicate that the arch_stack_walk() API is implemented
174	  and it can be enabled.
175
176config X86_USE_THREAD_LOCAL_STORAGE
177	bool
178	default y if THREAD_LOCAL_STORAGE
179	select SET_GDT
180	select GDT_DYNAMIC
181	help
182	  Internal config to enable thread local storage.
183
184config X86_MFENCE_INSTRUCTION_SUPPORTED
185	bool "X86 MFENCE instruction supported"
186	default y
187	depends on CACHE_MANAGEMENT
188	help
189	  Set n to disable the use of MFENCE instruction in arch_dcache_flush()
190	  for X86 CPUs have CLFLUSH instruction but no MFENCE
191
192config X86_RUNTIME_IRQ_STATS
193	bool
194	help
195	  Add irq runtime statistics to allow runtime profiling irq performance
196	  data with Host tools, enable this and implement platform dependent API
197	  runtime_irq_stats().
198
199endif # !X86_64
200