| /Zephyr-latest/dts/bindings/dma/ |
| D | st,stm32-dma.yaml | 2 # SPDX-License-Identifier: Apache-2.0
5 STM32 DMA controller
7 The STM32 DMA is a general-purpose direct memory access controller
8 capable of supporting 5 or 6 or 7 or 8 independent DMA channels.
9 Each stm32 soc with a DMA is of a special version type, which could be
14 compatible: "st,stm32-dma"
16 include: dma-controller.yaml
27 description: If the DMA controller V1 supports memory to memory transfer
29 dma-offset:
32 offset in the table of channels when mapping to a DMAMUX
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| D | dma-controller.yaml | 2 # SPDX-License-Identifier: Apache-2.0
4 # Common fields for DMA controllers
8 bus: dma
11 "#dma-cells":
14 description: Number of items to expect in a DMA specifier
16 dma-channel-mask:
19 Bitmask of available DMA channels in ascending order that are
23 dma-channels:
25 description: Number of DMA channels supported by the controller
27 dma-requests:
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| D | nxp,mcux-edma.yaml | 2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "nxp,mcux-edma"
8 include: dma-controller.yaml
14 Specifies base physical address(s) and size of DMA and respective DMAMUX register(s)
15 that routes DMA sources
20 dma-channels:
23 dma-requests:
26 dmamux-reg-offset:
33 channel-gap:
36 On some platforms, there may be a gap in the channels and
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| D | raspberrypi,pico-dma.yaml | 2 # SPDX-License-Identifier: Apache-2.0
5 Raspberry Pi Pico DMA
10 Use the definitions defined in `zephyr/dt-bindings/dma/rpi-pico-dma-rp2040.h`,
11 or `zephyr/dt-bindings/dma/rpi-pico-dma-rp2350.h`
13 channel-config: A 32bit mask specifying the DMA channel configuration
14 - bit 3: Enable Quiet IRQ
15 - bit 1: Enable Byte Swap
16 - bit 0: Enable High Priority
18 compatible: "raspberrypi,pico-dma"
20 include: [dma-controller.yaml, reset-device.yaml]
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| D | st,stm32-bdma.yaml | 2 # SPDX-License-Identifier: Apache-2.0
7 The STM32 BDMA is a general-purpose direct memory access controller
8 capable of supporting 5 or 6 or 7 or 8 independent BDMA channels.
11 described in the dma.txt file, using a four-cell specifier for each
13 1. channel: the bdma stream from 0 to <bdma-requests>
15 3. channel-config: A 32bit mask specifying the BDMA channel configuration
17 -bit 6-7 : Direction (see dma.h)
22 -bit 9 : Peripheral Increment Address
25 -bit 10 : Memory Increment Address
28 -bit 11-12 : Peripheral data size
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| D | infineon,xmc4xxx-dma.yaml | 2 # SPDX-License-Identifier: Apache-2.0
5 XMC4xxx DMA Controller
7 compatible: "infineon,xmc4xxx-dma"
9 include: dma-controller.yaml
18 dma-channels:
20 description: Number of DMA channels supported by the controller
22 "#dma-cells":
25 dma-cells:
26 - channel
27 - priority
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| D | nxp,edma.yaml | 2 # SPDX-License-Identifier: Apache-2.0
8 include: [dma-controller.yaml, base.yaml]
13 valid-channels:
18 property and "dma-channels" is the fact that this
21 not going to be using all of the possible channels, thus
23 and "dma-channels" are mutually exclusive, meaning you
26 "#dma-cells":
29 # IMPORTANT: if your EDMA version doesn't support channel MUX-ing please
33 dma-cells:
34 - channel
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| D | silabs,si32-dma.yaml | 3 # SPDX-License-Identifier: Apache-2.0
5 description: Si32 DMA controller
7 compatible: "silabs,si32-dma"
9 include: dma-controller.yaml
18 dma-channels:
21 Limiting the number of enabled channels saves RAM.
23 "#dma-cells":
26 dma-cells:
27 - channel
28 - high-prio
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| D | espressif,esp32-gdma.yaml | 2 # SPDX-License-Identifier: Apache-2.0
8 peripheral-to-memory, memory-to-peripheral, and memory-to-memory
11 The GDMA controller in ESP32-C3 has six independent channels,
12 three transmit channels and three receive channels.
24 The GDMA controller in ESP32-S3 has ten independent channels,
25 five transmit channels and five receive channels. Only six are
26 supported, meaning three transmit and three receive channels.
40 compatible: "espressif,esp32-gdma"
42 include: dma-controller.yaml
45 "#dma-cells":
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| D | wch,wch-dma.yaml | 2 # SPDX-License-Identifier: Apache-2.0
5 WCH DMA controller
7 The WCH DMA controller is a general-purpose direct memory access controller
8 featuring between 7 and 11 independent channels.
9 Every channel is capable of memory-to-memory, memory-to-peripheral, and
10 peripheral-to-memory access.
12 Mapping of peripheral requests to DMA channels is limited and SoC specific.
13 Commonly, each peripheral request maps to just a single DMA channel.
18 compatible: "wch,wch-dma"
20 include: dma-controller.yaml
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| D | dmamux-controller.yaml | 2 # SPDX-License-Identifier: Apache-2.0
11 "#dma-cells":
14 description: Number of items to expect in a DMA specifier (see dma V2)
16 dma-channels:
19 description: Number of DMAMUX output request channels supported by the controller
21 dma-generators:
25 dma-requests:
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| D | atmel,sam0-dmac.yaml | 1 description: Atmel SAM0 DMA controller
3 compatible: "atmel,sam0-dmac"
5 include: dma-controller.yaml
14 "#dma-cells":
17 # #dma-cells : Must be <2>.
26 # Example of devicetree dma channel configuration:
29 # /* Configure DMA channels for async operation */
31 # dma-names = "rx", "tx";
34 # In above fragment 10 and 11 represents the different channels used to
37 dma-cells:
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| D | st,stm32-dmamux.yaml | 2 # SPDX-License-Identifier: Apache-2.0
8 capable of supporting independent DMA channels.
9 DMAMUX clients connected to the STM32 DMA ultiplexer must use a two-cell specifier
10 for each dmamux channel: a phandle to the DMA multiplexer plus the following 2 integer cells:
11 1. channel: the mux channel from 0 to <dma-channels> - 1
13 3. channel-config: A 32bit mask specifying the DMA channel configuration
15 -bit 6-7 : Direction (see dma.h)
20 -bit 9 : Peripheral Increment Address
23 -bit 10 : Memory Increment Address
26 -bit 11-12 : Peripheral data size
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| /Zephyr-latest/drivers/dma/ |
| D | Kconfig.mcux_lpc | 1 # Copyright (c) 2020-2023, NXP
2 # SPDX-License-Identifier: Apache-2.0
9 DMA driver for MCUX LPC MCUs.
14 int "Number of DMA descriptors to use"
17 Each DMA descriptor can be used to transfer (1024*width) bytes of data.
22 int "Number of DMA channels to allocate memory for in driver"
25 The MCUX LPC DMA driver can save memory by not allocating static data
28 is "total number of unique DMA channels ever expected to be used, maximum
29 out of all DMA controllers". A value of 0 (default) means to allocate
30 as many channel data structures as the maximum number of DMA channels
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| D | dma_max32.c | 4 * SPDX-License-Identifier: Apache-2.0
9 #include <zephyr/drivers/dma.h>
24 uint8_t channels; member
36 /* mxc_dma_priority_t is limited to values 0-3 */ in max32_dma_ch_prio_valid()
38 LOG_ERR("Invalid DMA priority - must be type mxc_dma_priority_t (0-3)"); in max32_dma_ch_prio_valid()
54 LOG_ERR("Invalid DMA width - must be byte (1), halfword (2) or word (4)"); in max32_dma_width()
55 return -EINVAL; in max32_dma_width()
67 LOG_ERR("Invalid DMA address adjust - must be NO_CHANGE (0) or INCREMENT (1)"); in max32_dma_addr_adj()
72 static inline int max32_dma_ch_index(mxc_dma_regs_t *dma, uint8_t ch) in max32_dma_ch_index() argument
74 return (ch + MXC_DMA_GET_IDX(dma) * (MXC_DMA_CHANNELS / MXC_DMA_INSTANCES)); in max32_dma_ch_index()
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| D | dma_xmc4xxx.c | 4 * SPDX-License-Identifier: Apache-2.0
13 #include <zephyr/drivers/dma.h>
14 #include <zephyr/dt-bindings/dma/infineon-xmc4xxx-dma.h>
53 uint32_t llp; /* linked-list pointer to the next descriptor or null if last descriptor */
69 XMC_DMA_t *dma; member
75 struct dma_xmc4xxx_channel *channels; member
81 uint32_t channels_event = get_channels_event(dma); \
82 int channel = find_lsb_set(channels_event) - 1; \
86 dma_channel = &dev_data->channels[channel]; \
88 /* dma_start() and re-enable the event */ \
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| D | dma_xilinx_axi_dma.c | 2 *@brief Driver for Xilinx AXI DMA.
7 * SPDX-License-Identifier: Apache-2.0
11 #include <zephyr/drivers/dma.h>
40 /* internal DMA error, e.g., 0-length transfer */
54 /* masks for DMA registers */
59 /* interrupt timeout - trigger interrupt after X cycles when no transfer. Unit is 125 * */
62 /* irqthreshold - this can be used to generate interrupts after X completed packets */
76 /* DMA ignores completed bit in SG descriptor and overwrites descriptors */
84 /* run-stop */
107 /* DMA decode error */
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| D | dma_gd32.c | 4 * SPDX-License-Identifier: Apache-2.0
10 #include <zephyr/drivers/dma.h>
44 #define DMA_INTF(dma) REG32(dma + 0x00UL) argument
45 #define DMA_INTC(dma) REG32(dma + 0x04UL) argument
46 #define DMA_CHCTL(dma, ch) REG32((dma + 0x08UL) + 0x14UL * (uint32_t)(ch)) argument
47 #define DMA_CHCNT(dma, ch) REG32((dma + 0x0CUL) + 0x14UL * (uint32_t)(ch)) argument
48 #define DMA_CHPADDR(dma, ch) REG32((dma + 0x10UL) + 0x14UL * (uint32_t)(ch)) argument
49 #define DMA_CHMADDR(dma, ch) REG32((dma + 0x14UL) + 0x14UL * (uint32_t)(ch)) argument
52 #define GD32_DMA_INTF(dma) DMA_INTF(dma) argument
53 #define GD32_DMA_INTC(dma) DMA_INTC(dma) argument
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| D | dma_renesas_rz.c | 4 * SPDX-License-Identifier: Apache-2.0
8 #include <zephyr/drivers/dma.h>
14 /* FSP DMAC handler should be called within DMA ISR */
31 /* DMA call back */
48 /* Dma context should be the first in data structure */
50 struct dma_channel_data *channels; member
55 struct dmac_cb_ctx *cb_ctx = (struct dmac_cb_ctx *)args->p_context; in dmac_rz_cb_handler()
56 uint32_t channel = cb_ctx->channel; in dmac_rz_cb_handler()
57 const struct device *dev = cb_ctx->dmac_dev; in dmac_rz_cb_handler()
58 struct dma_renesas_rz_data *data = dev->data; in dmac_rz_cb_handler()
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| /Zephyr-latest/dts/xtensa/intel/ |
| D | intel_adsp_cavs.dtsi | 4 * SPDX-License-Identifier: Apache-2.0
11 lpgpdma0: dma@7c000 {
12 compatible = "intel,adsp-gpdma";
13 #dma-cells = <1>;
17 interrupt-parent = <&cavs_intc3>;
18 dma-buf-size-alignment = <4>;
19 dma-copy-alignment = <4>;
24 lpgpdma1: dma@7d000 {
25 compatible = "intel,adsp-gpdma";
26 #dma-cells = <1>;
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| /Zephyr-latest/tests/drivers/uart/uart_async_api/boards/ |
| D | samc21n_xpro.overlay | 1 /* SPDX-License-Identifier: Apache-2.0 */
8 /* Internally loop-back TX and RX on PAD0 */
12 /* Configure DMA channels for async operation */
14 dma-names = "rx", "tx";
22 /* configure DMA channels for async operation */
24 dma-names = "rx", "tx";
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| D | samd21_xpro.overlay | 1 /* SPDX-License-Identifier: Apache-2.0 */
12 /* Internally loop-back TX and RX on PAD0 */
16 /* Configure DMA channels for async operation */
18 dma-names = "rx", "tx";
22 /* configure DMA channels for async operation */
24 dma-names = "rx", "tx";
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| D | same54_xpro.overlay | 1 /* SPDX-License-Identifier: Apache-2.0 */
9 compatible = "atmel,sam0-uart";
10 current-speed = <115200>;
11 #address-cells = <1>;
12 #size-cells = <0>;
14 /* Internally loop-back TX and RX on PAD0 */
18 /* Configure DMA channels for async operation */
20 dma-names = "rx", "tx";
24 /* configure DMA channels for async operation */
26 dma-names = "rx", "tx";
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| D | saml21_xpro.overlay | 2 * SPDX-License-Identifier: Apache-2.0
12 /* internally loop-back Tx and Rx on PAD0 */
16 /* configure DMA channels for async operation */
18 dma-names = "rx", "tx";
22 /* configure DMA channels for async operation */
24 dma-names = "rx", "tx";
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| /Zephyr-latest/dts/arm/microchip/mec5/ |
| D | mec5_dma_chan16.dtsi | 4 * SPDX-License-Identifier: Apache-2.0
7 /* MEC5 central DMA controller with 16 channels */
14 #dma-cells = <2>;
15 dma-channels = <16>;
16 dma-requests = <16>;
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