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/Zephyr-latest/dts/bindings/pwm/
Draspberrypi,pico-pwm.yaml2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "raspberrypi,pico-pwm"
8 include: [pwm-controller.yaml, pinctrl-device.yaml, reset-device.yaml, base.yaml]
17 divider-int-0:
18 type: int
20 The integral part of the divider for pwm slice 0.
21 If a value between 1 and 255 is set, it will be set to the register
22 as the integer part of the divider.
26 divider-frac-0:
27 type: int
[all …]
Dinfineon,cat1-pwm.yaml4 # SPDX-License-Identifier: Apache-2.0
8 compatible: "infineon,cat1-pwm"
10 include: [pwm-controller.yaml, pinctrl-device.yaml]
21 pinctrl-0:
30 pinctrl-0 = <&p1_1_pwm0_0>;
33 pinctrl-names:
37 type: int
39 divider-type:
40 type: int
42 Specifies which type of divider to use.
[all …]
/Zephyr-latest/drivers/clock_control/
Dclock_control_r8a779f0_cpg_mssr.c7 * SPDX-License-Identifier: Apache-2.0
16 #include <zephyr/dt-bindings/clock/renesas_cpg_mssr.h>
17 #include <zephyr/dt-bindings/clock/r8a779f0_cpg_mssr.h>
82 static int r8a779f0_cpg_enable_disable_core(const struct device *dev, in r8a779f0_cpg_enable_disable_core()
85 int ret = 0; in r8a779f0_cpg_enable_disable_core()
88 switch (clk_info->module) { in r8a779f0_cpg_enable_disable_core()
90 reg = sys_read32(DEVICE_MMIO_GET(dev) + clk_info->offset); in r8a779f0_cpg_enable_disable_core()
91 reg &= ~(1 << R8A779F0_CLK_SD0_STOP_BIT); in r8a779f0_cpg_enable_disable_core()
95 reg = sys_read32(DEVICE_MMIO_GET(dev) + clk_info->offset); in r8a779f0_cpg_enable_disable_core()
96 reg &= ~(1 << R8A779F0_CLK_SD0H_STOP_BIT); in r8a779f0_cpg_enable_disable_core()
[all …]
Dclock_control_r8a7795_cpg_mssr.c6 * SPDX-License-Identifier: Apache-2.0
14 #include <zephyr/dt-bindings/clock/renesas_cpg_mssr.h>
15 #include <zephyr/dt-bindings/clock/r8a7795_cpg_mssr.h>
74 static int r8a7795_cpg_enable_disable_core(const struct device *dev, in r8a7795_cpg_enable_disable_core()
77 int ret = 0; in r8a7795_cpg_enable_disable_core()
82 switch (clk_info->module) { in r8a7795_cpg_enable_disable_core()
87 reg = sys_read32(DEVICE_MMIO_GET(dev) + clk_info->offset); in r8a7795_cpg_enable_disable_core()
88 reg &= ~(1 << R8A7795_CLK_SD_STOP_BIT); in r8a7795_cpg_enable_disable_core()
95 reg = sys_read32(DEVICE_MMIO_GET(dev) + clk_info->offset); in r8a7795_cpg_enable_disable_core()
96 reg &= ~(1 << R8A7795_CLK_SDH_STOP_BIT); in r8a7795_cpg_enable_disable_core()
[all …]
Dclock_control_si32_apb.c4 * SPDX-License-Identifier: Apache-2.0
20 uint32_t divider; member
23 static int clock_control_si32_apb_on(const struct device *dev, clock_control_subsys_t sys) in clock_control_si32_apb_on()
25 return -ENOTSUP; in clock_control_si32_apb_on()
28 static int clock_control_si32_apb_off(const struct device *dev, clock_control_subsys_t sys) in clock_control_si32_apb_off()
31 return -ENOTSUP; in clock_control_si32_apb_off()
34 static int clock_control_si32_apb_get_rate(const struct device *dev, clock_control_subsys_t sys, in clock_control_si32_apb_get_rate()
37 const struct clock_control_si32_apb_config *config = dev->config; in clock_control_si32_apb_get_rate()
38 const int ret = clock_control_get_rate(config->clock_dev, NULL, rate); in clock_control_si32_apb_get_rate()
44 *rate /= config->divider; in clock_control_si32_apb_get_rate()
[all …]
Dclock_control_lpc11u6x.h4 * SPDX-License-Identifier: Apache-2.0
12 #define LPC11U6X_SYS_AHB_CLK_CTRL_I2C0 (1 << 5)
13 #define LPC11U6X_SYS_AHB_CLK_CTRL_GPIO (1 << 6)
14 #define LPC11U6X_SYS_AHB_CLK_CTRL_USART0 (1 << 12)
15 #define LPC11U6X_SYS_AHB_CLK_CTRL_USB (1 << 14)
16 #define LPC11U6X_SYS_AHB_CLK_CTRL_IOCON (1 << 16)
17 #define LPC11U6X_SYS_AHB_CLK_CTRL_PINT (1 << 19)
18 #define LPC11U6X_SYS_AHB_CLK_CTRL_USART1 (1 << 20)
19 #define LPC11U6X_SYS_AHB_CLK_CTRL_USART2 (1 << 21)
20 #define LPC11U6X_SYS_AHB_CLK_CTRL_USART3_4 (1 << 22)
[all …]
Dclock_control_litex.c4 * SPDX-License-Identifier: Apache-2.0
30 {DRP_ADDR_RESET, 1},
31 {DRP_ADDR_LOCKED, 1},
32 {DRP_ADDR_READ, 1},
33 {DRP_ADDR_WRITE, 1},
34 {DRP_ADDR_DRDY, 1},
35 {DRP_ADDR_ADR, 1},
66 …* https://github.com/Digilent/Zybo-hdmi-out/blob/b991fff6e964420ae3c00c3dbee52f2ad748b3ba/sdk/disp…
213 return litex_clk_filter_table[glob_mul - 1]; in litex_clk_lookup_filter()
219 return litex_clk_lock_table[glob_mul - 1]; in litex_clk_lookup_lock()
[all …]
/Zephyr-latest/dts/bindings/i3c/
Dnxp,mcux-i3c.yaml4 # SPDX-License-Identifier: Apache-2.0
8 compatible: "nxp,mcux-i3c"
10 include: [i3c-controller.yaml, pinctrl-device.yaml]
19 i3c-od-scl-hz:
20 type: int
25 clk-divider:
26 type: int
27 description: Main clock divider for I3C
30 clk-divider-tc:
31 type: int
[all …]
/Zephyr-latest/dts/bindings/clock/
Draspberrypi,pico-pll.yaml2 # SPDX-License-Identifier: Apache-2.0
7 compatible: "raspberrypi,pico-pll"
9 include: [base.yaml, fixed-factor-clock.yaml]
12 fb-div:
13 type: int
16 The feedback divider value.
19 post-div1:
20 type: int
23 The post clock divider.
24 The valid range is 1 to 49.
[all …]
Dlitex,clk.yaml2 # SPDX-License-Identifier: Apache-2.0
4 include: [clock-controller.yaml, base.yaml]
14 clock-cells:
15 - id
22 "#clock-cells":
24 const: 1
26 clock-output-names:
28 type: string-array
33 litex,lock-timeout:
35 type: int
[all …]
Dnordic,nrf-auxpll.yaml2 # SPDX-License-Identifier: Apache-2.0
9 f_out = ((R + A * 2^(-16)) * f_src) / B
13 - A: nordic,frequency
14 - B: nordic,outdiv
15 - R: nordic,range (3=low, 4=mid, 5=high, 6=statichigh)
16 - f_src: Source frequency, given by clocks
18 compatible: "nordic,nrf-auxpll"
21 - base.yaml
22 - clock-controller.yaml
23 - nordic-nrf-ficr-client.yaml
[all …]
Dnxp,kinetis-mcg.yaml2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "nxp,kinetis-mcg"
8 include: [clock-controller.yaml, base.yaml]
14 "#clock-cells":
15 const: 1
18 type: int
19 enum: [0, 1, 2, 3, 4, 5, 6, 7]
21 Internal Reference Clock Divider.
25 type: int
26 enum: [0, 1, 2, 3, 4, 5, 6, 7]
[all …]
/Zephyr-latest/soc/nxp/rw/
Dflexspi_clock_setup.c2 * Copyright 2022-2023 NXP
3 * SPDX-License-Identifier: Apache-2.0
18 * the FlexSPI with a new MUX source, only change the divider. This function
22 int __ramfunc flexspi_clock_set_freq(uint32_t clock_name, uint32_t rate) in flexspi_clock_set_freq()
25 uint32_t divider; in flexspi_clock_set_freq() local
30 root_rate = ((CLKCTL0->FLEXSPIFCLKDIV & CLKCTL0_FLEXSPIFCLKDIV_DIV_MASK) + 1) * in flexspi_clock_set_freq()
33 /* Select a divider based on root frequency. in flexspi_clock_set_freq()
34 * if we can't get an exact divider, round down in flexspi_clock_set_freq()
36 divider = ((root_rate + (rate - 1)) / rate) - 1; in flexspi_clock_set_freq()
37 /* Cap divider to max value */ in flexspi_clock_set_freq()
[all …]
/Zephyr-latest/drivers/mdio/
Dmdio_xmc4xxx.c4 * SPDX-License-Identifier: Apache-2.0
27 #define MIN_MDC_FREQUENCY 1000000u /* 1us period */
30 uint8_t divider; member
35 {.divider = 8, .reg_val = 2}, {.divider = 13, .reg_val = 3},
36 {.divider = 21, .reg_val = 0}, {.divider = 31, .reg_val = 1},
37 {.divider = 51, .reg_val = 4}, {.divider = 62, .reg_val = 5},
51 static int mdio_xmc4xxx_transfer(const struct device *dev, uint8_t phy_addr, uint8_t reg_addr, in mdio_xmc4xxx_transfer()
54 const struct mdio_xmc4xxx_dev_config *const dev_cfg = dev->config; in mdio_xmc4xxx_transfer()
55 ETH_GLOBAL_TypeDef *const regs = dev_cfg->regs; in mdio_xmc4xxx_transfer()
56 struct mdio_xmc4xxx_dev_data *const dev_data = dev->data; in mdio_xmc4xxx_transfer()
[all …]
/Zephyr-latest/drivers/pwm/
Dpwm_sam.c4 * SPDX-License-Identifier: Apache-2.0
30 uint8_t divider; member
33 static int sam_pwm_get_cycles_per_sec(const struct device *dev, in sam_pwm_get_cycles_per_sec()
36 const struct sam_pwm_config *config = dev->config; in sam_pwm_get_cycles_per_sec()
37 uint8_t prescaler = config->prescaler; in sam_pwm_get_cycles_per_sec()
38 uint8_t divider = config->divider; in sam_pwm_get_cycles_per_sec() local
41 ((1 << prescaler) * divider); in sam_pwm_get_cycles_per_sec()
46 static int sam_pwm_set_cycles(const struct device *dev, uint32_t channel, in sam_pwm_set_cycles()
50 const struct sam_pwm_config *config = dev->config; in sam_pwm_set_cycles()
52 Pwm * const pwm = config->regs; in sam_pwm_set_cycles()
[all …]
/Zephyr-latest/soc/nxp/kinetis/k8x/
DKconfig5 # SPDX-License-Identifier: Apache-2.0
35 int "Freescale K8x core clock divider"
36 default 1
42 int "Freescale K8x bus clock divider"
49 int "Freescale K8x FlexBus clock divider"
56 int "Freescale K8x flash clock divider"
/Zephyr-latest/dts/bindings/adc/
Dadi,max32-adc.yaml1 # Copyright (c) 2023-2024 Analog Devices, Inc.
2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "adi,max32-adc"
8 include: [adc-controller.yaml, pinctrl-device.yaml]
20 pinctrl-0:
23 pinctrl-names:
26 channel-count:
27 type: int
31 vref-mv:
32 type: int
[all …]
Dnxp,vf610-adc.yaml2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "nxp,vf610-adc"
8 include: [adc-controller.yaml, "nxp,rdc-policy.yaml"]
17 clk-source:
18 type: int
21 Select adc clock source: 0 clock from IPG, 1 clock from IPG divided 2, 2 async clock
23 clk-divider:
24 type: int
27 Select clock divider: 0 clock divided by 1, 1 clock divided by 2, 2 clock divided by 4,
30 "#io-channel-cells":
[all …]
Dnxp,adc12.yaml2 # SPDX-License-Identifier: Apache-2.0
8 include: [adc-controller.yaml, pinctrl-device.yaml]
17 clk-source:
18 type: int
22 clk-divider:
23 type: int
25 description: clock divider for the converter
27 alternate-voltage-reference:
31 sample-time:
32 type: int
[all …]
Dnxp,mcux-12b1msps-sar.yaml2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "nxp,mcux-12b1msps-sar"
8 include: [adc-controller.yaml, pinctrl-device.yaml]
17 clk-divider:
18 type: int
20 description: clock divider for the converter
22 sample-period-mode:
23 type: int
27 "#io-channel-cells":
28 const: 1
[all …]
Dnxp,lpc-lpadc.yaml2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "nxp,lpc-lpadc"
8 include: [adc-controller.yaml, pinctrl-device.yaml]
17 clk-divider:
18 type: int
19 description: clock divider for the converter
21 clk-source:
22 type: int
25 voltage-ref:
26 type: int
[all …]
/Zephyr-latest/dts/bindings/tcpc/
Dst,stm32-ucpd.yaml2 # SPDX-License-Identifier: Apache-2.0
5 ST STM32 family USB Type-C / Power Delivery. The default values were
8 compatible: "st,stm32-ucpd"
10 include: [base.yaml, pinctrl-device.yaml]
22 psc-ucpdclk:
24 type: int
26 - 1
27 - 2
28 - 4
29 - 8
[all …]
/Zephyr-latest/dts/bindings/timer/
Dambiq,stimer.yaml2 # SPDX-License-Identifier: Apache-2.0
17 clk-source:
18 type: int
21 clk-source specifies the clock source that used by the system timer.
23 0 - NOCLK : No clock enabled.
24 1 - HFRC_DIV16 : 3MHz from the HFRC clock divider.
25 2 - HFRC_DIV256 : 187.5KHz from the HFRC clock divider.
26 3 - XTAL_DIV1 : 32768Hz from the crystal oscillator.
27 4 - XTAL_DIV2 : 16384Hz from the crystal oscillator.
28 5 - XTAL_DIV32 : 1024Hz from the crystal oscillator.
[all …]
/Zephyr-latest/drivers/serial/
Duart_b91.c4 * SPDX-License-Identifier: Apache-2.0
22 ((const struct uart_b91_config *)dev->config)->uart_addr)
32 #define UART_PARITY_EVEN ((uint8_t)1u)
111 return (uart->bufcnt & FLD_UART_TX_BUF_CNT) >> FLD_UART_TX_BUF_CNT_OFFSET; in uart_b91_get_tx_bufcnt()
117 return (uart->bufcnt & FLD_UART_RX_BUF_CNT) >> FLD_UART_RX_BUF_CNT_OFFSET; in uart_b91_get_rx_bufcnt()
126 return 1; in uart_b91_is_prime()
137 return 1; in uart_b91_is_prime()
142 uint16_t *divider, uint8_t *bwpc) in uart_b91_cal_div_and_bwpc() argument
151 primeDec = 10 * pclk / baudrate - 10 * primeInt; in uart_b91_cal_div_and_bwpc()
154 primeInt += 1; in uart_b91_cal_div_and_bwpc()
[all …]
/Zephyr-latest/dts/bindings/iio/afe/
Dcurrent-sense-amplifier.yaml2 # SPDX-License-Identifier: Apache-2.0
5 When an io-channel measures the voltage over a current sense amplifier,
11 … https://www.kernel.org/doc/Documentation/devicetree/bindings/iio/afe/current-sense-amplifier.yaml
13 compatible: "current-sense-amplifier"
18 io-channels:
21 Channels available with this divider configuration.
23 sense-resistor-milli-ohms:
24 type: int
27 Resistance of the shunt resistor in milli-ohms.
29 sense-gain-mult:
[all …]

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