Searched full:ch0 (Results 1 – 24 of 24) sorted by relevance
| /hal_espressif-latest/components/soc/esp32c6/include/soc/ |
| D | ledc_reg.h | 1457 * Ledc ch0 gamma ram write register.
1461 * Ledc ch0 gamma duty inc of current ram write address.This register is used to
1471 * Ledc ch0 gamma duty cycle of current ram write address.The duty will change every
1479 * Ledc ch0 gamma scale of current ram write address.This register is used to
1487 * Ledc ch0 gamma duty num of current ram write address.This register is used to
1496 * Ledc ch0 gamma ram write address register.
1500 * Ledc ch0 gamma ram write address.
1508 * Ledc ch0 gamma ram read address register.
1512 * Ledc ch0 gamma ram read address.
1520 * Ledc ch0 gamma ram read data register.
[all …]
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| D | ledc_struct.h | 82 * Ledc ch0 duty change end event enable register, write 1 to enable this event.
107 * Ledc ch0 overflow count pulse event enable register, write 1 to enable this event.
164 * Ledc ch0 duty scale update task enable register, write 1 to enable this task.
230 * Ledc ch0 signal out disable task enable register, write 1 to enable this task.
255 * Ledc ch0 overflow count reset task enable register, write 1 to enable this task.
321 * Ledc ch0 gamma restart task enable register, write 1 to enable this task.
346 * Ledc ch0 gamma pause task enable register, write 1 to enable this task.
371 * Ledc ch0 gamma resume task enable register, write 1 to enable this task.
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| D | soc_etm_struct.h | 20 * ch0 enable
157 * ch0 set
294 * ch0 clear
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| D | soc_etm_reg.h | 19 * ch0 enable
248 * ch0 set
477 * ch0 clear
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| D | efuse_struct.h | 746 * ADC1 init code at atten0 ch0
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| D | efuse_reg.h | 951 * ADC1 init code at atten0 ch0
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| D | mcpwm_reg.h | 2733 * ch0 capture value status register
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| /hal_espressif-latest/components/soc/esp32h2/include/soc/ |
| D | ledc_reg.h | 1457 * Ledc ch0 gamma ram write register.
1461 * Ledc ch0 gamma duty inc of current ram write address.This register is used to
1471 * Ledc ch0 gamma duty cycle of current ram write address.The duty will change every
1479 * Ledc ch0 gamma scale of current ram write address.This register is used to
1487 * Ledc ch0 gamma duty num of current ram write address.This register is used to
1496 * Ledc ch0 gamma ram write address register.
1500 * Ledc ch0 gamma ram write address.
1508 * Ledc ch0 gamma ram read address register.
1512 * Ledc ch0 gamma ram read address.
1520 * Ledc ch0 gamma ram read data register.
[all …]
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| D | ledc_struct.h | 82 * Ledc ch0 duty change end event enable register, write 1 to enable this event.
107 * Ledc ch0 overflow count pulse event enable register, write 1 to enable this event.
164 * Ledc ch0 duty scale update task enable register, write 1 to enable this task.
230 * Ledc ch0 signal out disable task enable register, write 1 to enable this task.
255 * Ledc ch0 overflow count reset task enable register, write 1 to enable this task.
321 * Ledc ch0 gamma restart task enable register, write 1 to enable this task.
346 * Ledc ch0 gamma pause task enable register, write 1 to enable this task.
371 * Ledc ch0 gamma resume task enable register, write 1 to enable this task.
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| D | soc_etm_struct.h | 20 * ch0 enable
157 * ch0 set
294 * ch0 clear
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| D | soc_etm_reg.h | 19 * ch0 enable
248 * ch0 set
477 * ch0 clear
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| D | mcpwm_reg.h | 2733 * ch0 capture value status register
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| /hal_espressif-latest/components/soc/esp32c3/include/soc/ |
| D | rmt_struct.h | 222 uint32_t ch0: 1; member
231 uint32_t ch0: 1; member
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| /hal_espressif-latest/zephyr/port/pincfgs/ |
| D | esp32c2.yml | 74 ch0:
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| D | esp32c3.yml | 126 ch0:
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| D | esp32c6.yml | 79 ch0:
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| D | esp32s2.yml | 159 ch0:
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| D | esp32.yml | 186 ch0:
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| D | esp32s3.yml | 185 ch0:
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| /hal_espressif-latest/components/efuse/esp32c6/ |
| D | esp_efuse_table.csv | 186 …1_INIT_CODE_ATTEN0_CH0, EFUSE_BLK2, 225, 4, [] ADC1 init code at atten0 ch0
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| D | esp_efuse_table.c | 689 {EFUSE_BLK2, 225, 4}, // [] ADC1 init code at atten0 ch0,
1593 &ADC1_INIT_CODE_ATTEN0_CH0[0], // [] ADC1 init code at atten0 ch0
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| /hal_espressif-latest/tools/esptool_py/espefuse/efuse_defs/ |
| D | esp32c6.yaml | 94 … : '', dict : '', desc: ADC1 init code at atten0 ch0, rloc: 'EFUSE_RD_SY…
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| /hal_espressif-latest/components/soc/esp32s3/include/soc/ |
| D | mcpwm_reg.h | 2805 * ch0 capture value status register
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| /hal_espressif-latest/components/soc/esp32/include/soc/ |
| D | mcpwm_reg.h | 2805 * ch0 capture value status register
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