1 /** 2 * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 #pragma once 7 8 #include <stdint.h> 9 #include "soc/soc.h" 10 #ifdef __cplusplus 11 extern "C" { 12 #endif 13 14 /** MCPWM_CLK_CFG_REG register 15 * PWM clock prescaler register. 16 */ 17 #define MCPWM_CLK_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x0) 18 /** MCPWM_CLK_PRESCALE : R/W; bitpos: [7:0]; default: 0; 19 * Period of PWM_clk = 6.25ns * (PWM_CLK_PRESCALE + 1) 20 */ 21 #define MCPWM_CLK_PRESCALE 0x000000FFU 22 #define MCPWM_CLK_PRESCALE_M (MCPWM_CLK_PRESCALE_V << MCPWM_CLK_PRESCALE_S) 23 #define MCPWM_CLK_PRESCALE_V 0x000000FFU 24 #define MCPWM_CLK_PRESCALE_S 0 25 26 /** MCPWM_TIMER0_CFG0_REG register 27 * PWM timer0 period and update method configuration register. 28 */ 29 #define MCPWM_TIMER0_CFG0_REG(i) (REG_MCPWM_BASE(i) + 0x4) 30 /** MCPWM_TIMER0_PRESCALE : R/W; bitpos: [7:0]; default: 0; 31 * period of PT0_clk = Period of PWM_clk * (PWM_TIMER0_PRESCALE + 1) 32 */ 33 #define MCPWM_TIMER0_PRESCALE 0x000000FFU 34 #define MCPWM_TIMER0_PRESCALE_M (MCPWM_TIMER0_PRESCALE_V << MCPWM_TIMER0_PRESCALE_S) 35 #define MCPWM_TIMER0_PRESCALE_V 0x000000FFU 36 #define MCPWM_TIMER0_PRESCALE_S 0 37 /** MCPWM_TIMER0_PERIOD : R/W; bitpos: [23:8]; default: 255; 38 * period shadow register of PWM timer0 39 */ 40 #define MCPWM_TIMER0_PERIOD 0x0000FFFFU 41 #define MCPWM_TIMER0_PERIOD_M (MCPWM_TIMER0_PERIOD_V << MCPWM_TIMER0_PERIOD_S) 42 #define MCPWM_TIMER0_PERIOD_V 0x0000FFFFU 43 #define MCPWM_TIMER0_PERIOD_S 8 44 /** MCPWM_TIMER0_PERIOD_UPMETHOD : R/W; bitpos: [25:24]; default: 0; 45 * Update method for active register of PWM timer0 period, 0: immediate, 1: TEZ, 2: 46 * sync, 3: TEZ | sync. TEZ here and below means timer equal zero event 47 */ 48 #define MCPWM_TIMER0_PERIOD_UPMETHOD 0x00000003U 49 #define MCPWM_TIMER0_PERIOD_UPMETHOD_M (MCPWM_TIMER0_PERIOD_UPMETHOD_V << MCPWM_TIMER0_PERIOD_UPMETHOD_S) 50 #define MCPWM_TIMER0_PERIOD_UPMETHOD_V 0x00000003U 51 #define MCPWM_TIMER0_PERIOD_UPMETHOD_S 24 52 53 /** MCPWM_TIMER0_CFG1_REG register 54 * PWM timer0 working mode and start/stop control configuration register. 55 */ 56 #define MCPWM_TIMER0_CFG1_REG(i) (REG_MCPWM_BASE(i) + 0x8) 57 /** MCPWM_TIMER0_START : R/W/SC; bitpos: [2:0]; default: 0; 58 * PWM timer0 start and stop control. 0: if PWM timer0 starts, then stops at TEZ, 1: 59 * if timer0 starts, then stops at TEP, 2: PWM timer0 starts and runs on, 3: timer0 60 * starts and stops at the next TEZ, 4: timer0 starts and stops at the next TEP. TEP 61 * here and below means the event that happens when the timer equals to period 62 */ 63 #define MCPWM_TIMER0_START 0x00000007U 64 #define MCPWM_TIMER0_START_M (MCPWM_TIMER0_START_V << MCPWM_TIMER0_START_S) 65 #define MCPWM_TIMER0_START_V 0x00000007U 66 #define MCPWM_TIMER0_START_S 0 67 /** MCPWM_TIMER0_MOD : R/W; bitpos: [4:3]; default: 0; 68 * PWM timer0 working mode, 0: freeze, 1: increase mode, 2: decrease mode, 3: up-down 69 * mode 70 */ 71 #define MCPWM_TIMER0_MOD 0x00000003U 72 #define MCPWM_TIMER0_MOD_M (MCPWM_TIMER0_MOD_V << MCPWM_TIMER0_MOD_S) 73 #define MCPWM_TIMER0_MOD_V 0x00000003U 74 #define MCPWM_TIMER0_MOD_S 3 75 76 /** MCPWM_TIMER0_SYNC_REG register 77 * PWM timer0 sync function configuration register. 78 */ 79 #define MCPWM_TIMER0_SYNC_REG(i) (REG_MCPWM_BASE(i) + 0xc) 80 /** MCPWM_TIMER0_SYNCI_EN : R/W; bitpos: [0]; default: 0; 81 * When set, timer reloading with phase on sync input event is enabled. 82 */ 83 #define MCPWM_TIMER0_SYNCI_EN (BIT(0)) 84 #define MCPWM_TIMER0_SYNCI_EN_M (MCPWM_TIMER0_SYNCI_EN_V << MCPWM_TIMER0_SYNCI_EN_S) 85 #define MCPWM_TIMER0_SYNCI_EN_V 0x00000001U 86 #define MCPWM_TIMER0_SYNCI_EN_S 0 87 /** MCPWM_TIMER0_SYNC_SW : R/W; bitpos: [1]; default: 0; 88 * Toggling this bit will trigger a software sync. 89 */ 90 #define MCPWM_TIMER0_SYNC_SW (BIT(1)) 91 #define MCPWM_TIMER0_SYNC_SW_M (MCPWM_TIMER0_SYNC_SW_V << MCPWM_TIMER0_SYNC_SW_S) 92 #define MCPWM_TIMER0_SYNC_SW_V 0x00000001U 93 #define MCPWM_TIMER0_SYNC_SW_S 1 94 /** MCPWM_TIMER0_SYNCO_SEL : R/W; bitpos: [3:2]; default: 0; 95 * PWM timer0 sync_out selection, 0: sync_in, 1: TEZ, 2: TEP, and sync out will always 96 * generate when toggling the reg_timer0_sync_sw bit 97 */ 98 #define MCPWM_TIMER0_SYNCO_SEL 0x00000003U 99 #define MCPWM_TIMER0_SYNCO_SEL_M (MCPWM_TIMER0_SYNCO_SEL_V << MCPWM_TIMER0_SYNCO_SEL_S) 100 #define MCPWM_TIMER0_SYNCO_SEL_V 0x00000003U 101 #define MCPWM_TIMER0_SYNCO_SEL_S 2 102 /** MCPWM_TIMER0_PHASE : R/W; bitpos: [19:4]; default: 0; 103 * phase for timer reload on sync event 104 */ 105 #define MCPWM_TIMER0_PHASE 0x0000FFFFU 106 #define MCPWM_TIMER0_PHASE_M (MCPWM_TIMER0_PHASE_V << MCPWM_TIMER0_PHASE_S) 107 #define MCPWM_TIMER0_PHASE_V 0x0000FFFFU 108 #define MCPWM_TIMER0_PHASE_S 4 109 /** MCPWM_TIMER0_PHASE_DIRECTION : R/W; bitpos: [20]; default: 0; 110 * Configure the PWM timer0's direction when timer0 mode is up-down mode: 111 * 0-increase,1-decrease 112 */ 113 #define MCPWM_TIMER0_PHASE_DIRECTION (BIT(20)) 114 #define MCPWM_TIMER0_PHASE_DIRECTION_M (MCPWM_TIMER0_PHASE_DIRECTION_V << MCPWM_TIMER0_PHASE_DIRECTION_S) 115 #define MCPWM_TIMER0_PHASE_DIRECTION_V 0x00000001U 116 #define MCPWM_TIMER0_PHASE_DIRECTION_S 20 117 118 /** MCPWM_TIMER0_STATUS_REG register 119 * PWM timer0 status register. 120 */ 121 #define MCPWM_TIMER0_STATUS_REG(i) (REG_MCPWM_BASE(i) + 0x10) 122 /** MCPWM_TIMER0_VALUE : RO; bitpos: [15:0]; default: 0; 123 * current PWM timer0 counter value 124 */ 125 #define MCPWM_TIMER0_VALUE 0x0000FFFFU 126 #define MCPWM_TIMER0_VALUE_M (MCPWM_TIMER0_VALUE_V << MCPWM_TIMER0_VALUE_S) 127 #define MCPWM_TIMER0_VALUE_V 0x0000FFFFU 128 #define MCPWM_TIMER0_VALUE_S 0 129 /** MCPWM_TIMER0_DIRECTION : RO; bitpos: [16]; default: 0; 130 * current PWM timer0 counter direction, 0: increment 1: decrement 131 */ 132 #define MCPWM_TIMER0_DIRECTION (BIT(16)) 133 #define MCPWM_TIMER0_DIRECTION_M (MCPWM_TIMER0_DIRECTION_V << MCPWM_TIMER0_DIRECTION_S) 134 #define MCPWM_TIMER0_DIRECTION_V 0x00000001U 135 #define MCPWM_TIMER0_DIRECTION_S 16 136 137 /** MCPWM_TIMER1_CFG0_REG register 138 * PWM timer1 period and update method configuration register. 139 */ 140 #define MCPWM_TIMER1_CFG0_REG(i) (REG_MCPWM_BASE(i) + 0x14) 141 /** MCPWM_TIMER1_PRESCALE : R/W; bitpos: [7:0]; default: 0; 142 * period of PT0_clk = Period of PWM_clk * (PWM_timer1_PRESCALE + 1) 143 */ 144 #define MCPWM_TIMER1_PRESCALE 0x000000FFU 145 #define MCPWM_TIMER1_PRESCALE_M (MCPWM_TIMER1_PRESCALE_V << MCPWM_TIMER1_PRESCALE_S) 146 #define MCPWM_TIMER1_PRESCALE_V 0x000000FFU 147 #define MCPWM_TIMER1_PRESCALE_S 0 148 /** MCPWM_TIMER1_PERIOD : R/W; bitpos: [23:8]; default: 255; 149 * period shadow register of PWM timer1 150 */ 151 #define MCPWM_TIMER1_PERIOD 0x0000FFFFU 152 #define MCPWM_TIMER1_PERIOD_M (MCPWM_TIMER1_PERIOD_V << MCPWM_TIMER1_PERIOD_S) 153 #define MCPWM_TIMER1_PERIOD_V 0x0000FFFFU 154 #define MCPWM_TIMER1_PERIOD_S 8 155 /** MCPWM_TIMER1_PERIOD_UPMETHOD : R/W; bitpos: [25:24]; default: 0; 156 * Update method for active register of PWM timer1 period, 0: immediate, 1: TEZ, 2: 157 * sync, 3: TEZ | sync. TEZ here and below means timer equal zero event 158 */ 159 #define MCPWM_TIMER1_PERIOD_UPMETHOD 0x00000003U 160 #define MCPWM_TIMER1_PERIOD_UPMETHOD_M (MCPWM_TIMER1_PERIOD_UPMETHOD_V << MCPWM_TIMER1_PERIOD_UPMETHOD_S) 161 #define MCPWM_TIMER1_PERIOD_UPMETHOD_V 0x00000003U 162 #define MCPWM_TIMER1_PERIOD_UPMETHOD_S 24 163 164 /** MCPWM_TIMER1_CFG1_REG register 165 * PWM timer1 working mode and start/stop control configuration register. 166 */ 167 #define MCPWM_TIMER1_CFG1_REG(i) (REG_MCPWM_BASE(i) + 0x18) 168 /** MCPWM_TIMER1_START : R/W/SC; bitpos: [2:0]; default: 0; 169 * PWM timer1 start and stop control. 0: if PWM timer1 starts, then stops at TEZ, 1: 170 * if timer1 starts, then stops at TEP, 2: PWM timer1 starts and runs on, 3: timer1 171 * starts and stops at the next TEZ, 4: timer1 starts and stops at the next TEP. TEP 172 * here and below means the event that happens when the timer equals to period 173 */ 174 #define MCPWM_TIMER1_START 0x00000007U 175 #define MCPWM_TIMER1_START_M (MCPWM_TIMER1_START_V << MCPWM_TIMER1_START_S) 176 #define MCPWM_TIMER1_START_V 0x00000007U 177 #define MCPWM_TIMER1_START_S 0 178 /** MCPWM_TIMER1_MOD : R/W; bitpos: [4:3]; default: 0; 179 * PWM timer1 working mode, 0: freeze, 1: increase mode, 2: decrease mode, 3: up-down 180 * mode 181 */ 182 #define MCPWM_TIMER1_MOD 0x00000003U 183 #define MCPWM_TIMER1_MOD_M (MCPWM_TIMER1_MOD_V << MCPWM_TIMER1_MOD_S) 184 #define MCPWM_TIMER1_MOD_V 0x00000003U 185 #define MCPWM_TIMER1_MOD_S 3 186 187 /** MCPWM_TIMER1_SYNC_REG register 188 * PWM timer1 sync function configuration register. 189 */ 190 #define MCPWM_TIMER1_SYNC_REG(i) (REG_MCPWM_BASE(i) + 0x1c) 191 /** MCPWM_TIMER1_SYNCI_EN : R/W; bitpos: [0]; default: 0; 192 * When set, timer reloading with phase on sync input event is enabled. 193 */ 194 #define MCPWM_TIMER1_SYNCI_EN (BIT(0)) 195 #define MCPWM_TIMER1_SYNCI_EN_M (MCPWM_TIMER1_SYNCI_EN_V << MCPWM_TIMER1_SYNCI_EN_S) 196 #define MCPWM_TIMER1_SYNCI_EN_V 0x00000001U 197 #define MCPWM_TIMER1_SYNCI_EN_S 0 198 /** MCPWM_TIMER1_SYNC_SW : R/W; bitpos: [1]; default: 0; 199 * Toggling this bit will trigger a software sync. 200 */ 201 #define MCPWM_TIMER1_SYNC_SW (BIT(1)) 202 #define MCPWM_TIMER1_SYNC_SW_M (MCPWM_TIMER1_SYNC_SW_V << MCPWM_TIMER1_SYNC_SW_S) 203 #define MCPWM_TIMER1_SYNC_SW_V 0x00000001U 204 #define MCPWM_TIMER1_SYNC_SW_S 1 205 /** MCPWM_TIMER1_SYNCO_SEL : R/W; bitpos: [3:2]; default: 0; 206 * PWM timer1 sync_out selection, 0: sync_in, 1: TEZ, 2: TEP, and sync out will always 207 * generate when toggling the reg_timer1_sync_sw bit 208 */ 209 #define MCPWM_TIMER1_SYNCO_SEL 0x00000003U 210 #define MCPWM_TIMER1_SYNCO_SEL_M (MCPWM_TIMER1_SYNCO_SEL_V << MCPWM_TIMER1_SYNCO_SEL_S) 211 #define MCPWM_TIMER1_SYNCO_SEL_V 0x00000003U 212 #define MCPWM_TIMER1_SYNCO_SEL_S 2 213 /** MCPWM_TIMER1_PHASE : R/W; bitpos: [19:4]; default: 0; 214 * phase for timer reload on sync event 215 */ 216 #define MCPWM_TIMER1_PHASE 0x0000FFFFU 217 #define MCPWM_TIMER1_PHASE_M (MCPWM_TIMER1_PHASE_V << MCPWM_TIMER1_PHASE_S) 218 #define MCPWM_TIMER1_PHASE_V 0x0000FFFFU 219 #define MCPWM_TIMER1_PHASE_S 4 220 /** MCPWM_TIMER1_PHASE_DIRECTION : R/W; bitpos: [20]; default: 0; 221 * Configure the PWM timer1's direction when timer1 mode is up-down mode: 222 * 0-increase,1-decrease 223 */ 224 #define MCPWM_TIMER1_PHASE_DIRECTION (BIT(20)) 225 #define MCPWM_TIMER1_PHASE_DIRECTION_M (MCPWM_TIMER1_PHASE_DIRECTION_V << MCPWM_TIMER1_PHASE_DIRECTION_S) 226 #define MCPWM_TIMER1_PHASE_DIRECTION_V 0x00000001U 227 #define MCPWM_TIMER1_PHASE_DIRECTION_S 20 228 229 /** MCPWM_TIMER1_STATUS_REG register 230 * PWM timer1 status register. 231 */ 232 #define MCPWM_TIMER1_STATUS_REG(i) (REG_MCPWM_BASE(i) + 0x20) 233 /** MCPWM_TIMER1_VALUE : RO; bitpos: [15:0]; default: 0; 234 * current PWM timer1 counter value 235 */ 236 #define MCPWM_TIMER1_VALUE 0x0000FFFFU 237 #define MCPWM_TIMER1_VALUE_M (MCPWM_TIMER1_VALUE_V << MCPWM_TIMER1_VALUE_S) 238 #define MCPWM_TIMER1_VALUE_V 0x0000FFFFU 239 #define MCPWM_TIMER1_VALUE_S 0 240 /** MCPWM_TIMER1_DIRECTION : RO; bitpos: [16]; default: 0; 241 * current PWM timer1 counter direction, 0: increment 1: decrement 242 */ 243 #define MCPWM_TIMER1_DIRECTION (BIT(16)) 244 #define MCPWM_TIMER1_DIRECTION_M (MCPWM_TIMER1_DIRECTION_V << MCPWM_TIMER1_DIRECTION_S) 245 #define MCPWM_TIMER1_DIRECTION_V 0x00000001U 246 #define MCPWM_TIMER1_DIRECTION_S 16 247 248 /** MCPWM_TIMER2_CFG0_REG register 249 * PWM timer2 period and update method configuration register. 250 */ 251 #define MCPWM_TIMER2_CFG0_REG(i) (REG_MCPWM_BASE(i) + 0x24) 252 /** MCPWM_TIMER2_PRESCALE : R/W; bitpos: [7:0]; default: 0; 253 * period of PT0_clk = Period of PWM_clk * (PWM_timer2_PRESCALE + 1) 254 */ 255 #define MCPWM_TIMER2_PRESCALE 0x000000FFU 256 #define MCPWM_TIMER2_PRESCALE_M (MCPWM_TIMER2_PRESCALE_V << MCPWM_TIMER2_PRESCALE_S) 257 #define MCPWM_TIMER2_PRESCALE_V 0x000000FFU 258 #define MCPWM_TIMER2_PRESCALE_S 0 259 /** MCPWM_TIMER2_PERIOD : R/W; bitpos: [23:8]; default: 255; 260 * period shadow register of PWM timer2 261 */ 262 #define MCPWM_TIMER2_PERIOD 0x0000FFFFU 263 #define MCPWM_TIMER2_PERIOD_M (MCPWM_TIMER2_PERIOD_V << MCPWM_TIMER2_PERIOD_S) 264 #define MCPWM_TIMER2_PERIOD_V 0x0000FFFFU 265 #define MCPWM_TIMER2_PERIOD_S 8 266 /** MCPWM_TIMER2_PERIOD_UPMETHOD : R/W; bitpos: [25:24]; default: 0; 267 * Update method for active register of PWM timer2 period, 0: immediate, 1: TEZ, 2: 268 * sync, 3: TEZ | sync. TEZ here and below means timer equal zero event 269 */ 270 #define MCPWM_TIMER2_PERIOD_UPMETHOD 0x00000003U 271 #define MCPWM_TIMER2_PERIOD_UPMETHOD_M (MCPWM_TIMER2_PERIOD_UPMETHOD_V << MCPWM_TIMER2_PERIOD_UPMETHOD_S) 272 #define MCPWM_TIMER2_PERIOD_UPMETHOD_V 0x00000003U 273 #define MCPWM_TIMER2_PERIOD_UPMETHOD_S 24 274 275 /** MCPWM_TIMER2_CFG1_REG register 276 * PWM timer2 working mode and start/stop control configuration register. 277 */ 278 #define MCPWM_TIMER2_CFG1_REG(i) (REG_MCPWM_BASE(i) + 0x28) 279 /** MCPWM_TIMER2_START : R/W/SC; bitpos: [2:0]; default: 0; 280 * PWM timer2 start and stop control. 0: if PWM timer2 starts, then stops at TEZ, 1: 281 * if timer2 starts, then stops at TEP, 2: PWM timer2 starts and runs on, 3: timer2 282 * starts and stops at the next TEZ, 4: timer2 starts and stops at the next TEP. TEP 283 * here and below means the event that happens when the timer equals to period 284 */ 285 #define MCPWM_TIMER2_START 0x00000007U 286 #define MCPWM_TIMER2_START_M (MCPWM_TIMER2_START_V << MCPWM_TIMER2_START_S) 287 #define MCPWM_TIMER2_START_V 0x00000007U 288 #define MCPWM_TIMER2_START_S 0 289 /** MCPWM_TIMER2_MOD : R/W; bitpos: [4:3]; default: 0; 290 * PWM timer2 working mode, 0: freeze, 1: increase mode, 2: decrease mode, 3: up-down 291 * mode 292 */ 293 #define MCPWM_TIMER2_MOD 0x00000003U 294 #define MCPWM_TIMER2_MOD_M (MCPWM_TIMER2_MOD_V << MCPWM_TIMER2_MOD_S) 295 #define MCPWM_TIMER2_MOD_V 0x00000003U 296 #define MCPWM_TIMER2_MOD_S 3 297 298 /** MCPWM_TIMER2_SYNC_REG register 299 * PWM timer2 sync function configuration register. 300 */ 301 #define MCPWM_TIMER2_SYNC_REG(i) (REG_MCPWM_BASE(i) + 0x2c) 302 /** MCPWM_TIMER2_SYNCI_EN : R/W; bitpos: [0]; default: 0; 303 * When set, timer reloading with phase on sync input event is enabled. 304 */ 305 #define MCPWM_TIMER2_SYNCI_EN (BIT(0)) 306 #define MCPWM_TIMER2_SYNCI_EN_M (MCPWM_TIMER2_SYNCI_EN_V << MCPWM_TIMER2_SYNCI_EN_S) 307 #define MCPWM_TIMER2_SYNCI_EN_V 0x00000001U 308 #define MCPWM_TIMER2_SYNCI_EN_S 0 309 /** MCPWM_TIMER2_SYNC_SW : R/W; bitpos: [1]; default: 0; 310 * Toggling this bit will trigger a software sync. 311 */ 312 #define MCPWM_TIMER2_SYNC_SW (BIT(1)) 313 #define MCPWM_TIMER2_SYNC_SW_M (MCPWM_TIMER2_SYNC_SW_V << MCPWM_TIMER2_SYNC_SW_S) 314 #define MCPWM_TIMER2_SYNC_SW_V 0x00000001U 315 #define MCPWM_TIMER2_SYNC_SW_S 1 316 /** MCPWM_TIMER2_SYNCO_SEL : R/W; bitpos: [3:2]; default: 0; 317 * PWM timer2 sync_out selection, 0: sync_in, 1: TEZ, 2: TEP, and sync out will always 318 * generate when toggling the reg_timer0_sync_sw bit 319 */ 320 #define MCPWM_TIMER2_SYNCO_SEL 0x00000003U 321 #define MCPWM_TIMER2_SYNCO_SEL_M (MCPWM_TIMER2_SYNCO_SEL_V << MCPWM_TIMER2_SYNCO_SEL_S) 322 #define MCPWM_TIMER2_SYNCO_SEL_V 0x00000003U 323 #define MCPWM_TIMER2_SYNCO_SEL_S 2 324 /** MCPWM_TIMER2_PHASE : R/W; bitpos: [19:4]; default: 0; 325 * phase for timer reload on sync event 326 */ 327 #define MCPWM_TIMER2_PHASE 0x0000FFFFU 328 #define MCPWM_TIMER2_PHASE_M (MCPWM_TIMER2_PHASE_V << MCPWM_TIMER2_PHASE_S) 329 #define MCPWM_TIMER2_PHASE_V 0x0000FFFFU 330 #define MCPWM_TIMER2_PHASE_S 4 331 /** MCPWM_TIMER2_PHASE_DIRECTION : R/W; bitpos: [20]; default: 0; 332 * Configure the PWM timer2's direction when timer2 mode is up-down mode: 333 * 0-increase,1-decrease 334 */ 335 #define MCPWM_TIMER2_PHASE_DIRECTION (BIT(20)) 336 #define MCPWM_TIMER2_PHASE_DIRECTION_M (MCPWM_TIMER2_PHASE_DIRECTION_V << MCPWM_TIMER2_PHASE_DIRECTION_S) 337 #define MCPWM_TIMER2_PHASE_DIRECTION_V 0x00000001U 338 #define MCPWM_TIMER2_PHASE_DIRECTION_S 20 339 340 /** MCPWM_TIMER2_STATUS_REG register 341 * PWM timer2 status register. 342 */ 343 #define MCPWM_TIMER2_STATUS_REG(i) (REG_MCPWM_BASE(i) + 0x30) 344 /** MCPWM_TIMER2_VALUE : RO; bitpos: [15:0]; default: 0; 345 * current PWM timer2 counter value 346 */ 347 #define MCPWM_TIMER2_VALUE 0x0000FFFFU 348 #define MCPWM_TIMER2_VALUE_M (MCPWM_TIMER2_VALUE_V << MCPWM_TIMER2_VALUE_S) 349 #define MCPWM_TIMER2_VALUE_V 0x0000FFFFU 350 #define MCPWM_TIMER2_VALUE_S 0 351 /** MCPWM_TIMER2_DIRECTION : RO; bitpos: [16]; default: 0; 352 * current PWM timer2 counter direction, 0: increment 1: decrement 353 */ 354 #define MCPWM_TIMER2_DIRECTION (BIT(16)) 355 #define MCPWM_TIMER2_DIRECTION_M (MCPWM_TIMER2_DIRECTION_V << MCPWM_TIMER2_DIRECTION_S) 356 #define MCPWM_TIMER2_DIRECTION_V 0x00000001U 357 #define MCPWM_TIMER2_DIRECTION_S 16 358 359 /** MCPWM_TIMER_SYNCI_CFG_REG register 360 * Synchronization input selection for three PWM timers. 361 */ 362 #define MCPWM_TIMER_SYNCI_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x34) 363 /** MCPWM_TIMER0_SYNCISEL : R/W; bitpos: [2:0]; default: 0; 364 * select sync input for PWM timer0, 1: PWM timer0 sync_out, 2: PWM timer1 sync_out, 365 * 3: PWM timer2 sync_out, 4: SYNC0 from GPIO matrix, 5: SYNC1 from GPIO matrix, 6: 366 * SYNC2 from GPIO matrix, other values: no sync input selected 367 */ 368 #define MCPWM_TIMER0_SYNCISEL 0x00000007U 369 #define MCPWM_TIMER0_SYNCISEL_M (MCPWM_TIMER0_SYNCISEL_V << MCPWM_TIMER0_SYNCISEL_S) 370 #define MCPWM_TIMER0_SYNCISEL_V 0x00000007U 371 #define MCPWM_TIMER0_SYNCISEL_S 0 372 /** MCPWM_TIMER1_SYNCISEL : R/W; bitpos: [5:3]; default: 0; 373 * select sync input for PWM timer1, 1: PWM timer0 sync_out, 2: PWM timer1 sync_out, 374 * 3: PWM timer2 sync_out, 4: SYNC0 from GPIO matrix, 5: SYNC1 from GPIO matrix, 6: 375 * SYNC2 from GPIO matrix, other values: no sync input selected 376 */ 377 #define MCPWM_TIMER1_SYNCISEL 0x00000007U 378 #define MCPWM_TIMER1_SYNCISEL_M (MCPWM_TIMER1_SYNCISEL_V << MCPWM_TIMER1_SYNCISEL_S) 379 #define MCPWM_TIMER1_SYNCISEL_V 0x00000007U 380 #define MCPWM_TIMER1_SYNCISEL_S 3 381 /** MCPWM_TIMER2_SYNCISEL : R/W; bitpos: [8:6]; default: 0; 382 * select sync input for PWM timer2, 1: PWM timer0 sync_out, 2: PWM timer1 sync_out, 383 * 3: PWM timer2 sync_out, 4: SYNC0 from GPIO matrix, 5: SYNC1 from GPIO matrix, 6: 384 * SYNC2 from GPIO matrix, other values: no sync input selected 385 */ 386 #define MCPWM_TIMER2_SYNCISEL 0x00000007U 387 #define MCPWM_TIMER2_SYNCISEL_M (MCPWM_TIMER2_SYNCISEL_V << MCPWM_TIMER2_SYNCISEL_S) 388 #define MCPWM_TIMER2_SYNCISEL_V 0x00000007U 389 #define MCPWM_TIMER2_SYNCISEL_S 6 390 /** MCPWM_EXTERNAL_SYNCI0_INVERT : R/W; bitpos: [9]; default: 0; 391 * invert SYNC0 from GPIO matrix 392 */ 393 #define MCPWM_EXTERNAL_SYNCI0_INVERT (BIT(9)) 394 #define MCPWM_EXTERNAL_SYNCI0_INVERT_M (MCPWM_EXTERNAL_SYNCI0_INVERT_V << MCPWM_EXTERNAL_SYNCI0_INVERT_S) 395 #define MCPWM_EXTERNAL_SYNCI0_INVERT_V 0x00000001U 396 #define MCPWM_EXTERNAL_SYNCI0_INVERT_S 9 397 /** MCPWM_EXTERNAL_SYNCI1_INVERT : R/W; bitpos: [10]; default: 0; 398 * invert SYNC1 from GPIO matrix 399 */ 400 #define MCPWM_EXTERNAL_SYNCI1_INVERT (BIT(10)) 401 #define MCPWM_EXTERNAL_SYNCI1_INVERT_M (MCPWM_EXTERNAL_SYNCI1_INVERT_V << MCPWM_EXTERNAL_SYNCI1_INVERT_S) 402 #define MCPWM_EXTERNAL_SYNCI1_INVERT_V 0x00000001U 403 #define MCPWM_EXTERNAL_SYNCI1_INVERT_S 10 404 /** MCPWM_EXTERNAL_SYNCI2_INVERT : R/W; bitpos: [11]; default: 0; 405 * invert SYNC2 from GPIO matrix 406 */ 407 #define MCPWM_EXTERNAL_SYNCI2_INVERT (BIT(11)) 408 #define MCPWM_EXTERNAL_SYNCI2_INVERT_M (MCPWM_EXTERNAL_SYNCI2_INVERT_V << MCPWM_EXTERNAL_SYNCI2_INVERT_S) 409 #define MCPWM_EXTERNAL_SYNCI2_INVERT_V 0x00000001U 410 #define MCPWM_EXTERNAL_SYNCI2_INVERT_S 11 411 412 /** MCPWM_OPERATOR_TIMERSEL_REG register 413 * Select specific timer for PWM operators. 414 */ 415 #define MCPWM_OPERATOR_TIMERSEL_REG(i) (REG_MCPWM_BASE(i) + 0x38) 416 /** MCPWM_OPERATOR0_TIMERSEL : R/W; bitpos: [1:0]; default: 0; 417 * Select which PWM timer's is the timing reference for PWM operator0, 0: timer0, 1: 418 * timer1, 2: timer2 419 */ 420 #define MCPWM_OPERATOR0_TIMERSEL 0x00000003U 421 #define MCPWM_OPERATOR0_TIMERSEL_M (MCPWM_OPERATOR0_TIMERSEL_V << MCPWM_OPERATOR0_TIMERSEL_S) 422 #define MCPWM_OPERATOR0_TIMERSEL_V 0x00000003U 423 #define MCPWM_OPERATOR0_TIMERSEL_S 0 424 /** MCPWM_OPERATOR1_TIMERSEL : R/W; bitpos: [3:2]; default: 0; 425 * Select which PWM timer's is the timing reference for PWM operator1, 0: timer0, 1: 426 * timer1, 2: timer2 427 */ 428 #define MCPWM_OPERATOR1_TIMERSEL 0x00000003U 429 #define MCPWM_OPERATOR1_TIMERSEL_M (MCPWM_OPERATOR1_TIMERSEL_V << MCPWM_OPERATOR1_TIMERSEL_S) 430 #define MCPWM_OPERATOR1_TIMERSEL_V 0x00000003U 431 #define MCPWM_OPERATOR1_TIMERSEL_S 2 432 /** MCPWM_OPERATOR2_TIMERSEL : R/W; bitpos: [5:4]; default: 0; 433 * Select which PWM timer's is the timing reference for PWM operator2, 0: timer0, 1: 434 * timer1, 2: timer2 435 */ 436 #define MCPWM_OPERATOR2_TIMERSEL 0x00000003U 437 #define MCPWM_OPERATOR2_TIMERSEL_M (MCPWM_OPERATOR2_TIMERSEL_V << MCPWM_OPERATOR2_TIMERSEL_S) 438 #define MCPWM_OPERATOR2_TIMERSEL_V 0x00000003U 439 #define MCPWM_OPERATOR2_TIMERSEL_S 4 440 441 /** MCPWM_GEN0_STMP_CFG_REG register 442 * Transfer status and update method for time stamp registers A and B 443 */ 444 #define MCPWM_GEN0_STMP_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x3c) 445 /** MCPWM_CMPR0_A_UPMETHOD : R/W; bitpos: [3:0]; default: 0; 446 * Update method for PWM generator 0 time stamp A's active register. When all bits are 447 * set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1: TEP,when 448 * bit2 is set to 1: sync, when bit3 is set to 1: disable the update. 449 */ 450 #define MCPWM_CMPR0_A_UPMETHOD 0x0000000FU 451 #define MCPWM_CMPR0_A_UPMETHOD_M (MCPWM_CMPR0_A_UPMETHOD_V << MCPWM_CMPR0_A_UPMETHOD_S) 452 #define MCPWM_CMPR0_A_UPMETHOD_V 0x0000000FU 453 #define MCPWM_CMPR0_A_UPMETHOD_S 0 454 /** MCPWM_CMPR0_B_UPMETHOD : R/W; bitpos: [7:4]; default: 0; 455 * Update method for PWM generator 0 time stamp B's active register. When all bits are 456 * set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1: TEP,when 457 * bit2 is set to 1: sync, when bit3 is set to 1: disable the update. 458 */ 459 #define MCPWM_CMPR0_B_UPMETHOD 0x0000000FU 460 #define MCPWM_CMPR0_B_UPMETHOD_M (MCPWM_CMPR0_B_UPMETHOD_V << MCPWM_CMPR0_B_UPMETHOD_S) 461 #define MCPWM_CMPR0_B_UPMETHOD_V 0x0000000FU 462 #define MCPWM_CMPR0_B_UPMETHOD_S 4 463 /** MCPWM_CMPR0_A_SHDW_FULL : R/W/WTC/SC; bitpos: [8]; default: 0; 464 * Set and reset by hardware. If set, PWM generator 0 time stamp A's shadow reg is 465 * filled and waiting to be transferred to A's active reg. If cleared, A's active reg 466 * has been updated with shadow register latest value 467 */ 468 #define MCPWM_CMPR0_A_SHDW_FULL (BIT(8)) 469 #define MCPWM_CMPR0_A_SHDW_FULL_M (MCPWM_CMPR0_A_SHDW_FULL_V << MCPWM_CMPR0_A_SHDW_FULL_S) 470 #define MCPWM_CMPR0_A_SHDW_FULL_V 0x00000001U 471 #define MCPWM_CMPR0_A_SHDW_FULL_S 8 472 /** MCPWM_CMPR0_B_SHDW_FULL : R/W/WTC/SC; bitpos: [9]; default: 0; 473 * Set and reset by hardware. If set, PWM generator 0 time stamp B's shadow reg is 474 * filled and waiting to be transferred to B's active reg. If cleared, B's active reg 475 * has been updated with shadow register latest value 476 */ 477 #define MCPWM_CMPR0_B_SHDW_FULL (BIT(9)) 478 #define MCPWM_CMPR0_B_SHDW_FULL_M (MCPWM_CMPR0_B_SHDW_FULL_V << MCPWM_CMPR0_B_SHDW_FULL_S) 479 #define MCPWM_CMPR0_B_SHDW_FULL_V 0x00000001U 480 #define MCPWM_CMPR0_B_SHDW_FULL_S 9 481 482 /** MCPWM_GEN0_TSTMP_A_REG register 483 * Shadow register for register A. 484 */ 485 #define MCPWM_GEN0_TSTMP_A_REG(i) (REG_MCPWM_BASE(i) + 0x40) 486 /** MCPWM_CMPR0_A : R/W; bitpos: [15:0]; default: 0; 487 * PWM generator 0 time stamp A's shadow register 488 */ 489 #define MCPWM_CMPR0_A 0x0000FFFFU 490 #define MCPWM_CMPR0_A_M (MCPWM_CMPR0_A_V << MCPWM_CMPR0_A_S) 491 #define MCPWM_CMPR0_A_V 0x0000FFFFU 492 #define MCPWM_CMPR0_A_S 0 493 494 /** MCPWM_GEN0_TSTMP_B_REG register 495 * Shadow register for register B. 496 */ 497 #define MCPWM_GEN0_TSTMP_B_REG(i) (REG_MCPWM_BASE(i) + 0x44) 498 /** MCPWM_CMPR0_B : R/W; bitpos: [15:0]; default: 0; 499 * PWM generator 0 time stamp B's shadow register 500 */ 501 #define MCPWM_CMPR0_B 0x0000FFFFU 502 #define MCPWM_CMPR0_B_M (MCPWM_CMPR0_B_V << MCPWM_CMPR0_B_S) 503 #define MCPWM_CMPR0_B_V 0x0000FFFFU 504 #define MCPWM_CMPR0_B_S 0 505 506 /** MCPWM_GEN0_CFG0_REG register 507 * Fault event T0 and T1 handling 508 */ 509 #define MCPWM_GEN0_CFG0_REG(i) (REG_MCPWM_BASE(i) + 0x48) 510 /** MCPWM_GEN0_CFG_UPMETHOD : R/W; bitpos: [3:0]; default: 0; 511 * Update method for PWM generator 0's active register of configuration. When all bits 512 * are set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 513 * 1:TEP,when bit2 is set to 1:sync,when bit3 is set to 1:disable the update 514 */ 515 #define MCPWM_GEN0_CFG_UPMETHOD 0x0000000FU 516 #define MCPWM_GEN0_CFG_UPMETHOD_M (MCPWM_GEN0_CFG_UPMETHOD_V << MCPWM_GEN0_CFG_UPMETHOD_S) 517 #define MCPWM_GEN0_CFG_UPMETHOD_V 0x0000000FU 518 #define MCPWM_GEN0_CFG_UPMETHOD_S 0 519 /** MCPWM_GEN0_T0_SEL : R/W; bitpos: [6:4]; default: 0; 520 * Source selection for PWM generator 0 event_t0, take effect immediately, 0: 521 * fault_event0, 1: fault_event1, 2: fault_event2, 3: sync_taken, 4: none 522 */ 523 #define MCPWM_GEN0_T0_SEL 0x00000007U 524 #define MCPWM_GEN0_T0_SEL_M (MCPWM_GEN0_T0_SEL_V << MCPWM_GEN0_T0_SEL_S) 525 #define MCPWM_GEN0_T0_SEL_V 0x00000007U 526 #define MCPWM_GEN0_T0_SEL_S 4 527 /** MCPWM_GEN0_T1_SEL : R/W; bitpos: [9:7]; default: 0; 528 * Source selection for PWM generator 0 event_t1, take effect immediately, 0: 529 * fault_event0, 1: fault_event1, 2: fault_event2, 3: sync_taken, 4: none 530 */ 531 #define MCPWM_GEN0_T1_SEL 0x00000007U 532 #define MCPWM_GEN0_T1_SEL_M (MCPWM_GEN0_T1_SEL_V << MCPWM_GEN0_T1_SEL_S) 533 #define MCPWM_GEN0_T1_SEL_V 0x00000007U 534 #define MCPWM_GEN0_T1_SEL_S 7 535 536 /** MCPWM_GEN0_FORCE_REG register 537 * Permissives to force PWM0A and PWM0B outputs by software 538 */ 539 #define MCPWM_GEN0_FORCE_REG(i) (REG_MCPWM_BASE(i) + 0x4c) 540 /** MCPWM_GEN0_CNTUFORCE_UPMETHOD : R/W; bitpos: [5:0]; default: 32; 541 * Updating method for continuous software force of PWM generator0. When all bits are 542 * set to 0: immediately, when bit0 is set to 1: TEZ,,when bit1 is set to 1: TEP, when 543 * bit2 is set to 1: TEA, when bit3 is set to 1: TEB, when bit4 is set to 1: sync, 544 * when bit5 is set to 1: disable update. (TEA/B here and below means an event 545 * generated when the timer's value equals to that of register A/B.) 546 */ 547 #define MCPWM_GEN0_CNTUFORCE_UPMETHOD 0x0000003FU 548 #define MCPWM_GEN0_CNTUFORCE_UPMETHOD_M (MCPWM_GEN0_CNTUFORCE_UPMETHOD_V << MCPWM_GEN0_CNTUFORCE_UPMETHOD_S) 549 #define MCPWM_GEN0_CNTUFORCE_UPMETHOD_V 0x0000003FU 550 #define MCPWM_GEN0_CNTUFORCE_UPMETHOD_S 0 551 /** MCPWM_GEN0_A_CNTUFORCE_MODE : R/W; bitpos: [7:6]; default: 0; 552 * Continuous software force mode for PWM0A. 0: disabled, 1: low, 2: high, 3: disabled 553 */ 554 #define MCPWM_GEN0_A_CNTUFORCE_MODE 0x00000003U 555 #define MCPWM_GEN0_A_CNTUFORCE_MODE_M (MCPWM_GEN0_A_CNTUFORCE_MODE_V << MCPWM_GEN0_A_CNTUFORCE_MODE_S) 556 #define MCPWM_GEN0_A_CNTUFORCE_MODE_V 0x00000003U 557 #define MCPWM_GEN0_A_CNTUFORCE_MODE_S 6 558 /** MCPWM_GEN0_B_CNTUFORCE_MODE : R/W; bitpos: [9:8]; default: 0; 559 * Continuous software force mode for PWM0B. 0: disabled, 1: low, 2: high, 3: disabled 560 */ 561 #define MCPWM_GEN0_B_CNTUFORCE_MODE 0x00000003U 562 #define MCPWM_GEN0_B_CNTUFORCE_MODE_M (MCPWM_GEN0_B_CNTUFORCE_MODE_V << MCPWM_GEN0_B_CNTUFORCE_MODE_S) 563 #define MCPWM_GEN0_B_CNTUFORCE_MODE_V 0x00000003U 564 #define MCPWM_GEN0_B_CNTUFORCE_MODE_S 8 565 /** MCPWM_GEN0_A_NCIFORCE : R/W; bitpos: [10]; default: 0; 566 * Trigger of non-continuous immediate software-force event for PWM0A, a toggle will 567 * trigger a force event. 568 */ 569 #define MCPWM_GEN0_A_NCIFORCE (BIT(10)) 570 #define MCPWM_GEN0_A_NCIFORCE_M (MCPWM_GEN0_A_NCIFORCE_V << MCPWM_GEN0_A_NCIFORCE_S) 571 #define MCPWM_GEN0_A_NCIFORCE_V 0x00000001U 572 #define MCPWM_GEN0_A_NCIFORCE_S 10 573 /** MCPWM_GEN0_A_NCIFORCE_MODE : R/W; bitpos: [12:11]; default: 0; 574 * non-continuous immediate software force mode for PWM0A, 0: disabled, 1: low, 2: 575 * high, 3: disabled 576 */ 577 #define MCPWM_GEN0_A_NCIFORCE_MODE 0x00000003U 578 #define MCPWM_GEN0_A_NCIFORCE_MODE_M (MCPWM_GEN0_A_NCIFORCE_MODE_V << MCPWM_GEN0_A_NCIFORCE_MODE_S) 579 #define MCPWM_GEN0_A_NCIFORCE_MODE_V 0x00000003U 580 #define MCPWM_GEN0_A_NCIFORCE_MODE_S 11 581 /** MCPWM_GEN0_B_NCIFORCE : R/W; bitpos: [13]; default: 0; 582 * Trigger of non-continuous immediate software-force event for PWM0B, a toggle will 583 * trigger a force event. 584 */ 585 #define MCPWM_GEN0_B_NCIFORCE (BIT(13)) 586 #define MCPWM_GEN0_B_NCIFORCE_M (MCPWM_GEN0_B_NCIFORCE_V << MCPWM_GEN0_B_NCIFORCE_S) 587 #define MCPWM_GEN0_B_NCIFORCE_V 0x00000001U 588 #define MCPWM_GEN0_B_NCIFORCE_S 13 589 /** MCPWM_GEN0_B_NCIFORCE_MODE : R/W; bitpos: [15:14]; default: 0; 590 * non-continuous immediate software force mode for PWM0B, 0: disabled, 1: low, 2: 591 * high, 3: disabled 592 */ 593 #define MCPWM_GEN0_B_NCIFORCE_MODE 0x00000003U 594 #define MCPWM_GEN0_B_NCIFORCE_MODE_M (MCPWM_GEN0_B_NCIFORCE_MODE_V << MCPWM_GEN0_B_NCIFORCE_MODE_S) 595 #define MCPWM_GEN0_B_NCIFORCE_MODE_V 0x00000003U 596 #define MCPWM_GEN0_B_NCIFORCE_MODE_S 14 597 598 /** MCPWM_GEN0_A_REG register 599 * Actions triggered by events on PWM0A 600 */ 601 #define MCPWM_GEN0_A_REG(i) (REG_MCPWM_BASE(i) + 0x50) 602 /** MCPWM_GEN0_A_UTEZ : R/W; bitpos: [1:0]; default: 0; 603 * Action on PWM0A triggered by event TEZ when timer increasing 604 */ 605 #define MCPWM_GEN0_A_UTEZ 0x00000003U 606 #define MCPWM_GEN0_A_UTEZ_M (MCPWM_GEN0_A_UTEZ_V << MCPWM_GEN0_A_UTEZ_S) 607 #define MCPWM_GEN0_A_UTEZ_V 0x00000003U 608 #define MCPWM_GEN0_A_UTEZ_S 0 609 /** MCPWM_GEN0_A_UTEP : R/W; bitpos: [3:2]; default: 0; 610 * Action on PWM0A triggered by event TEP when timer increasing 611 */ 612 #define MCPWM_GEN0_A_UTEP 0x00000003U 613 #define MCPWM_GEN0_A_UTEP_M (MCPWM_GEN0_A_UTEP_V << MCPWM_GEN0_A_UTEP_S) 614 #define MCPWM_GEN0_A_UTEP_V 0x00000003U 615 #define MCPWM_GEN0_A_UTEP_S 2 616 /** MCPWM_GEN0_A_UTEA : R/W; bitpos: [5:4]; default: 0; 617 * Action on PWM0A triggered by event TEA when timer increasing 618 */ 619 #define MCPWM_GEN0_A_UTEA 0x00000003U 620 #define MCPWM_GEN0_A_UTEA_M (MCPWM_GEN0_A_UTEA_V << MCPWM_GEN0_A_UTEA_S) 621 #define MCPWM_GEN0_A_UTEA_V 0x00000003U 622 #define MCPWM_GEN0_A_UTEA_S 4 623 /** MCPWM_GEN0_A_UTEB : R/W; bitpos: [7:6]; default: 0; 624 * Action on PWM0A triggered by event TEB when timer increasing 625 */ 626 #define MCPWM_GEN0_A_UTEB 0x00000003U 627 #define MCPWM_GEN0_A_UTEB_M (MCPWM_GEN0_A_UTEB_V << MCPWM_GEN0_A_UTEB_S) 628 #define MCPWM_GEN0_A_UTEB_V 0x00000003U 629 #define MCPWM_GEN0_A_UTEB_S 6 630 /** MCPWM_GEN0_A_UT0 : R/W; bitpos: [9:8]; default: 0; 631 * Action on PWM0A triggered by event_t0 when timer increasing 632 */ 633 #define MCPWM_GEN0_A_UT0 0x00000003U 634 #define MCPWM_GEN0_A_UT0_M (MCPWM_GEN0_A_UT0_V << MCPWM_GEN0_A_UT0_S) 635 #define MCPWM_GEN0_A_UT0_V 0x00000003U 636 #define MCPWM_GEN0_A_UT0_S 8 637 /** MCPWM_GEN0_A_UT1 : R/W; bitpos: [11:10]; default: 0; 638 * Action on PWM0A triggered by event_t1 when timer increasing 639 */ 640 #define MCPWM_GEN0_A_UT1 0x00000003U 641 #define MCPWM_GEN0_A_UT1_M (MCPWM_GEN0_A_UT1_V << MCPWM_GEN0_A_UT1_S) 642 #define MCPWM_GEN0_A_UT1_V 0x00000003U 643 #define MCPWM_GEN0_A_UT1_S 10 644 /** MCPWM_GEN0_A_DTEZ : R/W; bitpos: [13:12]; default: 0; 645 * Action on PWM0A triggered by event TEZ when timer decreasing 646 */ 647 #define MCPWM_GEN0_A_DTEZ 0x00000003U 648 #define MCPWM_GEN0_A_DTEZ_M (MCPWM_GEN0_A_DTEZ_V << MCPWM_GEN0_A_DTEZ_S) 649 #define MCPWM_GEN0_A_DTEZ_V 0x00000003U 650 #define MCPWM_GEN0_A_DTEZ_S 12 651 /** MCPWM_GEN0_A_DTEP : R/W; bitpos: [15:14]; default: 0; 652 * Action on PWM0A triggered by event TEP when timer decreasing 653 */ 654 #define MCPWM_GEN0_A_DTEP 0x00000003U 655 #define MCPWM_GEN0_A_DTEP_M (MCPWM_GEN0_A_DTEP_V << MCPWM_GEN0_A_DTEP_S) 656 #define MCPWM_GEN0_A_DTEP_V 0x00000003U 657 #define MCPWM_GEN0_A_DTEP_S 14 658 /** MCPWM_GEN0_A_DTEA : R/W; bitpos: [17:16]; default: 0; 659 * Action on PWM0A triggered by event TEA when timer decreasing 660 */ 661 #define MCPWM_GEN0_A_DTEA 0x00000003U 662 #define MCPWM_GEN0_A_DTEA_M (MCPWM_GEN0_A_DTEA_V << MCPWM_GEN0_A_DTEA_S) 663 #define MCPWM_GEN0_A_DTEA_V 0x00000003U 664 #define MCPWM_GEN0_A_DTEA_S 16 665 /** MCPWM_GEN0_A_DTEB : R/W; bitpos: [19:18]; default: 0; 666 * Action on PWM0A triggered by event TEB when timer decreasing 667 */ 668 #define MCPWM_GEN0_A_DTEB 0x00000003U 669 #define MCPWM_GEN0_A_DTEB_M (MCPWM_GEN0_A_DTEB_V << MCPWM_GEN0_A_DTEB_S) 670 #define MCPWM_GEN0_A_DTEB_V 0x00000003U 671 #define MCPWM_GEN0_A_DTEB_S 18 672 /** MCPWM_GEN0_A_DT0 : R/W; bitpos: [21:20]; default: 0; 673 * Action on PWM0A triggered by event_t0 when timer decreasing 674 */ 675 #define MCPWM_GEN0_A_DT0 0x00000003U 676 #define MCPWM_GEN0_A_DT0_M (MCPWM_GEN0_A_DT0_V << MCPWM_GEN0_A_DT0_S) 677 #define MCPWM_GEN0_A_DT0_V 0x00000003U 678 #define MCPWM_GEN0_A_DT0_S 20 679 /** MCPWM_GEN0_A_DT1 : R/W; bitpos: [23:22]; default: 0; 680 * Action on PWM0A triggered by event_t1 when timer decreasing. 0: no change, 1: low, 681 * 2: high, 3: toggle 682 */ 683 #define MCPWM_GEN0_A_DT1 0x00000003U 684 #define MCPWM_GEN0_A_DT1_M (MCPWM_GEN0_A_DT1_V << MCPWM_GEN0_A_DT1_S) 685 #define MCPWM_GEN0_A_DT1_V 0x00000003U 686 #define MCPWM_GEN0_A_DT1_S 22 687 688 /** MCPWM_GEN0_B_REG register 689 * Actions triggered by events on PWM0B 690 */ 691 #define MCPWM_GEN0_B_REG(i) (REG_MCPWM_BASE(i) + 0x54) 692 /** MCPWM_GEN0_B_UTEZ : R/W; bitpos: [1:0]; default: 0; 693 * Action on PWM0B triggered by event TEZ when timer increasing 694 */ 695 #define MCPWM_GEN0_B_UTEZ 0x00000003U 696 #define MCPWM_GEN0_B_UTEZ_M (MCPWM_GEN0_B_UTEZ_V << MCPWM_GEN0_B_UTEZ_S) 697 #define MCPWM_GEN0_B_UTEZ_V 0x00000003U 698 #define MCPWM_GEN0_B_UTEZ_S 0 699 /** MCPWM_GEN0_B_UTEP : R/W; bitpos: [3:2]; default: 0; 700 * Action on PWM0B triggered by event TEP when timer increasing 701 */ 702 #define MCPWM_GEN0_B_UTEP 0x00000003U 703 #define MCPWM_GEN0_B_UTEP_M (MCPWM_GEN0_B_UTEP_V << MCPWM_GEN0_B_UTEP_S) 704 #define MCPWM_GEN0_B_UTEP_V 0x00000003U 705 #define MCPWM_GEN0_B_UTEP_S 2 706 /** MCPWM_GEN0_B_UTEA : R/W; bitpos: [5:4]; default: 0; 707 * Action on PWM0B triggered by event TEA when timer increasing 708 */ 709 #define MCPWM_GEN0_B_UTEA 0x00000003U 710 #define MCPWM_GEN0_B_UTEA_M (MCPWM_GEN0_B_UTEA_V << MCPWM_GEN0_B_UTEA_S) 711 #define MCPWM_GEN0_B_UTEA_V 0x00000003U 712 #define MCPWM_GEN0_B_UTEA_S 4 713 /** MCPWM_GEN0_B_UTEB : R/W; bitpos: [7:6]; default: 0; 714 * Action on PWM0B triggered by event TEB when timer increasing 715 */ 716 #define MCPWM_GEN0_B_UTEB 0x00000003U 717 #define MCPWM_GEN0_B_UTEB_M (MCPWM_GEN0_B_UTEB_V << MCPWM_GEN0_B_UTEB_S) 718 #define MCPWM_GEN0_B_UTEB_V 0x00000003U 719 #define MCPWM_GEN0_B_UTEB_S 6 720 /** MCPWM_GEN0_B_UT0 : R/W; bitpos: [9:8]; default: 0; 721 * Action on PWM0B triggered by event_t0 when timer increasing 722 */ 723 #define MCPWM_GEN0_B_UT0 0x00000003U 724 #define MCPWM_GEN0_B_UT0_M (MCPWM_GEN0_B_UT0_V << MCPWM_GEN0_B_UT0_S) 725 #define MCPWM_GEN0_B_UT0_V 0x00000003U 726 #define MCPWM_GEN0_B_UT0_S 8 727 /** MCPWM_GEN0_B_UT1 : R/W; bitpos: [11:10]; default: 0; 728 * Action on PWM0B triggered by event_t1 when timer increasing 729 */ 730 #define MCPWM_GEN0_B_UT1 0x00000003U 731 #define MCPWM_GEN0_B_UT1_M (MCPWM_GEN0_B_UT1_V << MCPWM_GEN0_B_UT1_S) 732 #define MCPWM_GEN0_B_UT1_V 0x00000003U 733 #define MCPWM_GEN0_B_UT1_S 10 734 /** MCPWM_GEN0_B_DTEZ : R/W; bitpos: [13:12]; default: 0; 735 * Action on PWM0B triggered by event TEZ when timer decreasing 736 */ 737 #define MCPWM_GEN0_B_DTEZ 0x00000003U 738 #define MCPWM_GEN0_B_DTEZ_M (MCPWM_GEN0_B_DTEZ_V << MCPWM_GEN0_B_DTEZ_S) 739 #define MCPWM_GEN0_B_DTEZ_V 0x00000003U 740 #define MCPWM_GEN0_B_DTEZ_S 12 741 /** MCPWM_GEN0_B_DTEP : R/W; bitpos: [15:14]; default: 0; 742 * Action on PWM0B triggered by event TEP when timer decreasing 743 */ 744 #define MCPWM_GEN0_B_DTEP 0x00000003U 745 #define MCPWM_GEN0_B_DTEP_M (MCPWM_GEN0_B_DTEP_V << MCPWM_GEN0_B_DTEP_S) 746 #define MCPWM_GEN0_B_DTEP_V 0x00000003U 747 #define MCPWM_GEN0_B_DTEP_S 14 748 /** MCPWM_GEN0_B_DTEA : R/W; bitpos: [17:16]; default: 0; 749 * Action on PWM0B triggered by event TEA when timer decreasing 750 */ 751 #define MCPWM_GEN0_B_DTEA 0x00000003U 752 #define MCPWM_GEN0_B_DTEA_M (MCPWM_GEN0_B_DTEA_V << MCPWM_GEN0_B_DTEA_S) 753 #define MCPWM_GEN0_B_DTEA_V 0x00000003U 754 #define MCPWM_GEN0_B_DTEA_S 16 755 /** MCPWM_GEN0_B_DTEB : R/W; bitpos: [19:18]; default: 0; 756 * Action on PWM0B triggered by event TEB when timer decreasing 757 */ 758 #define MCPWM_GEN0_B_DTEB 0x00000003U 759 #define MCPWM_GEN0_B_DTEB_M (MCPWM_GEN0_B_DTEB_V << MCPWM_GEN0_B_DTEB_S) 760 #define MCPWM_GEN0_B_DTEB_V 0x00000003U 761 #define MCPWM_GEN0_B_DTEB_S 18 762 /** MCPWM_GEN0_B_DT0 : R/W; bitpos: [21:20]; default: 0; 763 * Action on PWM0B triggered by event_t0 when timer decreasing 764 */ 765 #define MCPWM_GEN0_B_DT0 0x00000003U 766 #define MCPWM_GEN0_B_DT0_M (MCPWM_GEN0_B_DT0_V << MCPWM_GEN0_B_DT0_S) 767 #define MCPWM_GEN0_B_DT0_V 0x00000003U 768 #define MCPWM_GEN0_B_DT0_S 20 769 /** MCPWM_GEN0_B_DT1 : R/W; bitpos: [23:22]; default: 0; 770 * Action on PWM0B triggered by event_t1 when timer decreasing. 0: no change, 1: low, 771 * 2: high, 3: toggle 772 */ 773 #define MCPWM_GEN0_B_DT1 0x00000003U 774 #define MCPWM_GEN0_B_DT1_M (MCPWM_GEN0_B_DT1_V << MCPWM_GEN0_B_DT1_S) 775 #define MCPWM_GEN0_B_DT1_V 0x00000003U 776 #define MCPWM_GEN0_B_DT1_S 22 777 778 /** MCPWM_DT0_CFG_REG register 779 * dead time type selection and configuration 780 */ 781 #define MCPWM_DT0_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x58) 782 /** MCPWM_DB0_FED_UPMETHOD : R/W; bitpos: [3:0]; default: 0; 783 * Update method for FED (rising edge delay) active register. 0: immediate, when bit0 784 * is set to 1: tez, when bit1 is set to 1:tep, when bit2 is set to 1: sync, when 785 * bit3 is set to 1: disable the update 786 */ 787 #define MCPWM_DB0_FED_UPMETHOD 0x0000000FU 788 #define MCPWM_DB0_FED_UPMETHOD_M (MCPWM_DB0_FED_UPMETHOD_V << MCPWM_DB0_FED_UPMETHOD_S) 789 #define MCPWM_DB0_FED_UPMETHOD_V 0x0000000FU 790 #define MCPWM_DB0_FED_UPMETHOD_S 0 791 /** MCPWM_DB0_RED_UPMETHOD : R/W; bitpos: [7:4]; default: 0; 792 * Update method for RED (rising edge delay) active register. 0: immediate, when bit0 793 * is set to 1: tez, when bit1 is set to 1:tep, when bit2 is set to 1: sync, when 794 * bit3 is set to 1: disable the update 795 */ 796 #define MCPWM_DB0_RED_UPMETHOD 0x0000000FU 797 #define MCPWM_DB0_RED_UPMETHOD_M (MCPWM_DB0_RED_UPMETHOD_V << MCPWM_DB0_RED_UPMETHOD_S) 798 #define MCPWM_DB0_RED_UPMETHOD_V 0x0000000FU 799 #define MCPWM_DB0_RED_UPMETHOD_S 4 800 /** MCPWM_DB0_DEB_MODE : R/W; bitpos: [8]; default: 0; 801 * S8 in table, dual-edge B mode, 0: fed/red take effect on different path separately, 802 * 1: fed/red take effect on B path, A out is in bypass or dulpB mode 803 */ 804 #define MCPWM_DB0_DEB_MODE (BIT(8)) 805 #define MCPWM_DB0_DEB_MODE_M (MCPWM_DB0_DEB_MODE_V << MCPWM_DB0_DEB_MODE_S) 806 #define MCPWM_DB0_DEB_MODE_V 0x00000001U 807 #define MCPWM_DB0_DEB_MODE_S 8 808 /** MCPWM_DB0_A_OUTSWAP : R/W; bitpos: [9]; default: 0; 809 * S6 in table 810 */ 811 #define MCPWM_DB0_A_OUTSWAP (BIT(9)) 812 #define MCPWM_DB0_A_OUTSWAP_M (MCPWM_DB0_A_OUTSWAP_V << MCPWM_DB0_A_OUTSWAP_S) 813 #define MCPWM_DB0_A_OUTSWAP_V 0x00000001U 814 #define MCPWM_DB0_A_OUTSWAP_S 9 815 /** MCPWM_DB0_B_OUTSWAP : R/W; bitpos: [10]; default: 0; 816 * S7 in table 817 */ 818 #define MCPWM_DB0_B_OUTSWAP (BIT(10)) 819 #define MCPWM_DB0_B_OUTSWAP_M (MCPWM_DB0_B_OUTSWAP_V << MCPWM_DB0_B_OUTSWAP_S) 820 #define MCPWM_DB0_B_OUTSWAP_V 0x00000001U 821 #define MCPWM_DB0_B_OUTSWAP_S 10 822 /** MCPWM_DB0_RED_INSEL : R/W; bitpos: [11]; default: 0; 823 * S4 in table 824 */ 825 #define MCPWM_DB0_RED_INSEL (BIT(11)) 826 #define MCPWM_DB0_RED_INSEL_M (MCPWM_DB0_RED_INSEL_V << MCPWM_DB0_RED_INSEL_S) 827 #define MCPWM_DB0_RED_INSEL_V 0x00000001U 828 #define MCPWM_DB0_RED_INSEL_S 11 829 /** MCPWM_DB0_FED_INSEL : R/W; bitpos: [12]; default: 0; 830 * S5 in table 831 */ 832 #define MCPWM_DB0_FED_INSEL (BIT(12)) 833 #define MCPWM_DB0_FED_INSEL_M (MCPWM_DB0_FED_INSEL_V << MCPWM_DB0_FED_INSEL_S) 834 #define MCPWM_DB0_FED_INSEL_V 0x00000001U 835 #define MCPWM_DB0_FED_INSEL_S 12 836 /** MCPWM_DB0_RED_OUTINVERT : R/W; bitpos: [13]; default: 0; 837 * S2 in table 838 */ 839 #define MCPWM_DB0_RED_OUTINVERT (BIT(13)) 840 #define MCPWM_DB0_RED_OUTINVERT_M (MCPWM_DB0_RED_OUTINVERT_V << MCPWM_DB0_RED_OUTINVERT_S) 841 #define MCPWM_DB0_RED_OUTINVERT_V 0x00000001U 842 #define MCPWM_DB0_RED_OUTINVERT_S 13 843 /** MCPWM_DB0_FED_OUTINVERT : R/W; bitpos: [14]; default: 0; 844 * S3 in table 845 */ 846 #define MCPWM_DB0_FED_OUTINVERT (BIT(14)) 847 #define MCPWM_DB0_FED_OUTINVERT_M (MCPWM_DB0_FED_OUTINVERT_V << MCPWM_DB0_FED_OUTINVERT_S) 848 #define MCPWM_DB0_FED_OUTINVERT_V 0x00000001U 849 #define MCPWM_DB0_FED_OUTINVERT_S 14 850 /** MCPWM_DB0_A_OUTBYPASS : R/W; bitpos: [15]; default: 1; 851 * S1 in table 852 */ 853 #define MCPWM_DB0_A_OUTBYPASS (BIT(15)) 854 #define MCPWM_DB0_A_OUTBYPASS_M (MCPWM_DB0_A_OUTBYPASS_V << MCPWM_DB0_A_OUTBYPASS_S) 855 #define MCPWM_DB0_A_OUTBYPASS_V 0x00000001U 856 #define MCPWM_DB0_A_OUTBYPASS_S 15 857 /** MCPWM_DB0_B_OUTBYPASS : R/W; bitpos: [16]; default: 1; 858 * S0 in table 859 */ 860 #define MCPWM_DB0_B_OUTBYPASS (BIT(16)) 861 #define MCPWM_DB0_B_OUTBYPASS_M (MCPWM_DB0_B_OUTBYPASS_V << MCPWM_DB0_B_OUTBYPASS_S) 862 #define MCPWM_DB0_B_OUTBYPASS_V 0x00000001U 863 #define MCPWM_DB0_B_OUTBYPASS_S 16 864 /** MCPWM_DB0_CLK_SEL : R/W; bitpos: [17]; default: 0; 865 * Dead time generator 0 clock selection. 0: PWM_clk, 1: PT_clk 866 */ 867 #define MCPWM_DB0_CLK_SEL (BIT(17)) 868 #define MCPWM_DB0_CLK_SEL_M (MCPWM_DB0_CLK_SEL_V << MCPWM_DB0_CLK_SEL_S) 869 #define MCPWM_DB0_CLK_SEL_V 0x00000001U 870 #define MCPWM_DB0_CLK_SEL_S 17 871 872 /** MCPWM_DT0_FED_CFG_REG register 873 * Shadow register for falling edge delay (FED). 874 */ 875 #define MCPWM_DT0_FED_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x5c) 876 /** MCPWM_DB0_FED : R/W; bitpos: [15:0]; default: 0; 877 * Shadow register for FED 878 */ 879 #define MCPWM_DB0_FED 0x0000FFFFU 880 #define MCPWM_DB0_FED_M (MCPWM_DB0_FED_V << MCPWM_DB0_FED_S) 881 #define MCPWM_DB0_FED_V 0x0000FFFFU 882 #define MCPWM_DB0_FED_S 0 883 884 /** MCPWM_DT0_RED_CFG_REG register 885 * Shadow register for rising edge delay (RED). 886 */ 887 #define MCPWM_DT0_RED_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x60) 888 /** MCPWM_DB0_RED : R/W; bitpos: [15:0]; default: 0; 889 * Shadow register for RED 890 */ 891 #define MCPWM_DB0_RED 0x0000FFFFU 892 #define MCPWM_DB0_RED_M (MCPWM_DB0_RED_V << MCPWM_DB0_RED_S) 893 #define MCPWM_DB0_RED_V 0x0000FFFFU 894 #define MCPWM_DB0_RED_S 0 895 896 /** MCPWM_CARRIER0_CFG_REG register 897 * Carrier enable and configuratoin 898 */ 899 #define MCPWM_CARRIER0_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x64) 900 /** MCPWM_CHOPPER0_EN : R/W; bitpos: [0]; default: 0; 901 * When set, carrier0 function is enabled. When cleared, carrier0 is bypassed 902 */ 903 #define MCPWM_CHOPPER0_EN (BIT(0)) 904 #define MCPWM_CHOPPER0_EN_M (MCPWM_CHOPPER0_EN_V << MCPWM_CHOPPER0_EN_S) 905 #define MCPWM_CHOPPER0_EN_V 0x00000001U 906 #define MCPWM_CHOPPER0_EN_S 0 907 /** MCPWM_CHOPPER0_PRESCALE : R/W; bitpos: [4:1]; default: 0; 908 * PWM carrier0 clock (PC_clk) prescale value. Period of PC_clk = period of PWM_clk * 909 * (PWM_CARRIER0_PRESCALE + 1) 910 */ 911 #define MCPWM_CHOPPER0_PRESCALE 0x0000000FU 912 #define MCPWM_CHOPPER0_PRESCALE_M (MCPWM_CHOPPER0_PRESCALE_V << MCPWM_CHOPPER0_PRESCALE_S) 913 #define MCPWM_CHOPPER0_PRESCALE_V 0x0000000FU 914 #define MCPWM_CHOPPER0_PRESCALE_S 1 915 /** MCPWM_CHOPPER0_DUTY : R/W; bitpos: [7:5]; default: 0; 916 * carrier duty selection. Duty = PWM_CARRIER0_DUTY / 8 917 */ 918 #define MCPWM_CHOPPER0_DUTY 0x00000007U 919 #define MCPWM_CHOPPER0_DUTY_M (MCPWM_CHOPPER0_DUTY_V << MCPWM_CHOPPER0_DUTY_S) 920 #define MCPWM_CHOPPER0_DUTY_V 0x00000007U 921 #define MCPWM_CHOPPER0_DUTY_S 5 922 /** MCPWM_CHOPPER0_OSHTWTH : R/W; bitpos: [11:8]; default: 0; 923 * width of the first pulse in number of periods of the carrier 924 */ 925 #define MCPWM_CHOPPER0_OSHTWTH 0x0000000FU 926 #define MCPWM_CHOPPER0_OSHTWTH_M (MCPWM_CHOPPER0_OSHTWTH_V << MCPWM_CHOPPER0_OSHTWTH_S) 927 #define MCPWM_CHOPPER0_OSHTWTH_V 0x0000000FU 928 #define MCPWM_CHOPPER0_OSHTWTH_S 8 929 /** MCPWM_CHOPPER0_OUT_INVERT : R/W; bitpos: [12]; default: 0; 930 * when set, invert the output of PWM0A and PWM0B for this submodule 931 */ 932 #define MCPWM_CHOPPER0_OUT_INVERT (BIT(12)) 933 #define MCPWM_CHOPPER0_OUT_INVERT_M (MCPWM_CHOPPER0_OUT_INVERT_V << MCPWM_CHOPPER0_OUT_INVERT_S) 934 #define MCPWM_CHOPPER0_OUT_INVERT_V 0x00000001U 935 #define MCPWM_CHOPPER0_OUT_INVERT_S 12 936 /** MCPWM_CHOPPER0_IN_INVERT : R/W; bitpos: [13]; default: 0; 937 * when set, invert the input of PWM0A and PWM0B for this submodule 938 */ 939 #define MCPWM_CHOPPER0_IN_INVERT (BIT(13)) 940 #define MCPWM_CHOPPER0_IN_INVERT_M (MCPWM_CHOPPER0_IN_INVERT_V << MCPWM_CHOPPER0_IN_INVERT_S) 941 #define MCPWM_CHOPPER0_IN_INVERT_V 0x00000001U 942 #define MCPWM_CHOPPER0_IN_INVERT_S 13 943 944 /** MCPWM_FH0_CFG0_REG register 945 * Actions on PWM0A and PWM0B trip events 946 */ 947 #define MCPWM_FH0_CFG0_REG(i) (REG_MCPWM_BASE(i) + 0x68) 948 /** MCPWM_TZ0_SW_CBC : R/W; bitpos: [0]; default: 0; 949 * Enable register for software force cycle-by-cycle mode action. 0: disable, 1: enable 950 */ 951 #define MCPWM_TZ0_SW_CBC (BIT(0)) 952 #define MCPWM_TZ0_SW_CBC_M (MCPWM_TZ0_SW_CBC_V << MCPWM_TZ0_SW_CBC_S) 953 #define MCPWM_TZ0_SW_CBC_V 0x00000001U 954 #define MCPWM_TZ0_SW_CBC_S 0 955 /** MCPWM_TZ0_F2_CBC : R/W; bitpos: [1]; default: 0; 956 * event_f2 will trigger cycle-by-cycle mode action. 0: disable, 1: enable 957 */ 958 #define MCPWM_TZ0_F2_CBC (BIT(1)) 959 #define MCPWM_TZ0_F2_CBC_M (MCPWM_TZ0_F2_CBC_V << MCPWM_TZ0_F2_CBC_S) 960 #define MCPWM_TZ0_F2_CBC_V 0x00000001U 961 #define MCPWM_TZ0_F2_CBC_S 1 962 /** MCPWM_TZ0_F1_CBC : R/W; bitpos: [2]; default: 0; 963 * event_f1 will trigger cycle-by-cycle mode action. 0: disable, 1: enable 964 */ 965 #define MCPWM_TZ0_F1_CBC (BIT(2)) 966 #define MCPWM_TZ0_F1_CBC_M (MCPWM_TZ0_F1_CBC_V << MCPWM_TZ0_F1_CBC_S) 967 #define MCPWM_TZ0_F1_CBC_V 0x00000001U 968 #define MCPWM_TZ0_F1_CBC_S 2 969 /** MCPWM_TZ0_F0_CBC : R/W; bitpos: [3]; default: 0; 970 * event_f0 will trigger cycle-by-cycle mode action. 0: disable, 1: enable 971 */ 972 #define MCPWM_TZ0_F0_CBC (BIT(3)) 973 #define MCPWM_TZ0_F0_CBC_M (MCPWM_TZ0_F0_CBC_V << MCPWM_TZ0_F0_CBC_S) 974 #define MCPWM_TZ0_F0_CBC_V 0x00000001U 975 #define MCPWM_TZ0_F0_CBC_S 3 976 /** MCPWM_TZ0_SW_OST : R/W; bitpos: [4]; default: 0; 977 * Enable register for software force one-shot mode action. 0: disable, 1: enable 978 */ 979 #define MCPWM_TZ0_SW_OST (BIT(4)) 980 #define MCPWM_TZ0_SW_OST_M (MCPWM_TZ0_SW_OST_V << MCPWM_TZ0_SW_OST_S) 981 #define MCPWM_TZ0_SW_OST_V 0x00000001U 982 #define MCPWM_TZ0_SW_OST_S 4 983 /** MCPWM_TZ0_F2_OST : R/W; bitpos: [5]; default: 0; 984 * event_f2 will trigger one-shot mode action. 0: disable, 1: enable 985 */ 986 #define MCPWM_TZ0_F2_OST (BIT(5)) 987 #define MCPWM_TZ0_F2_OST_M (MCPWM_TZ0_F2_OST_V << MCPWM_TZ0_F2_OST_S) 988 #define MCPWM_TZ0_F2_OST_V 0x00000001U 989 #define MCPWM_TZ0_F2_OST_S 5 990 /** MCPWM_TZ0_F1_OST : R/W; bitpos: [6]; default: 0; 991 * event_f1 will trigger one-shot mode action. 0: disable, 1: enable 992 */ 993 #define MCPWM_TZ0_F1_OST (BIT(6)) 994 #define MCPWM_TZ0_F1_OST_M (MCPWM_TZ0_F1_OST_V << MCPWM_TZ0_F1_OST_S) 995 #define MCPWM_TZ0_F1_OST_V 0x00000001U 996 #define MCPWM_TZ0_F1_OST_S 6 997 /** MCPWM_TZ0_F0_OST : R/W; bitpos: [7]; default: 0; 998 * event_f0 will trigger one-shot mode action. 0: disable, 1: enable 999 */ 1000 #define MCPWM_TZ0_F0_OST (BIT(7)) 1001 #define MCPWM_TZ0_F0_OST_M (MCPWM_TZ0_F0_OST_V << MCPWM_TZ0_F0_OST_S) 1002 #define MCPWM_TZ0_F0_OST_V 0x00000001U 1003 #define MCPWM_TZ0_F0_OST_S 7 1004 /** MCPWM_TZ0_A_CBC_D : R/W; bitpos: [9:8]; default: 0; 1005 * Cycle-by-cycle mode action on PWM0A when fault event occurs and timer is 1006 * decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle 1007 */ 1008 #define MCPWM_TZ0_A_CBC_D 0x00000003U 1009 #define MCPWM_TZ0_A_CBC_D_M (MCPWM_TZ0_A_CBC_D_V << MCPWM_TZ0_A_CBC_D_S) 1010 #define MCPWM_TZ0_A_CBC_D_V 0x00000003U 1011 #define MCPWM_TZ0_A_CBC_D_S 8 1012 /** MCPWM_TZ0_A_CBC_U : R/W; bitpos: [11:10]; default: 0; 1013 * Cycle-by-cycle mode action on PWM0A when fault event occurs and timer is 1014 * increasing. 0: do nothing, 1: force low, 2: force high, 3: toggle 1015 */ 1016 #define MCPWM_TZ0_A_CBC_U 0x00000003U 1017 #define MCPWM_TZ0_A_CBC_U_M (MCPWM_TZ0_A_CBC_U_V << MCPWM_TZ0_A_CBC_U_S) 1018 #define MCPWM_TZ0_A_CBC_U_V 0x00000003U 1019 #define MCPWM_TZ0_A_CBC_U_S 10 1020 /** MCPWM_TZ0_A_OST_D : R/W; bitpos: [13:12]; default: 0; 1021 * One-shot mode action on PWM0A when fault event occurs and timer is decreasing. 0: 1022 * do nothing, 1: force low, 2: force high, 3: toggle 1023 */ 1024 #define MCPWM_TZ0_A_OST_D 0x00000003U 1025 #define MCPWM_TZ0_A_OST_D_M (MCPWM_TZ0_A_OST_D_V << MCPWM_TZ0_A_OST_D_S) 1026 #define MCPWM_TZ0_A_OST_D_V 0x00000003U 1027 #define MCPWM_TZ0_A_OST_D_S 12 1028 /** MCPWM_TZ0_A_OST_U : R/W; bitpos: [15:14]; default: 0; 1029 * One-shot mode action on PWM0A when fault event occurs and timer is increasing. 0: 1030 * do nothing, 1: force low, 2: force high, 3: toggle 1031 */ 1032 #define MCPWM_TZ0_A_OST_U 0x00000003U 1033 #define MCPWM_TZ0_A_OST_U_M (MCPWM_TZ0_A_OST_U_V << MCPWM_TZ0_A_OST_U_S) 1034 #define MCPWM_TZ0_A_OST_U_V 0x00000003U 1035 #define MCPWM_TZ0_A_OST_U_S 14 1036 /** MCPWM_TZ0_B_CBC_D : R/W; bitpos: [17:16]; default: 0; 1037 * Cycle-by-cycle mode action on PWM0B when fault event occurs and timer is 1038 * decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle 1039 */ 1040 #define MCPWM_TZ0_B_CBC_D 0x00000003U 1041 #define MCPWM_TZ0_B_CBC_D_M (MCPWM_TZ0_B_CBC_D_V << MCPWM_TZ0_B_CBC_D_S) 1042 #define MCPWM_TZ0_B_CBC_D_V 0x00000003U 1043 #define MCPWM_TZ0_B_CBC_D_S 16 1044 /** MCPWM_TZ0_B_CBC_U : R/W; bitpos: [19:18]; default: 0; 1045 * Cycle-by-cycle mode action on PWM0B when fault event occurs and timer is 1046 * increasing. 0: do nothing,1: force low, 2: force high, 3: toggle 1047 */ 1048 #define MCPWM_TZ0_B_CBC_U 0x00000003U 1049 #define MCPWM_TZ0_B_CBC_U_M (MCPWM_TZ0_B_CBC_U_V << MCPWM_TZ0_B_CBC_U_S) 1050 #define MCPWM_TZ0_B_CBC_U_V 0x00000003U 1051 #define MCPWM_TZ0_B_CBC_U_S 18 1052 /** MCPWM_TZ0_B_OST_D : R/W; bitpos: [21:20]; default: 0; 1053 * One-shot mode action on PWM0B when fault event occurs and timer is decreasing. 0: 1054 * do nothing, 1: force low, 2: force high, 3: toggle 1055 */ 1056 #define MCPWM_TZ0_B_OST_D 0x00000003U 1057 #define MCPWM_TZ0_B_OST_D_M (MCPWM_TZ0_B_OST_D_V << MCPWM_TZ0_B_OST_D_S) 1058 #define MCPWM_TZ0_B_OST_D_V 0x00000003U 1059 #define MCPWM_TZ0_B_OST_D_S 20 1060 /** MCPWM_TZ0_B_OST_U : R/W; bitpos: [23:22]; default: 0; 1061 * One-shot mode action on PWM0B when fault event occurs and timer is increasing. 0: 1062 * do nothing, 1: force low, 2: force high, 3: toggle 1063 */ 1064 #define MCPWM_TZ0_B_OST_U 0x00000003U 1065 #define MCPWM_TZ0_B_OST_U_M (MCPWM_TZ0_B_OST_U_V << MCPWM_TZ0_B_OST_U_S) 1066 #define MCPWM_TZ0_B_OST_U_V 0x00000003U 1067 #define MCPWM_TZ0_B_OST_U_S 22 1068 1069 /** MCPWM_FH0_CFG1_REG register 1070 * Software triggers for fault handler actions 1071 */ 1072 #define MCPWM_FH0_CFG1_REG(i) (REG_MCPWM_BASE(i) + 0x6c) 1073 /** MCPWM_TZ0_CLR_OST : R/W; bitpos: [0]; default: 0; 1074 * a rising edge will clear on going one-shot mode action 1075 */ 1076 #define MCPWM_TZ0_CLR_OST (BIT(0)) 1077 #define MCPWM_TZ0_CLR_OST_M (MCPWM_TZ0_CLR_OST_V << MCPWM_TZ0_CLR_OST_S) 1078 #define MCPWM_TZ0_CLR_OST_V 0x00000001U 1079 #define MCPWM_TZ0_CLR_OST_S 0 1080 /** MCPWM_TZ0_CBCPULSE : R/W; bitpos: [2:1]; default: 0; 1081 * cycle-by-cycle mode action refresh moment selection. When bit0 is set to 1: TEZ, 1082 * when bit1 is set to 1:TEP 1083 */ 1084 #define MCPWM_TZ0_CBCPULSE 0x00000003U 1085 #define MCPWM_TZ0_CBCPULSE_M (MCPWM_TZ0_CBCPULSE_V << MCPWM_TZ0_CBCPULSE_S) 1086 #define MCPWM_TZ0_CBCPULSE_V 0x00000003U 1087 #define MCPWM_TZ0_CBCPULSE_S 1 1088 /** MCPWM_TZ0_FORCE_CBC : R/W; bitpos: [3]; default: 0; 1089 * a toggle trigger a cycle-by-cycle mode action 1090 */ 1091 #define MCPWM_TZ0_FORCE_CBC (BIT(3)) 1092 #define MCPWM_TZ0_FORCE_CBC_M (MCPWM_TZ0_FORCE_CBC_V << MCPWM_TZ0_FORCE_CBC_S) 1093 #define MCPWM_TZ0_FORCE_CBC_V 0x00000001U 1094 #define MCPWM_TZ0_FORCE_CBC_S 3 1095 /** MCPWM_TZ0_FORCE_OST : R/W; bitpos: [4]; default: 0; 1096 * a toggle (software negate its value) triggers a one-shot mode action 1097 */ 1098 #define MCPWM_TZ0_FORCE_OST (BIT(4)) 1099 #define MCPWM_TZ0_FORCE_OST_M (MCPWM_TZ0_FORCE_OST_V << MCPWM_TZ0_FORCE_OST_S) 1100 #define MCPWM_TZ0_FORCE_OST_V 0x00000001U 1101 #define MCPWM_TZ0_FORCE_OST_S 4 1102 1103 /** MCPWM_FH0_STATUS_REG register 1104 * Status of fault events. 1105 */ 1106 #define MCPWM_FH0_STATUS_REG(i) (REG_MCPWM_BASE(i) + 0x70) 1107 /** MCPWM_TZ0_CBC_ON : RO; bitpos: [0]; default: 0; 1108 * Set and reset by hardware. If set, a cycle-by-cycle mode action is on going 1109 */ 1110 #define MCPWM_TZ0_CBC_ON (BIT(0)) 1111 #define MCPWM_TZ0_CBC_ON_M (MCPWM_TZ0_CBC_ON_V << MCPWM_TZ0_CBC_ON_S) 1112 #define MCPWM_TZ0_CBC_ON_V 0x00000001U 1113 #define MCPWM_TZ0_CBC_ON_S 0 1114 /** MCPWM_TZ0_OST_ON : RO; bitpos: [1]; default: 0; 1115 * Set and reset by hardware. If set, an one-shot mode action is on going 1116 */ 1117 #define MCPWM_TZ0_OST_ON (BIT(1)) 1118 #define MCPWM_TZ0_OST_ON_M (MCPWM_TZ0_OST_ON_V << MCPWM_TZ0_OST_ON_S) 1119 #define MCPWM_TZ0_OST_ON_V 0x00000001U 1120 #define MCPWM_TZ0_OST_ON_S 1 1121 1122 /** MCPWM_GEN1_STMP_CFG_REG register 1123 * Transfer status and update method for time stamp registers A and B 1124 */ 1125 #define MCPWM_GEN1_STMP_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x74) 1126 /** MCPWM_CMPR1_A_UPMETHOD : R/W; bitpos: [3:0]; default: 0; 1127 * Update method for PWM generator 1 time stamp A's active register. When all bits are 1128 * set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1: TEP,when 1129 * bit2 is set to 1: sync, when bit3 is set to 1: disable the update. 1130 */ 1131 #define MCPWM_CMPR1_A_UPMETHOD 0x0000000FU 1132 #define MCPWM_CMPR1_A_UPMETHOD_M (MCPWM_CMPR1_A_UPMETHOD_V << MCPWM_CMPR1_A_UPMETHOD_S) 1133 #define MCPWM_CMPR1_A_UPMETHOD_V 0x0000000FU 1134 #define MCPWM_CMPR1_A_UPMETHOD_S 0 1135 /** MCPWM_CMPR1_B_UPMETHOD : R/W; bitpos: [7:4]; default: 0; 1136 * Update method for PWM generator 1 time stamp B's active register. When all bits are 1137 * set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1: TEP,when 1138 * bit2 is set to 1: sync, when bit3 is set to 1: disable the update. 1139 */ 1140 #define MCPWM_CMPR1_B_UPMETHOD 0x0000000FU 1141 #define MCPWM_CMPR1_B_UPMETHOD_M (MCPWM_CMPR1_B_UPMETHOD_V << MCPWM_CMPR1_B_UPMETHOD_S) 1142 #define MCPWM_CMPR1_B_UPMETHOD_V 0x0000000FU 1143 #define MCPWM_CMPR1_B_UPMETHOD_S 4 1144 /** MCPWM_CMPR1_A_SHDW_FULL : R/W/WTC/SC; bitpos: [8]; default: 0; 1145 * Set and reset by hardware. If set, PWM generator 1 time stamp A's shadow reg is 1146 * filled and waiting to be transferred to A's active reg. If cleared, A's active reg 1147 * has been updated with shadow register latest value 1148 */ 1149 #define MCPWM_CMPR1_A_SHDW_FULL (BIT(8)) 1150 #define MCPWM_CMPR1_A_SHDW_FULL_M (MCPWM_CMPR1_A_SHDW_FULL_V << MCPWM_CMPR1_A_SHDW_FULL_S) 1151 #define MCPWM_CMPR1_A_SHDW_FULL_V 0x00000001U 1152 #define MCPWM_CMPR1_A_SHDW_FULL_S 8 1153 /** MCPWM_CMPR1_B_SHDW_FULL : R/W/WTC/SC; bitpos: [9]; default: 0; 1154 * Set and reset by hardware. If set, PWM generator 1 time stamp B's shadow reg is 1155 * filled and waiting to be transferred to B's active reg. If cleared, B's active reg 1156 * has been updated with shadow register latest value 1157 */ 1158 #define MCPWM_CMPR1_B_SHDW_FULL (BIT(9)) 1159 #define MCPWM_CMPR1_B_SHDW_FULL_M (MCPWM_CMPR1_B_SHDW_FULL_V << MCPWM_CMPR1_B_SHDW_FULL_S) 1160 #define MCPWM_CMPR1_B_SHDW_FULL_V 0x00000001U 1161 #define MCPWM_CMPR1_B_SHDW_FULL_S 9 1162 1163 /** MCPWM_GEN1_TSTMP_A_REG register 1164 * Shadow register for register A. 1165 */ 1166 #define MCPWM_GEN1_TSTMP_A_REG(i) (REG_MCPWM_BASE(i) + 0x78) 1167 /** MCPWM_CMPR1_A : R/W; bitpos: [15:0]; default: 0; 1168 * PWM generator 1 time stamp A's shadow register 1169 */ 1170 #define MCPWM_CMPR1_A 0x0000FFFFU 1171 #define MCPWM_CMPR1_A_M (MCPWM_CMPR1_A_V << MCPWM_CMPR1_A_S) 1172 #define MCPWM_CMPR1_A_V 0x0000FFFFU 1173 #define MCPWM_CMPR1_A_S 0 1174 1175 /** MCPWM_GEN1_TSTMP_B_REG register 1176 * Shadow register for register B. 1177 */ 1178 #define MCPWM_GEN1_TSTMP_B_REG(i) (REG_MCPWM_BASE(i) + 0x7c) 1179 /** MCPWM_CMPR1_B : R/W; bitpos: [15:0]; default: 0; 1180 * PWM generator 1 time stamp B's shadow register 1181 */ 1182 #define MCPWM_CMPR1_B 0x0000FFFFU 1183 #define MCPWM_CMPR1_B_M (MCPWM_CMPR1_B_V << MCPWM_CMPR1_B_S) 1184 #define MCPWM_CMPR1_B_V 0x0000FFFFU 1185 #define MCPWM_CMPR1_B_S 0 1186 1187 /** MCPWM_GEN1_CFG0_REG register 1188 * Fault event T0 and T1 handling 1189 */ 1190 #define MCPWM_GEN1_CFG0_REG(i) (REG_MCPWM_BASE(i) + 0x80) 1191 /** MCPWM_GEN1_CFG_UPMETHOD : R/W; bitpos: [3:0]; default: 0; 1192 * Update method for PWM generator 1's active register of configuration. When all bits 1193 * are set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1194 * 1:sync;when bit3 is set to 1:disable the update. 1195 */ 1196 #define MCPWM_GEN1_CFG_UPMETHOD 0x0000000FU 1197 #define MCPWM_GEN1_CFG_UPMETHOD_M (MCPWM_GEN1_CFG_UPMETHOD_V << MCPWM_GEN1_CFG_UPMETHOD_S) 1198 #define MCPWM_GEN1_CFG_UPMETHOD_V 0x0000000FU 1199 #define MCPWM_GEN1_CFG_UPMETHOD_S 0 1200 /** MCPWM_GEN1_T0_SEL : R/W; bitpos: [6:4]; default: 0; 1201 * Source selection for PWM generator 1 event_t0, take effect immediately, 0: 1202 * fault_event0, 1: fault_event1, 2: fault_event2, 3: sync_taken, 4: none 1203 */ 1204 #define MCPWM_GEN1_T0_SEL 0x00000007U 1205 #define MCPWM_GEN1_T0_SEL_M (MCPWM_GEN1_T0_SEL_V << MCPWM_GEN1_T0_SEL_S) 1206 #define MCPWM_GEN1_T0_SEL_V 0x00000007U 1207 #define MCPWM_GEN1_T0_SEL_S 4 1208 /** MCPWM_GEN1_T1_SEL : R/W; bitpos: [9:7]; default: 0; 1209 * Source selection for PWM generator 1 event_t1, take effect immediately, 0: 1210 * fault_event0, 1: fault_event1, 2: fault_event2, 3: sync_taken, 4: none 1211 */ 1212 #define MCPWM_GEN1_T1_SEL 0x00000007U 1213 #define MCPWM_GEN1_T1_SEL_M (MCPWM_GEN1_T1_SEL_V << MCPWM_GEN1_T1_SEL_S) 1214 #define MCPWM_GEN1_T1_SEL_V 0x00000007U 1215 #define MCPWM_GEN1_T1_SEL_S 7 1216 1217 /** MCPWM_GEN1_FORCE_REG register 1218 * Permissives to force PWM1A and PWM1B outputs by software 1219 */ 1220 #define MCPWM_GEN1_FORCE_REG(i) (REG_MCPWM_BASE(i) + 0x84) 1221 /** MCPWM_GEN1_CNTUFORCE_UPMETHOD : R/W; bitpos: [5:0]; default: 32; 1222 * Updating method for continuous software force of PWM generator 1. When all bits are 1223 * set to 0: immediately, when bit0 is set to 1: TEZ,,when bit1 is set to 1: TEP, when 1224 * bit2 is set to 1: TEA, when bit3 is set to 1: TEB, when bit4 is set to 1: sync, 1225 * when bit5 is set to 1: disable update. (TEA/B here and below means an event 1226 * generated when the timer's value equals to that of register A/B.) 1227 */ 1228 #define MCPWM_GEN1_CNTUFORCE_UPMETHOD 0x0000003FU 1229 #define MCPWM_GEN1_CNTUFORCE_UPMETHOD_M (MCPWM_GEN1_CNTUFORCE_UPMETHOD_V << MCPWM_GEN1_CNTUFORCE_UPMETHOD_S) 1230 #define MCPWM_GEN1_CNTUFORCE_UPMETHOD_V 0x0000003FU 1231 #define MCPWM_GEN1_CNTUFORCE_UPMETHOD_S 0 1232 /** MCPWM_GEN1_A_CNTUFORCE_MODE : R/W; bitpos: [7:6]; default: 0; 1233 * Continuous software force mode for PWM1A. 0: disabled, 1: low, 2: high, 3: disabled 1234 */ 1235 #define MCPWM_GEN1_A_CNTUFORCE_MODE 0x00000003U 1236 #define MCPWM_GEN1_A_CNTUFORCE_MODE_M (MCPWM_GEN1_A_CNTUFORCE_MODE_V << MCPWM_GEN1_A_CNTUFORCE_MODE_S) 1237 #define MCPWM_GEN1_A_CNTUFORCE_MODE_V 0x00000003U 1238 #define MCPWM_GEN1_A_CNTUFORCE_MODE_S 6 1239 /** MCPWM_GEN1_B_CNTUFORCE_MODE : R/W; bitpos: [9:8]; default: 0; 1240 * Continuous software force mode for PWM1B. 0: disabled, 1: low, 2: high, 3: disabled 1241 */ 1242 #define MCPWM_GEN1_B_CNTUFORCE_MODE 0x00000003U 1243 #define MCPWM_GEN1_B_CNTUFORCE_MODE_M (MCPWM_GEN1_B_CNTUFORCE_MODE_V << MCPWM_GEN1_B_CNTUFORCE_MODE_S) 1244 #define MCPWM_GEN1_B_CNTUFORCE_MODE_V 0x00000003U 1245 #define MCPWM_GEN1_B_CNTUFORCE_MODE_S 8 1246 /** MCPWM_GEN1_A_NCIFORCE : R/W; bitpos: [10]; default: 0; 1247 * Trigger of non-continuous immediate software-force event for PWM1A, a toggle will 1248 * trigger a force event. 1249 */ 1250 #define MCPWM_GEN1_A_NCIFORCE (BIT(10)) 1251 #define MCPWM_GEN1_A_NCIFORCE_M (MCPWM_GEN1_A_NCIFORCE_V << MCPWM_GEN1_A_NCIFORCE_S) 1252 #define MCPWM_GEN1_A_NCIFORCE_V 0x00000001U 1253 #define MCPWM_GEN1_A_NCIFORCE_S 10 1254 /** MCPWM_GEN1_A_NCIFORCE_MODE : R/W; bitpos: [12:11]; default: 0; 1255 * non-continuous immediate software force mode for PWM1A, 0: disabled, 1: low, 2: 1256 * high, 3: disabled 1257 */ 1258 #define MCPWM_GEN1_A_NCIFORCE_MODE 0x00000003U 1259 #define MCPWM_GEN1_A_NCIFORCE_MODE_M (MCPWM_GEN1_A_NCIFORCE_MODE_V << MCPWM_GEN1_A_NCIFORCE_MODE_S) 1260 #define MCPWM_GEN1_A_NCIFORCE_MODE_V 0x00000003U 1261 #define MCPWM_GEN1_A_NCIFORCE_MODE_S 11 1262 /** MCPWM_GEN1_B_NCIFORCE : R/W; bitpos: [13]; default: 0; 1263 * Trigger of non-continuous immediate software-force event for PWM1B, a toggle will 1264 * trigger a force event. 1265 */ 1266 #define MCPWM_GEN1_B_NCIFORCE (BIT(13)) 1267 #define MCPWM_GEN1_B_NCIFORCE_M (MCPWM_GEN1_B_NCIFORCE_V << MCPWM_GEN1_B_NCIFORCE_S) 1268 #define MCPWM_GEN1_B_NCIFORCE_V 0x00000001U 1269 #define MCPWM_GEN1_B_NCIFORCE_S 13 1270 /** MCPWM_GEN1_B_NCIFORCE_MODE : R/W; bitpos: [15:14]; default: 0; 1271 * non-continuous immediate software force mode for PWM1B, 0: disabled, 1: low, 2: 1272 * high, 3: disabled 1273 */ 1274 #define MCPWM_GEN1_B_NCIFORCE_MODE 0x00000003U 1275 #define MCPWM_GEN1_B_NCIFORCE_MODE_M (MCPWM_GEN1_B_NCIFORCE_MODE_V << MCPWM_GEN1_B_NCIFORCE_MODE_S) 1276 #define MCPWM_GEN1_B_NCIFORCE_MODE_V 0x00000003U 1277 #define MCPWM_GEN1_B_NCIFORCE_MODE_S 14 1278 1279 /** MCPWM_GEN1_A_REG register 1280 * Actions triggered by events on PWM1A 1281 */ 1282 #define MCPWM_GEN1_A_REG(i) (REG_MCPWM_BASE(i) + 0x88) 1283 /** MCPWM_GEN1_A_UTEZ : R/W; bitpos: [1:0]; default: 0; 1284 * Action on PWM1A triggered by event TEZ when timer increasing 1285 */ 1286 #define MCPWM_GEN1_A_UTEZ 0x00000003U 1287 #define MCPWM_GEN1_A_UTEZ_M (MCPWM_GEN1_A_UTEZ_V << MCPWM_GEN1_A_UTEZ_S) 1288 #define MCPWM_GEN1_A_UTEZ_V 0x00000003U 1289 #define MCPWM_GEN1_A_UTEZ_S 0 1290 /** MCPWM_GEN1_A_UTEP : R/W; bitpos: [3:2]; default: 0; 1291 * Action on PWM1A triggered by event TEP when timer increasing 1292 */ 1293 #define MCPWM_GEN1_A_UTEP 0x00000003U 1294 #define MCPWM_GEN1_A_UTEP_M (MCPWM_GEN1_A_UTEP_V << MCPWM_GEN1_A_UTEP_S) 1295 #define MCPWM_GEN1_A_UTEP_V 0x00000003U 1296 #define MCPWM_GEN1_A_UTEP_S 2 1297 /** MCPWM_GEN1_A_UTEA : R/W; bitpos: [5:4]; default: 0; 1298 * Action on PWM1A triggered by event TEA when timer increasing 1299 */ 1300 #define MCPWM_GEN1_A_UTEA 0x00000003U 1301 #define MCPWM_GEN1_A_UTEA_M (MCPWM_GEN1_A_UTEA_V << MCPWM_GEN1_A_UTEA_S) 1302 #define MCPWM_GEN1_A_UTEA_V 0x00000003U 1303 #define MCPWM_GEN1_A_UTEA_S 4 1304 /** MCPWM_GEN1_A_UTEB : R/W; bitpos: [7:6]; default: 0; 1305 * Action on PWM1A triggered by event TEB when timer increasing 1306 */ 1307 #define MCPWM_GEN1_A_UTEB 0x00000003U 1308 #define MCPWM_GEN1_A_UTEB_M (MCPWM_GEN1_A_UTEB_V << MCPWM_GEN1_A_UTEB_S) 1309 #define MCPWM_GEN1_A_UTEB_V 0x00000003U 1310 #define MCPWM_GEN1_A_UTEB_S 6 1311 /** MCPWM_GEN1_A_UT0 : R/W; bitpos: [9:8]; default: 0; 1312 * Action on PWM1A triggered by event_t0 when timer increasing 1313 */ 1314 #define MCPWM_GEN1_A_UT0 0x00000003U 1315 #define MCPWM_GEN1_A_UT0_M (MCPWM_GEN1_A_UT0_V << MCPWM_GEN1_A_UT0_S) 1316 #define MCPWM_GEN1_A_UT0_V 0x00000003U 1317 #define MCPWM_GEN1_A_UT0_S 8 1318 /** MCPWM_GEN1_A_UT1 : R/W; bitpos: [11:10]; default: 0; 1319 * Action on PWM1A triggered by event_t1 when timer increasing 1320 */ 1321 #define MCPWM_GEN1_A_UT1 0x00000003U 1322 #define MCPWM_GEN1_A_UT1_M (MCPWM_GEN1_A_UT1_V << MCPWM_GEN1_A_UT1_S) 1323 #define MCPWM_GEN1_A_UT1_V 0x00000003U 1324 #define MCPWM_GEN1_A_UT1_S 10 1325 /** MCPWM_GEN1_A_DTEZ : R/W; bitpos: [13:12]; default: 0; 1326 * Action on PWM1A triggered by event TEZ when timer decreasing 1327 */ 1328 #define MCPWM_GEN1_A_DTEZ 0x00000003U 1329 #define MCPWM_GEN1_A_DTEZ_M (MCPWM_GEN1_A_DTEZ_V << MCPWM_GEN1_A_DTEZ_S) 1330 #define MCPWM_GEN1_A_DTEZ_V 0x00000003U 1331 #define MCPWM_GEN1_A_DTEZ_S 12 1332 /** MCPWM_GEN1_A_DTEP : R/W; bitpos: [15:14]; default: 0; 1333 * Action on PWM1A triggered by event TEP when timer decreasing 1334 */ 1335 #define MCPWM_GEN1_A_DTEP 0x00000003U 1336 #define MCPWM_GEN1_A_DTEP_M (MCPWM_GEN1_A_DTEP_V << MCPWM_GEN1_A_DTEP_S) 1337 #define MCPWM_GEN1_A_DTEP_V 0x00000003U 1338 #define MCPWM_GEN1_A_DTEP_S 14 1339 /** MCPWM_GEN1_A_DTEA : R/W; bitpos: [17:16]; default: 0; 1340 * Action on PWM1A triggered by event TEA when timer decreasing 1341 */ 1342 #define MCPWM_GEN1_A_DTEA 0x00000003U 1343 #define MCPWM_GEN1_A_DTEA_M (MCPWM_GEN1_A_DTEA_V << MCPWM_GEN1_A_DTEA_S) 1344 #define MCPWM_GEN1_A_DTEA_V 0x00000003U 1345 #define MCPWM_GEN1_A_DTEA_S 16 1346 /** MCPWM_GEN1_A_DTEB : R/W; bitpos: [19:18]; default: 0; 1347 * Action on PWM1A triggered by event TEB when timer decreasing 1348 */ 1349 #define MCPWM_GEN1_A_DTEB 0x00000003U 1350 #define MCPWM_GEN1_A_DTEB_M (MCPWM_GEN1_A_DTEB_V << MCPWM_GEN1_A_DTEB_S) 1351 #define MCPWM_GEN1_A_DTEB_V 0x00000003U 1352 #define MCPWM_GEN1_A_DTEB_S 18 1353 /** MCPWM_GEN1_A_DT0 : R/W; bitpos: [21:20]; default: 0; 1354 * Action on PWM1A triggered by event_t0 when timer decreasing 1355 */ 1356 #define MCPWM_GEN1_A_DT0 0x00000003U 1357 #define MCPWM_GEN1_A_DT0_M (MCPWM_GEN1_A_DT0_V << MCPWM_GEN1_A_DT0_S) 1358 #define MCPWM_GEN1_A_DT0_V 0x00000003U 1359 #define MCPWM_GEN1_A_DT0_S 20 1360 /** MCPWM_GEN1_A_DT1 : R/W; bitpos: [23:22]; default: 0; 1361 * Action on PWM1A triggered by event_t1 when timer decreasing. 0: no change, 1: low, 1362 * 2: high, 3: toggle 1363 */ 1364 #define MCPWM_GEN1_A_DT1 0x00000003U 1365 #define MCPWM_GEN1_A_DT1_M (MCPWM_GEN1_A_DT1_V << MCPWM_GEN1_A_DT1_S) 1366 #define MCPWM_GEN1_A_DT1_V 0x00000003U 1367 #define MCPWM_GEN1_A_DT1_S 22 1368 1369 /** MCPWM_GEN1_B_REG register 1370 * Actions triggered by events on PWM1B 1371 */ 1372 #define MCPWM_GEN1_B_REG(i) (REG_MCPWM_BASE(i) + 0x8c) 1373 /** MCPWM_GEN1_B_UTEZ : R/W; bitpos: [1:0]; default: 0; 1374 * Action on PWM1B triggered by event TEZ when timer increasing 1375 */ 1376 #define MCPWM_GEN1_B_UTEZ 0x00000003U 1377 #define MCPWM_GEN1_B_UTEZ_M (MCPWM_GEN1_B_UTEZ_V << MCPWM_GEN1_B_UTEZ_S) 1378 #define MCPWM_GEN1_B_UTEZ_V 0x00000003U 1379 #define MCPWM_GEN1_B_UTEZ_S 0 1380 /** MCPWM_GEN1_B_UTEP : R/W; bitpos: [3:2]; default: 0; 1381 * Action on PWM1B triggered by event TEP when timer increasing 1382 */ 1383 #define MCPWM_GEN1_B_UTEP 0x00000003U 1384 #define MCPWM_GEN1_B_UTEP_M (MCPWM_GEN1_B_UTEP_V << MCPWM_GEN1_B_UTEP_S) 1385 #define MCPWM_GEN1_B_UTEP_V 0x00000003U 1386 #define MCPWM_GEN1_B_UTEP_S 2 1387 /** MCPWM_GEN1_B_UTEA : R/W; bitpos: [5:4]; default: 0; 1388 * Action on PWM1B triggered by event TEA when timer increasing 1389 */ 1390 #define MCPWM_GEN1_B_UTEA 0x00000003U 1391 #define MCPWM_GEN1_B_UTEA_M (MCPWM_GEN1_B_UTEA_V << MCPWM_GEN1_B_UTEA_S) 1392 #define MCPWM_GEN1_B_UTEA_V 0x00000003U 1393 #define MCPWM_GEN1_B_UTEA_S 4 1394 /** MCPWM_GEN1_B_UTEB : R/W; bitpos: [7:6]; default: 0; 1395 * Action on PWM1B triggered by event TEB when timer increasing 1396 */ 1397 #define MCPWM_GEN1_B_UTEB 0x00000003U 1398 #define MCPWM_GEN1_B_UTEB_M (MCPWM_GEN1_B_UTEB_V << MCPWM_GEN1_B_UTEB_S) 1399 #define MCPWM_GEN1_B_UTEB_V 0x00000003U 1400 #define MCPWM_GEN1_B_UTEB_S 6 1401 /** MCPWM_GEN1_B_UT0 : R/W; bitpos: [9:8]; default: 0; 1402 * Action on PWM1B triggered by event_t0 when timer increasing 1403 */ 1404 #define MCPWM_GEN1_B_UT0 0x00000003U 1405 #define MCPWM_GEN1_B_UT0_M (MCPWM_GEN1_B_UT0_V << MCPWM_GEN1_B_UT0_S) 1406 #define MCPWM_GEN1_B_UT0_V 0x00000003U 1407 #define MCPWM_GEN1_B_UT0_S 8 1408 /** MCPWM_GEN1_B_UT1 : R/W; bitpos: [11:10]; default: 0; 1409 * Action on PWM1B triggered by event_t1 when timer increasing 1410 */ 1411 #define MCPWM_GEN1_B_UT1 0x00000003U 1412 #define MCPWM_GEN1_B_UT1_M (MCPWM_GEN1_B_UT1_V << MCPWM_GEN1_B_UT1_S) 1413 #define MCPWM_GEN1_B_UT1_V 0x00000003U 1414 #define MCPWM_GEN1_B_UT1_S 10 1415 /** MCPWM_GEN1_B_DTEZ : R/W; bitpos: [13:12]; default: 0; 1416 * Action on PWM1B triggered by event TEZ when timer decreasing 1417 */ 1418 #define MCPWM_GEN1_B_DTEZ 0x00000003U 1419 #define MCPWM_GEN1_B_DTEZ_M (MCPWM_GEN1_B_DTEZ_V << MCPWM_GEN1_B_DTEZ_S) 1420 #define MCPWM_GEN1_B_DTEZ_V 0x00000003U 1421 #define MCPWM_GEN1_B_DTEZ_S 12 1422 /** MCPWM_GEN1_B_DTEP : R/W; bitpos: [15:14]; default: 0; 1423 * Action on PWM1B triggered by event TEP when timer decreasing 1424 */ 1425 #define MCPWM_GEN1_B_DTEP 0x00000003U 1426 #define MCPWM_GEN1_B_DTEP_M (MCPWM_GEN1_B_DTEP_V << MCPWM_GEN1_B_DTEP_S) 1427 #define MCPWM_GEN1_B_DTEP_V 0x00000003U 1428 #define MCPWM_GEN1_B_DTEP_S 14 1429 /** MCPWM_GEN1_B_DTEA : R/W; bitpos: [17:16]; default: 0; 1430 * Action on PWM1B triggered by event TEA when timer decreasing 1431 */ 1432 #define MCPWM_GEN1_B_DTEA 0x00000003U 1433 #define MCPWM_GEN1_B_DTEA_M (MCPWM_GEN1_B_DTEA_V << MCPWM_GEN1_B_DTEA_S) 1434 #define MCPWM_GEN1_B_DTEA_V 0x00000003U 1435 #define MCPWM_GEN1_B_DTEA_S 16 1436 /** MCPWM_GEN1_B_DTEB : R/W; bitpos: [19:18]; default: 0; 1437 * Action on PWM1B triggered by event TEB when timer decreasing 1438 */ 1439 #define MCPWM_GEN1_B_DTEB 0x00000003U 1440 #define MCPWM_GEN1_B_DTEB_M (MCPWM_GEN1_B_DTEB_V << MCPWM_GEN1_B_DTEB_S) 1441 #define MCPWM_GEN1_B_DTEB_V 0x00000003U 1442 #define MCPWM_GEN1_B_DTEB_S 18 1443 /** MCPWM_GEN1_B_DT0 : R/W; bitpos: [21:20]; default: 0; 1444 * Action on PWM1B triggered by event_t0 when timer decreasing 1445 */ 1446 #define MCPWM_GEN1_B_DT0 0x00000003U 1447 #define MCPWM_GEN1_B_DT0_M (MCPWM_GEN1_B_DT0_V << MCPWM_GEN1_B_DT0_S) 1448 #define MCPWM_GEN1_B_DT0_V 0x00000003U 1449 #define MCPWM_GEN1_B_DT0_S 20 1450 /** MCPWM_GEN1_B_DT1 : R/W; bitpos: [23:22]; default: 0; 1451 * Action on PWM1B triggered by event_t1 when timer decreasing. 0: no change, 1: low, 1452 * 2: high, 3: toggle 1453 */ 1454 #define MCPWM_GEN1_B_DT1 0x00000003U 1455 #define MCPWM_GEN1_B_DT1_M (MCPWM_GEN1_B_DT1_V << MCPWM_GEN1_B_DT1_S) 1456 #define MCPWM_GEN1_B_DT1_V 0x00000003U 1457 #define MCPWM_GEN1_B_DT1_S 22 1458 1459 /** MCPWM_DT1_CFG_REG register 1460 * dead time type selection and configuration 1461 */ 1462 #define MCPWM_DT1_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x90) 1463 /** MCPWM_DB1_FED_UPMETHOD : R/W; bitpos: [3:0]; default: 0; 1464 * Update method for FED (falling edge delay) active register. 0: immediate, when bit0 1465 * is set to 1: tez, when bit1 is set to 1:tep, when bit2 is set to 1: sync, when 1466 * bit3 is set to 1: disable the update 1467 */ 1468 #define MCPWM_DB1_FED_UPMETHOD 0x0000000FU 1469 #define MCPWM_DB1_FED_UPMETHOD_M (MCPWM_DB1_FED_UPMETHOD_V << MCPWM_DB1_FED_UPMETHOD_S) 1470 #define MCPWM_DB1_FED_UPMETHOD_V 0x0000000FU 1471 #define MCPWM_DB1_FED_UPMETHOD_S 0 1472 /** MCPWM_DB1_RED_UPMETHOD : R/W; bitpos: [7:4]; default: 0; 1473 * Update method for RED (rising edge delay) active register. 0: immediate,when bit0 1474 * is set to 1: tez, when bit1 is set to 1:tep, when bit2 is set to 1: sync, when 1475 * bit3 is set to 1: disable the update 1476 */ 1477 #define MCPWM_DB1_RED_UPMETHOD 0x0000000FU 1478 #define MCPWM_DB1_RED_UPMETHOD_M (MCPWM_DB1_RED_UPMETHOD_V << MCPWM_DB1_RED_UPMETHOD_S) 1479 #define MCPWM_DB1_RED_UPMETHOD_V 0x0000000FU 1480 #define MCPWM_DB1_RED_UPMETHOD_S 4 1481 /** MCPWM_DB1_DEB_MODE : R/W; bitpos: [8]; default: 0; 1482 * S8 in table, dual-edge B mode, 0: fed/red take effect on different path separately, 1483 * 1: fed/red take effect on B path, A out is in bypass or dulpB mode 1484 */ 1485 #define MCPWM_DB1_DEB_MODE (BIT(8)) 1486 #define MCPWM_DB1_DEB_MODE_M (MCPWM_DB1_DEB_MODE_V << MCPWM_DB1_DEB_MODE_S) 1487 #define MCPWM_DB1_DEB_MODE_V 0x00000001U 1488 #define MCPWM_DB1_DEB_MODE_S 8 1489 /** MCPWM_DB1_A_OUTSWAP : R/W; bitpos: [9]; default: 0; 1490 * S6 in table 1491 */ 1492 #define MCPWM_DB1_A_OUTSWAP (BIT(9)) 1493 #define MCPWM_DB1_A_OUTSWAP_M (MCPWM_DB1_A_OUTSWAP_V << MCPWM_DB1_A_OUTSWAP_S) 1494 #define MCPWM_DB1_A_OUTSWAP_V 0x00000001U 1495 #define MCPWM_DB1_A_OUTSWAP_S 9 1496 /** MCPWM_DB1_B_OUTSWAP : R/W; bitpos: [10]; default: 0; 1497 * S7 in table 1498 */ 1499 #define MCPWM_DB1_B_OUTSWAP (BIT(10)) 1500 #define MCPWM_DB1_B_OUTSWAP_M (MCPWM_DB1_B_OUTSWAP_V << MCPWM_DB1_B_OUTSWAP_S) 1501 #define MCPWM_DB1_B_OUTSWAP_V 0x00000001U 1502 #define MCPWM_DB1_B_OUTSWAP_S 10 1503 /** MCPWM_DB1_RED_INSEL : R/W; bitpos: [11]; default: 0; 1504 * S4 in table 1505 */ 1506 #define MCPWM_DB1_RED_INSEL (BIT(11)) 1507 #define MCPWM_DB1_RED_INSEL_M (MCPWM_DB1_RED_INSEL_V << MCPWM_DB1_RED_INSEL_S) 1508 #define MCPWM_DB1_RED_INSEL_V 0x00000001U 1509 #define MCPWM_DB1_RED_INSEL_S 11 1510 /** MCPWM_DB1_FED_INSEL : R/W; bitpos: [12]; default: 0; 1511 * S5 in table 1512 */ 1513 #define MCPWM_DB1_FED_INSEL (BIT(12)) 1514 #define MCPWM_DB1_FED_INSEL_M (MCPWM_DB1_FED_INSEL_V << MCPWM_DB1_FED_INSEL_S) 1515 #define MCPWM_DB1_FED_INSEL_V 0x00000001U 1516 #define MCPWM_DB1_FED_INSEL_S 12 1517 /** MCPWM_DB1_RED_OUTINVERT : R/W; bitpos: [13]; default: 0; 1518 * S2 in table 1519 */ 1520 #define MCPWM_DB1_RED_OUTINVERT (BIT(13)) 1521 #define MCPWM_DB1_RED_OUTINVERT_M (MCPWM_DB1_RED_OUTINVERT_V << MCPWM_DB1_RED_OUTINVERT_S) 1522 #define MCPWM_DB1_RED_OUTINVERT_V 0x00000001U 1523 #define MCPWM_DB1_RED_OUTINVERT_S 13 1524 /** MCPWM_DB1_FED_OUTINVERT : R/W; bitpos: [14]; default: 0; 1525 * S3 in table 1526 */ 1527 #define MCPWM_DB1_FED_OUTINVERT (BIT(14)) 1528 #define MCPWM_DB1_FED_OUTINVERT_M (MCPWM_DB1_FED_OUTINVERT_V << MCPWM_DB1_FED_OUTINVERT_S) 1529 #define MCPWM_DB1_FED_OUTINVERT_V 0x00000001U 1530 #define MCPWM_DB1_FED_OUTINVERT_S 14 1531 /** MCPWM_DB1_A_OUTBYPASS : R/W; bitpos: [15]; default: 1; 1532 * S1 in table 1533 */ 1534 #define MCPWM_DB1_A_OUTBYPASS (BIT(15)) 1535 #define MCPWM_DB1_A_OUTBYPASS_M (MCPWM_DB1_A_OUTBYPASS_V << MCPWM_DB1_A_OUTBYPASS_S) 1536 #define MCPWM_DB1_A_OUTBYPASS_V 0x00000001U 1537 #define MCPWM_DB1_A_OUTBYPASS_S 15 1538 /** MCPWM_DB1_B_OUTBYPASS : R/W; bitpos: [16]; default: 1; 1539 * S0 in table 1540 */ 1541 #define MCPWM_DB1_B_OUTBYPASS (BIT(16)) 1542 #define MCPWM_DB1_B_OUTBYPASS_M (MCPWM_DB1_B_OUTBYPASS_V << MCPWM_DB1_B_OUTBYPASS_S) 1543 #define MCPWM_DB1_B_OUTBYPASS_V 0x00000001U 1544 #define MCPWM_DB1_B_OUTBYPASS_S 16 1545 /** MCPWM_DB1_CLK_SEL : R/W; bitpos: [17]; default: 0; 1546 * Dead time generator 1 clock selection. 0: PWM_clk, 1: PT_clk 1547 */ 1548 #define MCPWM_DB1_CLK_SEL (BIT(17)) 1549 #define MCPWM_DB1_CLK_SEL_M (MCPWM_DB1_CLK_SEL_V << MCPWM_DB1_CLK_SEL_S) 1550 #define MCPWM_DB1_CLK_SEL_V 0x00000001U 1551 #define MCPWM_DB1_CLK_SEL_S 17 1552 1553 /** MCPWM_DT1_FED_CFG_REG register 1554 * Shadow register for falling edge delay (FED). 1555 */ 1556 #define MCPWM_DT1_FED_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x94) 1557 /** MCPWM_DB1_FED : R/W; bitpos: [15:0]; default: 0; 1558 * Shadow register for FED 1559 */ 1560 #define MCPWM_DB1_FED 0x0000FFFFU 1561 #define MCPWM_DB1_FED_M (MCPWM_DB1_FED_V << MCPWM_DB1_FED_S) 1562 #define MCPWM_DB1_FED_V 0x0000FFFFU 1563 #define MCPWM_DB1_FED_S 0 1564 1565 /** MCPWM_DT1_RED_CFG_REG register 1566 * Shadow register for rising edge delay (RED). 1567 */ 1568 #define MCPWM_DT1_RED_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x98) 1569 /** MCPWM_DB1_RED : R/W; bitpos: [15:0]; default: 0; 1570 * Shadow register for RED 1571 */ 1572 #define MCPWM_DB1_RED 0x0000FFFFU 1573 #define MCPWM_DB1_RED_M (MCPWM_DB1_RED_V << MCPWM_DB1_RED_S) 1574 #define MCPWM_DB1_RED_V 0x0000FFFFU 1575 #define MCPWM_DB1_RED_S 0 1576 1577 /** MCPWM_CARRIER1_CFG_REG register 1578 * Carrier enable and configuratoin 1579 */ 1580 #define MCPWM_CARRIER1_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x9c) 1581 /** MCPWM_CHOPPER1_EN : R/W; bitpos: [0]; default: 0; 1582 * When set, carrier1 function is enabled. When cleared, carrier1 is bypassed 1583 */ 1584 #define MCPWM_CHOPPER1_EN (BIT(0)) 1585 #define MCPWM_CHOPPER1_EN_M (MCPWM_CHOPPER1_EN_V << MCPWM_CHOPPER1_EN_S) 1586 #define MCPWM_CHOPPER1_EN_V 0x00000001U 1587 #define MCPWM_CHOPPER1_EN_S 0 1588 /** MCPWM_CHOPPER1_PRESCALE : R/W; bitpos: [4:1]; default: 0; 1589 * PWM carrier1 clock (PC_clk) prescale value. Period of PC_clk = period of PWM_clk * 1590 * (PWM_CARRIER0_PRESCALE + 1) 1591 */ 1592 #define MCPWM_CHOPPER1_PRESCALE 0x0000000FU 1593 #define MCPWM_CHOPPER1_PRESCALE_M (MCPWM_CHOPPER1_PRESCALE_V << MCPWM_CHOPPER1_PRESCALE_S) 1594 #define MCPWM_CHOPPER1_PRESCALE_V 0x0000000FU 1595 #define MCPWM_CHOPPER1_PRESCALE_S 1 1596 /** MCPWM_CHOPPER1_DUTY : R/W; bitpos: [7:5]; default: 0; 1597 * carrier duty selection. Duty = PWM_CARRIER0_DUTY / 8 1598 */ 1599 #define MCPWM_CHOPPER1_DUTY 0x00000007U 1600 #define MCPWM_CHOPPER1_DUTY_M (MCPWM_CHOPPER1_DUTY_V << MCPWM_CHOPPER1_DUTY_S) 1601 #define MCPWM_CHOPPER1_DUTY_V 0x00000007U 1602 #define MCPWM_CHOPPER1_DUTY_S 5 1603 /** MCPWM_CHOPPER1_OSHTWTH : R/W; bitpos: [11:8]; default: 0; 1604 * width of the first pulse in number of periods of the carrier 1605 */ 1606 #define MCPWM_CHOPPER1_OSHTWTH 0x0000000FU 1607 #define MCPWM_CHOPPER1_OSHTWTH_M (MCPWM_CHOPPER1_OSHTWTH_V << MCPWM_CHOPPER1_OSHTWTH_S) 1608 #define MCPWM_CHOPPER1_OSHTWTH_V 0x0000000FU 1609 #define MCPWM_CHOPPER1_OSHTWTH_S 8 1610 /** MCPWM_CHOPPER1_OUT_INVERT : R/W; bitpos: [12]; default: 0; 1611 * when set, invert the output of PWM1A and PWM1B for this submodule 1612 */ 1613 #define MCPWM_CHOPPER1_OUT_INVERT (BIT(12)) 1614 #define MCPWM_CHOPPER1_OUT_INVERT_M (MCPWM_CHOPPER1_OUT_INVERT_V << MCPWM_CHOPPER1_OUT_INVERT_S) 1615 #define MCPWM_CHOPPER1_OUT_INVERT_V 0x00000001U 1616 #define MCPWM_CHOPPER1_OUT_INVERT_S 12 1617 /** MCPWM_CHOPPER1_IN_INVERT : R/W; bitpos: [13]; default: 0; 1618 * when set, invert the input of PWM1A and PWM1B for this submodule 1619 */ 1620 #define MCPWM_CHOPPER1_IN_INVERT (BIT(13)) 1621 #define MCPWM_CHOPPER1_IN_INVERT_M (MCPWM_CHOPPER1_IN_INVERT_V << MCPWM_CHOPPER1_IN_INVERT_S) 1622 #define MCPWM_CHOPPER1_IN_INVERT_V 0x00000001U 1623 #define MCPWM_CHOPPER1_IN_INVERT_S 13 1624 1625 /** MCPWM_FH1_CFG0_REG register 1626 * Actions on PWM1A and PWM1B trip events 1627 */ 1628 #define MCPWM_FH1_CFG0_REG(i) (REG_MCPWM_BASE(i) + 0xa0) 1629 /** MCPWM_TZ1_SW_CBC : R/W; bitpos: [0]; default: 0; 1630 * Enable register for software force cycle-by-cycle mode action. 0: disable, 1: enable 1631 */ 1632 #define MCPWM_TZ1_SW_CBC (BIT(0)) 1633 #define MCPWM_TZ1_SW_CBC_M (MCPWM_TZ1_SW_CBC_V << MCPWM_TZ1_SW_CBC_S) 1634 #define MCPWM_TZ1_SW_CBC_V 0x00000001U 1635 #define MCPWM_TZ1_SW_CBC_S 0 1636 /** MCPWM_TZ1_F2_CBC : R/W; bitpos: [1]; default: 0; 1637 * event_f2 will trigger cycle-by-cycle mode action. 0: disable, 1: enable 1638 */ 1639 #define MCPWM_TZ1_F2_CBC (BIT(1)) 1640 #define MCPWM_TZ1_F2_CBC_M (MCPWM_TZ1_F2_CBC_V << MCPWM_TZ1_F2_CBC_S) 1641 #define MCPWM_TZ1_F2_CBC_V 0x00000001U 1642 #define MCPWM_TZ1_F2_CBC_S 1 1643 /** MCPWM_TZ1_F1_CBC : R/W; bitpos: [2]; default: 0; 1644 * event_f1 will trigger cycle-by-cycle mode action. 0: disable, 1: enable 1645 */ 1646 #define MCPWM_TZ1_F1_CBC (BIT(2)) 1647 #define MCPWM_TZ1_F1_CBC_M (MCPWM_TZ1_F1_CBC_V << MCPWM_TZ1_F1_CBC_S) 1648 #define MCPWM_TZ1_F1_CBC_V 0x00000001U 1649 #define MCPWM_TZ1_F1_CBC_S 2 1650 /** MCPWM_TZ1_F0_CBC : R/W; bitpos: [3]; default: 0; 1651 * event_f0 will trigger cycle-by-cycle mode action. 0: disable, 1: enable 1652 */ 1653 #define MCPWM_TZ1_F0_CBC (BIT(3)) 1654 #define MCPWM_TZ1_F0_CBC_M (MCPWM_TZ1_F0_CBC_V << MCPWM_TZ1_F0_CBC_S) 1655 #define MCPWM_TZ1_F0_CBC_V 0x00000001U 1656 #define MCPWM_TZ1_F0_CBC_S 3 1657 /** MCPWM_TZ1_SW_OST : R/W; bitpos: [4]; default: 0; 1658 * Enable register for software force one-shot mode action. 0: disable, 1: enable 1659 */ 1660 #define MCPWM_TZ1_SW_OST (BIT(4)) 1661 #define MCPWM_TZ1_SW_OST_M (MCPWM_TZ1_SW_OST_V << MCPWM_TZ1_SW_OST_S) 1662 #define MCPWM_TZ1_SW_OST_V 0x00000001U 1663 #define MCPWM_TZ1_SW_OST_S 4 1664 /** MCPWM_TZ1_F2_OST : R/W; bitpos: [5]; default: 0; 1665 * event_f2 will trigger one-shot mode action. 0: disable, 1: enable 1666 */ 1667 #define MCPWM_TZ1_F2_OST (BIT(5)) 1668 #define MCPWM_TZ1_F2_OST_M (MCPWM_TZ1_F2_OST_V << MCPWM_TZ1_F2_OST_S) 1669 #define MCPWM_TZ1_F2_OST_V 0x00000001U 1670 #define MCPWM_TZ1_F2_OST_S 5 1671 /** MCPWM_TZ1_F1_OST : R/W; bitpos: [6]; default: 0; 1672 * event_f1 will trigger one-shot mode action. 0: disable, 1: enable 1673 */ 1674 #define MCPWM_TZ1_F1_OST (BIT(6)) 1675 #define MCPWM_TZ1_F1_OST_M (MCPWM_TZ1_F1_OST_V << MCPWM_TZ1_F1_OST_S) 1676 #define MCPWM_TZ1_F1_OST_V 0x00000001U 1677 #define MCPWM_TZ1_F1_OST_S 6 1678 /** MCPWM_TZ1_F0_OST : R/W; bitpos: [7]; default: 0; 1679 * event_f0 will trigger one-shot mode action. 0: disable, 1: enable 1680 */ 1681 #define MCPWM_TZ1_F0_OST (BIT(7)) 1682 #define MCPWM_TZ1_F0_OST_M (MCPWM_TZ1_F0_OST_V << MCPWM_TZ1_F0_OST_S) 1683 #define MCPWM_TZ1_F0_OST_V 0x00000001U 1684 #define MCPWM_TZ1_F0_OST_S 7 1685 /** MCPWM_TZ1_A_CBC_D : R/W; bitpos: [9:8]; default: 0; 1686 * Cycle-by-cycle mode action on PWM1A when fault event occurs and timer is 1687 * decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle 1688 */ 1689 #define MCPWM_TZ1_A_CBC_D 0x00000003U 1690 #define MCPWM_TZ1_A_CBC_D_M (MCPWM_TZ1_A_CBC_D_V << MCPWM_TZ1_A_CBC_D_S) 1691 #define MCPWM_TZ1_A_CBC_D_V 0x00000003U 1692 #define MCPWM_TZ1_A_CBC_D_S 8 1693 /** MCPWM_TZ1_A_CBC_U : R/W; bitpos: [11:10]; default: 0; 1694 * Cycle-by-cycle mode action on PWM1A when fault event occurs and timer is 1695 * increasing. 0: do nothing, 1: force low, 2: force high, 3: toggle 1696 */ 1697 #define MCPWM_TZ1_A_CBC_U 0x00000003U 1698 #define MCPWM_TZ1_A_CBC_U_M (MCPWM_TZ1_A_CBC_U_V << MCPWM_TZ1_A_CBC_U_S) 1699 #define MCPWM_TZ1_A_CBC_U_V 0x00000003U 1700 #define MCPWM_TZ1_A_CBC_U_S 10 1701 /** MCPWM_TZ1_A_OST_D : R/W; bitpos: [13:12]; default: 0; 1702 * One-shot mode action on PWM1A when fault event occurs and timer is decreasing. 0: 1703 * do nothing,1: force low, 2: force high, 3: toggle 1704 */ 1705 #define MCPWM_TZ1_A_OST_D 0x00000003U 1706 #define MCPWM_TZ1_A_OST_D_M (MCPWM_TZ1_A_OST_D_V << MCPWM_TZ1_A_OST_D_S) 1707 #define MCPWM_TZ1_A_OST_D_V 0x00000003U 1708 #define MCPWM_TZ1_A_OST_D_S 12 1709 /** MCPWM_TZ1_A_OST_U : R/W; bitpos: [15:14]; default: 0; 1710 * One-shot mode action on PWM1A when fault event occurs and timer is increasing. 0: 1711 * do nothing, 1: force low, 2: force high, 3: toggle 1712 */ 1713 #define MCPWM_TZ1_A_OST_U 0x00000003U 1714 #define MCPWM_TZ1_A_OST_U_M (MCPWM_TZ1_A_OST_U_V << MCPWM_TZ1_A_OST_U_S) 1715 #define MCPWM_TZ1_A_OST_U_V 0x00000003U 1716 #define MCPWM_TZ1_A_OST_U_S 14 1717 /** MCPWM_TZ1_B_CBC_D : R/W; bitpos: [17:16]; default: 0; 1718 * Cycle-by-cycle mode action on PWM1B when fault event occurs and timer is 1719 * decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle 1720 */ 1721 #define MCPWM_TZ1_B_CBC_D 0x00000003U 1722 #define MCPWM_TZ1_B_CBC_D_M (MCPWM_TZ1_B_CBC_D_V << MCPWM_TZ1_B_CBC_D_S) 1723 #define MCPWM_TZ1_B_CBC_D_V 0x00000003U 1724 #define MCPWM_TZ1_B_CBC_D_S 16 1725 /** MCPWM_TZ1_B_CBC_U : R/W; bitpos: [19:18]; default: 0; 1726 * Cycle-by-cycle mode action on PWM1B when fault event occurs and timer is 1727 * increasing. 0: do nothing, 1: force low, 2: force high, 3: toggle 1728 */ 1729 #define MCPWM_TZ1_B_CBC_U 0x00000003U 1730 #define MCPWM_TZ1_B_CBC_U_M (MCPWM_TZ1_B_CBC_U_V << MCPWM_TZ1_B_CBC_U_S) 1731 #define MCPWM_TZ1_B_CBC_U_V 0x00000003U 1732 #define MCPWM_TZ1_B_CBC_U_S 18 1733 /** MCPWM_TZ1_B_OST_D : R/W; bitpos: [21:20]; default: 0; 1734 * One-shot mode action on PWM1B when fault event occurs and timer is decreasing. 0: 1735 * do nothing, 1: force low, 2: force high, 3: toggle 1736 */ 1737 #define MCPWM_TZ1_B_OST_D 0x00000003U 1738 #define MCPWM_TZ1_B_OST_D_M (MCPWM_TZ1_B_OST_D_V << MCPWM_TZ1_B_OST_D_S) 1739 #define MCPWM_TZ1_B_OST_D_V 0x00000003U 1740 #define MCPWM_TZ1_B_OST_D_S 20 1741 /** MCPWM_TZ1_B_OST_U : R/W; bitpos: [23:22]; default: 0; 1742 * One-shot mode action on PWM1B when fault event occurs and timer is increasing. 0: 1743 * do nothing, 1: force low, 2: force high, 3: toggle 1744 */ 1745 #define MCPWM_TZ1_B_OST_U 0x00000003U 1746 #define MCPWM_TZ1_B_OST_U_M (MCPWM_TZ1_B_OST_U_V << MCPWM_TZ1_B_OST_U_S) 1747 #define MCPWM_TZ1_B_OST_U_V 0x00000003U 1748 #define MCPWM_TZ1_B_OST_U_S 22 1749 1750 /** MCPWM_FH1_CFG1_REG register 1751 * Software triggers for fault handler actions 1752 */ 1753 #define MCPWM_FH1_CFG1_REG(i) (REG_MCPWM_BASE(i) + 0xa4) 1754 /** MCPWM_TZ1_CLR_OST : R/W; bitpos: [0]; default: 0; 1755 * a rising edge will clear on going one-shot mode action 1756 */ 1757 #define MCPWM_TZ1_CLR_OST (BIT(0)) 1758 #define MCPWM_TZ1_CLR_OST_M (MCPWM_TZ1_CLR_OST_V << MCPWM_TZ1_CLR_OST_S) 1759 #define MCPWM_TZ1_CLR_OST_V 0x00000001U 1760 #define MCPWM_TZ1_CLR_OST_S 0 1761 /** MCPWM_TZ1_CBCPULSE : R/W; bitpos: [2:1]; default: 0; 1762 * cycle-by-cycle mode action refresh moment selection. When bit0 is set to 1: TEZ, 1763 * when bit1 is set to 1:TEP 1764 */ 1765 #define MCPWM_TZ1_CBCPULSE 0x00000003U 1766 #define MCPWM_TZ1_CBCPULSE_M (MCPWM_TZ1_CBCPULSE_V << MCPWM_TZ1_CBCPULSE_S) 1767 #define MCPWM_TZ1_CBCPULSE_V 0x00000003U 1768 #define MCPWM_TZ1_CBCPULSE_S 1 1769 /** MCPWM_TZ1_FORCE_CBC : R/W; bitpos: [3]; default: 0; 1770 * a toggle trigger a cycle-by-cycle mode action 1771 */ 1772 #define MCPWM_TZ1_FORCE_CBC (BIT(3)) 1773 #define MCPWM_TZ1_FORCE_CBC_M (MCPWM_TZ1_FORCE_CBC_V << MCPWM_TZ1_FORCE_CBC_S) 1774 #define MCPWM_TZ1_FORCE_CBC_V 0x00000001U 1775 #define MCPWM_TZ1_FORCE_CBC_S 3 1776 /** MCPWM_TZ1_FORCE_OST : R/W; bitpos: [4]; default: 0; 1777 * a toggle (software negate its value) triggers a one-shot mode action 1778 */ 1779 #define MCPWM_TZ1_FORCE_OST (BIT(4)) 1780 #define MCPWM_TZ1_FORCE_OST_M (MCPWM_TZ1_FORCE_OST_V << MCPWM_TZ1_FORCE_OST_S) 1781 #define MCPWM_TZ1_FORCE_OST_V 0x00000001U 1782 #define MCPWM_TZ1_FORCE_OST_S 4 1783 1784 /** MCPWM_FH1_STATUS_REG register 1785 * Status of fault events. 1786 */ 1787 #define MCPWM_FH1_STATUS_REG(i) (REG_MCPWM_BASE(i) + 0xa8) 1788 /** MCPWM_TZ1_CBC_ON : RO; bitpos: [0]; default: 0; 1789 * Set and reset by hardware. If set, a cycle-by-cycle mode action is on going 1790 */ 1791 #define MCPWM_TZ1_CBC_ON (BIT(0)) 1792 #define MCPWM_TZ1_CBC_ON_M (MCPWM_TZ1_CBC_ON_V << MCPWM_TZ1_CBC_ON_S) 1793 #define MCPWM_TZ1_CBC_ON_V 0x00000001U 1794 #define MCPWM_TZ1_CBC_ON_S 0 1795 /** MCPWM_TZ1_OST_ON : RO; bitpos: [1]; default: 0; 1796 * Set and reset by hardware. If set, an one-shot mode action is on going 1797 */ 1798 #define MCPWM_TZ1_OST_ON (BIT(1)) 1799 #define MCPWM_TZ1_OST_ON_M (MCPWM_TZ1_OST_ON_V << MCPWM_TZ1_OST_ON_S) 1800 #define MCPWM_TZ1_OST_ON_V 0x00000001U 1801 #define MCPWM_TZ1_OST_ON_S 1 1802 1803 /** MCPWM_GEN2_STMP_CFG_REG register 1804 * Transfer status and update method for time stamp registers A and B 1805 */ 1806 #define MCPWM_GEN2_STMP_CFG_REG(i) (REG_MCPWM_BASE(i) + 0xac) 1807 /** MCPWM_CMPR2_A_UPMETHOD : R/W; bitpos: [3:0]; default: 0; 1808 * Update method for PWM generator 2 time stamp A's active register. When all bits are 1809 * set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1: TEP,when 1810 * bit2 is set to 1: sync, when bit3 is set to 1: disable the update. 1811 */ 1812 #define MCPWM_CMPR2_A_UPMETHOD 0x0000000FU 1813 #define MCPWM_CMPR2_A_UPMETHOD_M (MCPWM_CMPR2_A_UPMETHOD_V << MCPWM_CMPR2_A_UPMETHOD_S) 1814 #define MCPWM_CMPR2_A_UPMETHOD_V 0x0000000FU 1815 #define MCPWM_CMPR2_A_UPMETHOD_S 0 1816 /** MCPWM_CMPR2_B_UPMETHOD : R/W; bitpos: [7:4]; default: 0; 1817 * Update method for PWM generator 2 time stamp B's active register. When all bits are 1818 * set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1: TEP,when 1819 * bit2 is set to 1: sync, when bit3 is set to 1: disable the update. 1820 */ 1821 #define MCPWM_CMPR2_B_UPMETHOD 0x0000000FU 1822 #define MCPWM_CMPR2_B_UPMETHOD_M (MCPWM_CMPR2_B_UPMETHOD_V << MCPWM_CMPR2_B_UPMETHOD_S) 1823 #define MCPWM_CMPR2_B_UPMETHOD_V 0x0000000FU 1824 #define MCPWM_CMPR2_B_UPMETHOD_S 4 1825 /** MCPWM_CMPR2_A_SHDW_FULL : R/W/WTC/SC; bitpos: [8]; default: 0; 1826 * Set and reset by hardware. If set, PWM generator 2 time stamp A's shadow reg is 1827 * filled and waiting to be transferred to A's active reg. If cleared, A's active reg 1828 * has been updated with shadow register latest value 1829 */ 1830 #define MCPWM_CMPR2_A_SHDW_FULL (BIT(8)) 1831 #define MCPWM_CMPR2_A_SHDW_FULL_M (MCPWM_CMPR2_A_SHDW_FULL_V << MCPWM_CMPR2_A_SHDW_FULL_S) 1832 #define MCPWM_CMPR2_A_SHDW_FULL_V 0x00000001U 1833 #define MCPWM_CMPR2_A_SHDW_FULL_S 8 1834 /** MCPWM_CMPR2_B_SHDW_FULL : R/W/WTC/SC; bitpos: [9]; default: 0; 1835 * Set and reset by hardware. If set, PWM generator 2 time stamp B's shadow reg is 1836 * filled and waiting to be transferred to B's active reg. If cleared, B's active reg 1837 * has been updated with shadow register latest value 1838 */ 1839 #define MCPWM_CMPR2_B_SHDW_FULL (BIT(9)) 1840 #define MCPWM_CMPR2_B_SHDW_FULL_M (MCPWM_CMPR2_B_SHDW_FULL_V << MCPWM_CMPR2_B_SHDW_FULL_S) 1841 #define MCPWM_CMPR2_B_SHDW_FULL_V 0x00000001U 1842 #define MCPWM_CMPR2_B_SHDW_FULL_S 9 1843 1844 /** MCPWM_GEN2_TSTMP_A_REG register 1845 * Shadow register for register A. 1846 */ 1847 #define MCPWM_GEN2_TSTMP_A_REG(i) (REG_MCPWM_BASE(i) + 0xb0) 1848 /** MCPWM_CMPR2_A : R/W; bitpos: [15:0]; default: 0; 1849 * PWM generator 2 time stamp A's shadow register 1850 */ 1851 #define MCPWM_CMPR2_A 0x0000FFFFU 1852 #define MCPWM_CMPR2_A_M (MCPWM_CMPR2_A_V << MCPWM_CMPR2_A_S) 1853 #define MCPWM_CMPR2_A_V 0x0000FFFFU 1854 #define MCPWM_CMPR2_A_S 0 1855 1856 /** MCPWM_GEN2_TSTMP_B_REG register 1857 * Shadow register for register B. 1858 */ 1859 #define MCPWM_GEN2_TSTMP_B_REG(i) (REG_MCPWM_BASE(i) + 0xb4) 1860 /** MCPWM_CMPR2_B : R/W; bitpos: [15:0]; default: 0; 1861 * PWM generator 2 time stamp B's shadow register 1862 */ 1863 #define MCPWM_CMPR2_B 0x0000FFFFU 1864 #define MCPWM_CMPR2_B_M (MCPWM_CMPR2_B_V << MCPWM_CMPR2_B_S) 1865 #define MCPWM_CMPR2_B_V 0x0000FFFFU 1866 #define MCPWM_CMPR2_B_S 0 1867 1868 /** MCPWM_GEN2_CFG0_REG register 1869 * Fault event T0 and T1 handling 1870 */ 1871 #define MCPWM_GEN2_CFG0_REG(i) (REG_MCPWM_BASE(i) + 0xb8) 1872 /** MCPWM_GEN2_CFG_UPMETHOD : R/W; bitpos: [3:0]; default: 0; 1873 * Update method for PWM generator 2's active register of configuration. 0: 1874 * immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1:sync;when bit3 is 1875 * set to 1:disable the update. 1876 */ 1877 #define MCPWM_GEN2_CFG_UPMETHOD 0x0000000FU 1878 #define MCPWM_GEN2_CFG_UPMETHOD_M (MCPWM_GEN2_CFG_UPMETHOD_V << MCPWM_GEN2_CFG_UPMETHOD_S) 1879 #define MCPWM_GEN2_CFG_UPMETHOD_V 0x0000000FU 1880 #define MCPWM_GEN2_CFG_UPMETHOD_S 0 1881 /** MCPWM_GEN2_T0_SEL : R/W; bitpos: [6:4]; default: 0; 1882 * Source selection for PWM generator 2 event_t0, take effect immediately, 0: 1883 * fault_event0, 1: fault_event1, 2: fault_event2, 3: sync_taken, 4: none 1884 */ 1885 #define MCPWM_GEN2_T0_SEL 0x00000007U 1886 #define MCPWM_GEN2_T0_SEL_M (MCPWM_GEN2_T0_SEL_V << MCPWM_GEN2_T0_SEL_S) 1887 #define MCPWM_GEN2_T0_SEL_V 0x00000007U 1888 #define MCPWM_GEN2_T0_SEL_S 4 1889 /** MCPWM_GEN2_T1_SEL : R/W; bitpos: [9:7]; default: 0; 1890 * Source selection for PWM generator 2 event_t1, take effect immediately, 0: 1891 * fault_event0, 1: fault_event1, 2: fault_event2, 3: sync_taken, 4: none 1892 */ 1893 #define MCPWM_GEN2_T1_SEL 0x00000007U 1894 #define MCPWM_GEN2_T1_SEL_M (MCPWM_GEN2_T1_SEL_V << MCPWM_GEN2_T1_SEL_S) 1895 #define MCPWM_GEN2_T1_SEL_V 0x00000007U 1896 #define MCPWM_GEN2_T1_SEL_S 7 1897 1898 /** MCPWM_GEN2_FORCE_REG register 1899 * Permissives to force PWM2A and PWM2B outputs by software 1900 */ 1901 #define MCPWM_GEN2_FORCE_REG(i) (REG_MCPWM_BASE(i) + 0xbc) 1902 /** MCPWM_GEN2_CNTUFORCE_UPMETHOD : R/W; bitpos: [5:0]; default: 32; 1903 * Updating method for continuous software force of PWM generator 2. When all bits are 1904 * set to 0: immediately, when bit0 is set to 1: TEZ,when bit1 is set to 1: TEP, when 1905 * bit2 is set to 1: TEA, when bit3 is set to 1: TEB, when bit4 is set to 1: sync, 1906 * when bit5 is set to 1: disable update. (TEA/B here and below means an event 1907 * generated when the timer's value equals to that of register A/B.) 1908 */ 1909 #define MCPWM_GEN2_CNTUFORCE_UPMETHOD 0x0000003FU 1910 #define MCPWM_GEN2_CNTUFORCE_UPMETHOD_M (MCPWM_GEN2_CNTUFORCE_UPMETHOD_V << MCPWM_GEN2_CNTUFORCE_UPMETHOD_S) 1911 #define MCPWM_GEN2_CNTUFORCE_UPMETHOD_V 0x0000003FU 1912 #define MCPWM_GEN2_CNTUFORCE_UPMETHOD_S 0 1913 /** MCPWM_GEN2_A_CNTUFORCE_MODE : R/W; bitpos: [7:6]; default: 0; 1914 * Continuous software force mode for PWM2A. 0: disabled, 1: low, 2: high, 3: disabled 1915 */ 1916 #define MCPWM_GEN2_A_CNTUFORCE_MODE 0x00000003U 1917 #define MCPWM_GEN2_A_CNTUFORCE_MODE_M (MCPWM_GEN2_A_CNTUFORCE_MODE_V << MCPWM_GEN2_A_CNTUFORCE_MODE_S) 1918 #define MCPWM_GEN2_A_CNTUFORCE_MODE_V 0x00000003U 1919 #define MCPWM_GEN2_A_CNTUFORCE_MODE_S 6 1920 /** MCPWM_GEN2_B_CNTUFORCE_MODE : R/W; bitpos: [9:8]; default: 0; 1921 * Continuous software force mode for PWM2B. 0: disabled, 1: low, 2: high, 3: disabled 1922 */ 1923 #define MCPWM_GEN2_B_CNTUFORCE_MODE 0x00000003U 1924 #define MCPWM_GEN2_B_CNTUFORCE_MODE_M (MCPWM_GEN2_B_CNTUFORCE_MODE_V << MCPWM_GEN2_B_CNTUFORCE_MODE_S) 1925 #define MCPWM_GEN2_B_CNTUFORCE_MODE_V 0x00000003U 1926 #define MCPWM_GEN2_B_CNTUFORCE_MODE_S 8 1927 /** MCPWM_GEN2_A_NCIFORCE : R/W; bitpos: [10]; default: 0; 1928 * Trigger of non-continuous immediate software-force event for PWM2A, a toggle will 1929 * trigger a force event. 1930 */ 1931 #define MCPWM_GEN2_A_NCIFORCE (BIT(10)) 1932 #define MCPWM_GEN2_A_NCIFORCE_M (MCPWM_GEN2_A_NCIFORCE_V << MCPWM_GEN2_A_NCIFORCE_S) 1933 #define MCPWM_GEN2_A_NCIFORCE_V 0x00000001U 1934 #define MCPWM_GEN2_A_NCIFORCE_S 10 1935 /** MCPWM_GEN2_A_NCIFORCE_MODE : R/W; bitpos: [12:11]; default: 0; 1936 * non-continuous immediate software force mode for PWM2A, 0: disabled, 1: low, 2: 1937 * high, 3: disabled 1938 */ 1939 #define MCPWM_GEN2_A_NCIFORCE_MODE 0x00000003U 1940 #define MCPWM_GEN2_A_NCIFORCE_MODE_M (MCPWM_GEN2_A_NCIFORCE_MODE_V << MCPWM_GEN2_A_NCIFORCE_MODE_S) 1941 #define MCPWM_GEN2_A_NCIFORCE_MODE_V 0x00000003U 1942 #define MCPWM_GEN2_A_NCIFORCE_MODE_S 11 1943 /** MCPWM_GEN2_B_NCIFORCE : R/W; bitpos: [13]; default: 0; 1944 * Trigger of non-continuous immediate software-force event for PWM2B, a toggle will 1945 * trigger a force event. 1946 */ 1947 #define MCPWM_GEN2_B_NCIFORCE (BIT(13)) 1948 #define MCPWM_GEN2_B_NCIFORCE_M (MCPWM_GEN2_B_NCIFORCE_V << MCPWM_GEN2_B_NCIFORCE_S) 1949 #define MCPWM_GEN2_B_NCIFORCE_V 0x00000001U 1950 #define MCPWM_GEN2_B_NCIFORCE_S 13 1951 /** MCPWM_GEN2_B_NCIFORCE_MODE : R/W; bitpos: [15:14]; default: 0; 1952 * non-continuous immediate software force mode for PWM2B, 0: disabled, 1: low, 2: 1953 * high, 3: disabled 1954 */ 1955 #define MCPWM_GEN2_B_NCIFORCE_MODE 0x00000003U 1956 #define MCPWM_GEN2_B_NCIFORCE_MODE_M (MCPWM_GEN2_B_NCIFORCE_MODE_V << MCPWM_GEN2_B_NCIFORCE_MODE_S) 1957 #define MCPWM_GEN2_B_NCIFORCE_MODE_V 0x00000003U 1958 #define MCPWM_GEN2_B_NCIFORCE_MODE_S 14 1959 1960 /** MCPWM_GEN2_A_REG register 1961 * Actions triggered by events on PWM2A 1962 */ 1963 #define MCPWM_GEN2_A_REG(i) (REG_MCPWM_BASE(i) + 0xc0) 1964 /** MCPWM_GEN2_A_UTEZ : R/W; bitpos: [1:0]; default: 0; 1965 * Action on PWM2A triggered by event TEZ when timer increasing 1966 */ 1967 #define MCPWM_GEN2_A_UTEZ 0x00000003U 1968 #define MCPWM_GEN2_A_UTEZ_M (MCPWM_GEN2_A_UTEZ_V << MCPWM_GEN2_A_UTEZ_S) 1969 #define MCPWM_GEN2_A_UTEZ_V 0x00000003U 1970 #define MCPWM_GEN2_A_UTEZ_S 0 1971 /** MCPWM_GEN2_A_UTEP : R/W; bitpos: [3:2]; default: 0; 1972 * Action on PWM2A triggered by event TEP when timer increasing 1973 */ 1974 #define MCPWM_GEN2_A_UTEP 0x00000003U 1975 #define MCPWM_GEN2_A_UTEP_M (MCPWM_GEN2_A_UTEP_V << MCPWM_GEN2_A_UTEP_S) 1976 #define MCPWM_GEN2_A_UTEP_V 0x00000003U 1977 #define MCPWM_GEN2_A_UTEP_S 2 1978 /** MCPWM_GEN2_A_UTEA : R/W; bitpos: [5:4]; default: 0; 1979 * Action on PWM2A triggered by event TEA when timer increasing 1980 */ 1981 #define MCPWM_GEN2_A_UTEA 0x00000003U 1982 #define MCPWM_GEN2_A_UTEA_M (MCPWM_GEN2_A_UTEA_V << MCPWM_GEN2_A_UTEA_S) 1983 #define MCPWM_GEN2_A_UTEA_V 0x00000003U 1984 #define MCPWM_GEN2_A_UTEA_S 4 1985 /** MCPWM_GEN2_A_UTEB : R/W; bitpos: [7:6]; default: 0; 1986 * Action on PWM2A triggered by event TEB when timer increasing 1987 */ 1988 #define MCPWM_GEN2_A_UTEB 0x00000003U 1989 #define MCPWM_GEN2_A_UTEB_M (MCPWM_GEN2_A_UTEB_V << MCPWM_GEN2_A_UTEB_S) 1990 #define MCPWM_GEN2_A_UTEB_V 0x00000003U 1991 #define MCPWM_GEN2_A_UTEB_S 6 1992 /** MCPWM_GEN2_A_UT0 : R/W; bitpos: [9:8]; default: 0; 1993 * Action on PWM2A triggered by event_t0 when timer increasing 1994 */ 1995 #define MCPWM_GEN2_A_UT0 0x00000003U 1996 #define MCPWM_GEN2_A_UT0_M (MCPWM_GEN2_A_UT0_V << MCPWM_GEN2_A_UT0_S) 1997 #define MCPWM_GEN2_A_UT0_V 0x00000003U 1998 #define MCPWM_GEN2_A_UT0_S 8 1999 /** MCPWM_GEN2_A_UT1 : R/W; bitpos: [11:10]; default: 0; 2000 * Action on PWM2A triggered by event_t1 when timer increasing 2001 */ 2002 #define MCPWM_GEN2_A_UT1 0x00000003U 2003 #define MCPWM_GEN2_A_UT1_M (MCPWM_GEN2_A_UT1_V << MCPWM_GEN2_A_UT1_S) 2004 #define MCPWM_GEN2_A_UT1_V 0x00000003U 2005 #define MCPWM_GEN2_A_UT1_S 10 2006 /** MCPWM_GEN2_A_DTEZ : R/W; bitpos: [13:12]; default: 0; 2007 * Action on PWM2A triggered by event TEZ when timer decreasing 2008 */ 2009 #define MCPWM_GEN2_A_DTEZ 0x00000003U 2010 #define MCPWM_GEN2_A_DTEZ_M (MCPWM_GEN2_A_DTEZ_V << MCPWM_GEN2_A_DTEZ_S) 2011 #define MCPWM_GEN2_A_DTEZ_V 0x00000003U 2012 #define MCPWM_GEN2_A_DTEZ_S 12 2013 /** MCPWM_GEN2_A_DTEP : R/W; bitpos: [15:14]; default: 0; 2014 * Action on PWM2A triggered by event TEP when timer decreasing 2015 */ 2016 #define MCPWM_GEN2_A_DTEP 0x00000003U 2017 #define MCPWM_GEN2_A_DTEP_M (MCPWM_GEN2_A_DTEP_V << MCPWM_GEN2_A_DTEP_S) 2018 #define MCPWM_GEN2_A_DTEP_V 0x00000003U 2019 #define MCPWM_GEN2_A_DTEP_S 14 2020 /** MCPWM_GEN2_A_DTEA : R/W; bitpos: [17:16]; default: 0; 2021 * Action on PWM2A triggered by event TEA when timer decreasing 2022 */ 2023 #define MCPWM_GEN2_A_DTEA 0x00000003U 2024 #define MCPWM_GEN2_A_DTEA_M (MCPWM_GEN2_A_DTEA_V << MCPWM_GEN2_A_DTEA_S) 2025 #define MCPWM_GEN2_A_DTEA_V 0x00000003U 2026 #define MCPWM_GEN2_A_DTEA_S 16 2027 /** MCPWM_GEN2_A_DTEB : R/W; bitpos: [19:18]; default: 0; 2028 * Action on PWM2A triggered by event TEB when timer decreasing 2029 */ 2030 #define MCPWM_GEN2_A_DTEB 0x00000003U 2031 #define MCPWM_GEN2_A_DTEB_M (MCPWM_GEN2_A_DTEB_V << MCPWM_GEN2_A_DTEB_S) 2032 #define MCPWM_GEN2_A_DTEB_V 0x00000003U 2033 #define MCPWM_GEN2_A_DTEB_S 18 2034 /** MCPWM_GEN2_A_DT0 : R/W; bitpos: [21:20]; default: 0; 2035 * Action on PWM2A triggered by event_t0 when timer decreasing 2036 */ 2037 #define MCPWM_GEN2_A_DT0 0x00000003U 2038 #define MCPWM_GEN2_A_DT0_M (MCPWM_GEN2_A_DT0_V << MCPWM_GEN2_A_DT0_S) 2039 #define MCPWM_GEN2_A_DT0_V 0x00000003U 2040 #define MCPWM_GEN2_A_DT0_S 20 2041 /** MCPWM_GEN2_A_DT1 : R/W; bitpos: [23:22]; default: 0; 2042 * Action on PWM2A triggered by event_t1 when timer decreasing. 0: no change, 1: low, 2043 * 2: high, 3: toggle 2044 */ 2045 #define MCPWM_GEN2_A_DT1 0x00000003U 2046 #define MCPWM_GEN2_A_DT1_M (MCPWM_GEN2_A_DT1_V << MCPWM_GEN2_A_DT1_S) 2047 #define MCPWM_GEN2_A_DT1_V 0x00000003U 2048 #define MCPWM_GEN2_A_DT1_S 22 2049 2050 /** MCPWM_GEN2_B_REG register 2051 * Actions triggered by events on PWM2B 2052 */ 2053 #define MCPWM_GEN2_B_REG(i) (REG_MCPWM_BASE(i) + 0xc4) 2054 /** MCPWM_GEN2_B_UTEZ : R/W; bitpos: [1:0]; default: 0; 2055 * Action on PWM2B triggered by event TEZ when timer increasing 2056 */ 2057 #define MCPWM_GEN2_B_UTEZ 0x00000003U 2058 #define MCPWM_GEN2_B_UTEZ_M (MCPWM_GEN2_B_UTEZ_V << MCPWM_GEN2_B_UTEZ_S) 2059 #define MCPWM_GEN2_B_UTEZ_V 0x00000003U 2060 #define MCPWM_GEN2_B_UTEZ_S 0 2061 /** MCPWM_GEN2_B_UTEP : R/W; bitpos: [3:2]; default: 0; 2062 * Action on PWM2B triggered by event TEP when timer increasing 2063 */ 2064 #define MCPWM_GEN2_B_UTEP 0x00000003U 2065 #define MCPWM_GEN2_B_UTEP_M (MCPWM_GEN2_B_UTEP_V << MCPWM_GEN2_B_UTEP_S) 2066 #define MCPWM_GEN2_B_UTEP_V 0x00000003U 2067 #define MCPWM_GEN2_B_UTEP_S 2 2068 /** MCPWM_GEN2_B_UTEA : R/W; bitpos: [5:4]; default: 0; 2069 * Action on PWM2B triggered by event TEA when timer increasing 2070 */ 2071 #define MCPWM_GEN2_B_UTEA 0x00000003U 2072 #define MCPWM_GEN2_B_UTEA_M (MCPWM_GEN2_B_UTEA_V << MCPWM_GEN2_B_UTEA_S) 2073 #define MCPWM_GEN2_B_UTEA_V 0x00000003U 2074 #define MCPWM_GEN2_B_UTEA_S 4 2075 /** MCPWM_GEN2_B_UTEB : R/W; bitpos: [7:6]; default: 0; 2076 * Action on PWM2B triggered by event TEB when timer increasing 2077 */ 2078 #define MCPWM_GEN2_B_UTEB 0x00000003U 2079 #define MCPWM_GEN2_B_UTEB_M (MCPWM_GEN2_B_UTEB_V << MCPWM_GEN2_B_UTEB_S) 2080 #define MCPWM_GEN2_B_UTEB_V 0x00000003U 2081 #define MCPWM_GEN2_B_UTEB_S 6 2082 /** MCPWM_GEN2_B_UT0 : R/W; bitpos: [9:8]; default: 0; 2083 * Action on PWM2B triggered by event_t0 when timer increasing 2084 */ 2085 #define MCPWM_GEN2_B_UT0 0x00000003U 2086 #define MCPWM_GEN2_B_UT0_M (MCPWM_GEN2_B_UT0_V << MCPWM_GEN2_B_UT0_S) 2087 #define MCPWM_GEN2_B_UT0_V 0x00000003U 2088 #define MCPWM_GEN2_B_UT0_S 8 2089 /** MCPWM_GEN2_B_UT1 : R/W; bitpos: [11:10]; default: 0; 2090 * Action on PWM2B triggered by event_t1 when timer increasing 2091 */ 2092 #define MCPWM_GEN2_B_UT1 0x00000003U 2093 #define MCPWM_GEN2_B_UT1_M (MCPWM_GEN2_B_UT1_V << MCPWM_GEN2_B_UT1_S) 2094 #define MCPWM_GEN2_B_UT1_V 0x00000003U 2095 #define MCPWM_GEN2_B_UT1_S 10 2096 /** MCPWM_GEN2_B_DTEZ : R/W; bitpos: [13:12]; default: 0; 2097 * Action on PWM2B triggered by event TEZ when timer decreasing 2098 */ 2099 #define MCPWM_GEN2_B_DTEZ 0x00000003U 2100 #define MCPWM_GEN2_B_DTEZ_M (MCPWM_GEN2_B_DTEZ_V << MCPWM_GEN2_B_DTEZ_S) 2101 #define MCPWM_GEN2_B_DTEZ_V 0x00000003U 2102 #define MCPWM_GEN2_B_DTEZ_S 12 2103 /** MCPWM_GEN2_B_DTEP : R/W; bitpos: [15:14]; default: 0; 2104 * Action on PWM2B triggered by event TEP when timer decreasing 2105 */ 2106 #define MCPWM_GEN2_B_DTEP 0x00000003U 2107 #define MCPWM_GEN2_B_DTEP_M (MCPWM_GEN2_B_DTEP_V << MCPWM_GEN2_B_DTEP_S) 2108 #define MCPWM_GEN2_B_DTEP_V 0x00000003U 2109 #define MCPWM_GEN2_B_DTEP_S 14 2110 /** MCPWM_GEN2_B_DTEA : R/W; bitpos: [17:16]; default: 0; 2111 * Action on PWM2B triggered by event TEA when timer decreasing 2112 */ 2113 #define MCPWM_GEN2_B_DTEA 0x00000003U 2114 #define MCPWM_GEN2_B_DTEA_M (MCPWM_GEN2_B_DTEA_V << MCPWM_GEN2_B_DTEA_S) 2115 #define MCPWM_GEN2_B_DTEA_V 0x00000003U 2116 #define MCPWM_GEN2_B_DTEA_S 16 2117 /** MCPWM_GEN2_B_DTEB : R/W; bitpos: [19:18]; default: 0; 2118 * Action on PWM2B triggered by event TEB when timer decreasing 2119 */ 2120 #define MCPWM_GEN2_B_DTEB 0x00000003U 2121 #define MCPWM_GEN2_B_DTEB_M (MCPWM_GEN2_B_DTEB_V << MCPWM_GEN2_B_DTEB_S) 2122 #define MCPWM_GEN2_B_DTEB_V 0x00000003U 2123 #define MCPWM_GEN2_B_DTEB_S 18 2124 /** MCPWM_GEN2_B_DT0 : R/W; bitpos: [21:20]; default: 0; 2125 * Action on PWM2B triggered by event_t0 when timer decreasing 2126 */ 2127 #define MCPWM_GEN2_B_DT0 0x00000003U 2128 #define MCPWM_GEN2_B_DT0_M (MCPWM_GEN2_B_DT0_V << MCPWM_GEN2_B_DT0_S) 2129 #define MCPWM_GEN2_B_DT0_V 0x00000003U 2130 #define MCPWM_GEN2_B_DT0_S 20 2131 /** MCPWM_GEN2_B_DT1 : R/W; bitpos: [23:22]; default: 0; 2132 * Action on PWM2B triggered by event_t1 when timer decreasing. 0: no change, 1: low, 2133 * 2: high, 3: toggle 2134 */ 2135 #define MCPWM_GEN2_B_DT1 0x00000003U 2136 #define MCPWM_GEN2_B_DT1_M (MCPWM_GEN2_B_DT1_V << MCPWM_GEN2_B_DT1_S) 2137 #define MCPWM_GEN2_B_DT1_V 0x00000003U 2138 #define MCPWM_GEN2_B_DT1_S 22 2139 2140 /** MCPWM_DT2_CFG_REG register 2141 * dead time type selection and configuration 2142 */ 2143 #define MCPWM_DT2_CFG_REG(i) (REG_MCPWM_BASE(i) + 0xc8) 2144 /** MCPWM_DB2_FED_UPMETHOD : R/W; bitpos: [3:0]; default: 0; 2145 * Update method for FED (falling edge delay) active register. 0: immediate,when bit0 2146 * is set to 1: tez, when bit1 is set to 1:tep, when bit2 is set to 1: sync, when 2147 * bit3 is set to 1: disable the update 2148 */ 2149 #define MCPWM_DB2_FED_UPMETHOD 0x0000000FU 2150 #define MCPWM_DB2_FED_UPMETHOD_M (MCPWM_DB2_FED_UPMETHOD_V << MCPWM_DB2_FED_UPMETHOD_S) 2151 #define MCPWM_DB2_FED_UPMETHOD_V 0x0000000FU 2152 #define MCPWM_DB2_FED_UPMETHOD_S 0 2153 /** MCPWM_DB2_RED_UPMETHOD : R/W; bitpos: [7:4]; default: 0; 2154 * Update method for RED (rising edge delay) active register. 0: immediate,when bit0 2155 * is set to 1: tez, when bit1 is set to 1:tep, when bit2 is set to 1: sync, when 2156 * bit3 is set to 1: disable the update 2157 */ 2158 #define MCPWM_DB2_RED_UPMETHOD 0x0000000FU 2159 #define MCPWM_DB2_RED_UPMETHOD_M (MCPWM_DB2_RED_UPMETHOD_V << MCPWM_DB2_RED_UPMETHOD_S) 2160 #define MCPWM_DB2_RED_UPMETHOD_V 0x0000000FU 2161 #define MCPWM_DB2_RED_UPMETHOD_S 4 2162 /** MCPWM_DB2_DEB_MODE : R/W; bitpos: [8]; default: 0; 2163 * S8 in table, dual-edge B mode, 0: fed/red take effect on different path separately, 2164 * 1: fed/red take effect on B path, A out is in bypass or dulpB mode 2165 */ 2166 #define MCPWM_DB2_DEB_MODE (BIT(8)) 2167 #define MCPWM_DB2_DEB_MODE_M (MCPWM_DB2_DEB_MODE_V << MCPWM_DB2_DEB_MODE_S) 2168 #define MCPWM_DB2_DEB_MODE_V 0x00000001U 2169 #define MCPWM_DB2_DEB_MODE_S 8 2170 /** MCPWM_DB2_A_OUTSWAP : R/W; bitpos: [9]; default: 0; 2171 * S6 in table 2172 */ 2173 #define MCPWM_DB2_A_OUTSWAP (BIT(9)) 2174 #define MCPWM_DB2_A_OUTSWAP_M (MCPWM_DB2_A_OUTSWAP_V << MCPWM_DB2_A_OUTSWAP_S) 2175 #define MCPWM_DB2_A_OUTSWAP_V 0x00000001U 2176 #define MCPWM_DB2_A_OUTSWAP_S 9 2177 /** MCPWM_DB2_B_OUTSWAP : R/W; bitpos: [10]; default: 0; 2178 * S7 in table 2179 */ 2180 #define MCPWM_DB2_B_OUTSWAP (BIT(10)) 2181 #define MCPWM_DB2_B_OUTSWAP_M (MCPWM_DB2_B_OUTSWAP_V << MCPWM_DB2_B_OUTSWAP_S) 2182 #define MCPWM_DB2_B_OUTSWAP_V 0x00000001U 2183 #define MCPWM_DB2_B_OUTSWAP_S 10 2184 /** MCPWM_DB2_RED_INSEL : R/W; bitpos: [11]; default: 0; 2185 * S4 in table 2186 */ 2187 #define MCPWM_DB2_RED_INSEL (BIT(11)) 2188 #define MCPWM_DB2_RED_INSEL_M (MCPWM_DB2_RED_INSEL_V << MCPWM_DB2_RED_INSEL_S) 2189 #define MCPWM_DB2_RED_INSEL_V 0x00000001U 2190 #define MCPWM_DB2_RED_INSEL_S 11 2191 /** MCPWM_DB2_FED_INSEL : R/W; bitpos: [12]; default: 0; 2192 * S5 in table 2193 */ 2194 #define MCPWM_DB2_FED_INSEL (BIT(12)) 2195 #define MCPWM_DB2_FED_INSEL_M (MCPWM_DB2_FED_INSEL_V << MCPWM_DB2_FED_INSEL_S) 2196 #define MCPWM_DB2_FED_INSEL_V 0x00000001U 2197 #define MCPWM_DB2_FED_INSEL_S 12 2198 /** MCPWM_DB2_RED_OUTINVERT : R/W; bitpos: [13]; default: 0; 2199 * S2 in table 2200 */ 2201 #define MCPWM_DB2_RED_OUTINVERT (BIT(13)) 2202 #define MCPWM_DB2_RED_OUTINVERT_M (MCPWM_DB2_RED_OUTINVERT_V << MCPWM_DB2_RED_OUTINVERT_S) 2203 #define MCPWM_DB2_RED_OUTINVERT_V 0x00000001U 2204 #define MCPWM_DB2_RED_OUTINVERT_S 13 2205 /** MCPWM_DB2_FED_OUTINVERT : R/W; bitpos: [14]; default: 0; 2206 * S3 in table 2207 */ 2208 #define MCPWM_DB2_FED_OUTINVERT (BIT(14)) 2209 #define MCPWM_DB2_FED_OUTINVERT_M (MCPWM_DB2_FED_OUTINVERT_V << MCPWM_DB2_FED_OUTINVERT_S) 2210 #define MCPWM_DB2_FED_OUTINVERT_V 0x00000001U 2211 #define MCPWM_DB2_FED_OUTINVERT_S 14 2212 /** MCPWM_DB2_A_OUTBYPASS : R/W; bitpos: [15]; default: 1; 2213 * S1 in table 2214 */ 2215 #define MCPWM_DB2_A_OUTBYPASS (BIT(15)) 2216 #define MCPWM_DB2_A_OUTBYPASS_M (MCPWM_DB2_A_OUTBYPASS_V << MCPWM_DB2_A_OUTBYPASS_S) 2217 #define MCPWM_DB2_A_OUTBYPASS_V 0x00000001U 2218 #define MCPWM_DB2_A_OUTBYPASS_S 15 2219 /** MCPWM_DB2_B_OUTBYPASS : R/W; bitpos: [16]; default: 1; 2220 * S0 in table 2221 */ 2222 #define MCPWM_DB2_B_OUTBYPASS (BIT(16)) 2223 #define MCPWM_DB2_B_OUTBYPASS_M (MCPWM_DB2_B_OUTBYPASS_V << MCPWM_DB2_B_OUTBYPASS_S) 2224 #define MCPWM_DB2_B_OUTBYPASS_V 0x00000001U 2225 #define MCPWM_DB2_B_OUTBYPASS_S 16 2226 /** MCPWM_DB2_CLK_SEL : R/W; bitpos: [17]; default: 0; 2227 * Dead time generator 2 clock selection. 0: PWM_clk, 1: PT_clk 2228 */ 2229 #define MCPWM_DB2_CLK_SEL (BIT(17)) 2230 #define MCPWM_DB2_CLK_SEL_M (MCPWM_DB2_CLK_SEL_V << MCPWM_DB2_CLK_SEL_S) 2231 #define MCPWM_DB2_CLK_SEL_V 0x00000001U 2232 #define MCPWM_DB2_CLK_SEL_S 17 2233 2234 /** MCPWM_DT2_FED_CFG_REG register 2235 * Shadow register for falling edge delay (FED). 2236 */ 2237 #define MCPWM_DT2_FED_CFG_REG(i) (REG_MCPWM_BASE(i) + 0xcc) 2238 /** MCPWM_DB2_FED : R/W; bitpos: [15:0]; default: 0; 2239 * Shadow register for FED 2240 */ 2241 #define MCPWM_DB2_FED 0x0000FFFFU 2242 #define MCPWM_DB2_FED_M (MCPWM_DB2_FED_V << MCPWM_DB2_FED_S) 2243 #define MCPWM_DB2_FED_V 0x0000FFFFU 2244 #define MCPWM_DB2_FED_S 0 2245 2246 /** MCPWM_DT2_RED_CFG_REG register 2247 * Shadow register for rising edge delay (RED). 2248 */ 2249 #define MCPWM_DT2_RED_CFG_REG(i) (REG_MCPWM_BASE(i) + 0xd0) 2250 /** MCPWM_DB2_RED : R/W; bitpos: [15:0]; default: 0; 2251 * Shadow register for RED 2252 */ 2253 #define MCPWM_DB2_RED 0x0000FFFFU 2254 #define MCPWM_DB2_RED_M (MCPWM_DB2_RED_V << MCPWM_DB2_RED_S) 2255 #define MCPWM_DB2_RED_V 0x0000FFFFU 2256 #define MCPWM_DB2_RED_S 0 2257 2258 /** MCPWM_CARRIER2_CFG_REG register 2259 * Carrier enable and configuratoin 2260 */ 2261 #define MCPWM_CARRIER2_CFG_REG(i) (REG_MCPWM_BASE(i) + 0xd4) 2262 /** MCPWM_CHOPPER2_EN : R/W; bitpos: [0]; default: 0; 2263 * When set, carrier2 function is enabled. When cleared, carrier2 is bypassed 2264 */ 2265 #define MCPWM_CHOPPER2_EN (BIT(0)) 2266 #define MCPWM_CHOPPER2_EN_M (MCPWM_CHOPPER2_EN_V << MCPWM_CHOPPER2_EN_S) 2267 #define MCPWM_CHOPPER2_EN_V 0x00000001U 2268 #define MCPWM_CHOPPER2_EN_S 0 2269 /** MCPWM_CHOPPER2_PRESCALE : R/W; bitpos: [4:1]; default: 0; 2270 * PWM carrier2 clock (PC_clk) prescale value. Period of PC_clk = period of PWM_clk * 2271 * (PWM_CARRIER0_PRESCALE + 1) 2272 */ 2273 #define MCPWM_CHOPPER2_PRESCALE 0x0000000FU 2274 #define MCPWM_CHOPPER2_PRESCALE_M (MCPWM_CHOPPER2_PRESCALE_V << MCPWM_CHOPPER2_PRESCALE_S) 2275 #define MCPWM_CHOPPER2_PRESCALE_V 0x0000000FU 2276 #define MCPWM_CHOPPER2_PRESCALE_S 1 2277 /** MCPWM_CHOPPER2_DUTY : R/W; bitpos: [7:5]; default: 0; 2278 * carrier duty selection. Duty = PWM_CARRIER0_DUTY / 8 2279 */ 2280 #define MCPWM_CHOPPER2_DUTY 0x00000007U 2281 #define MCPWM_CHOPPER2_DUTY_M (MCPWM_CHOPPER2_DUTY_V << MCPWM_CHOPPER2_DUTY_S) 2282 #define MCPWM_CHOPPER2_DUTY_V 0x00000007U 2283 #define MCPWM_CHOPPER2_DUTY_S 5 2284 /** MCPWM_CHOPPER2_OSHTWTH : R/W; bitpos: [11:8]; default: 0; 2285 * width of the first pulse in number of periods of the carrier 2286 */ 2287 #define MCPWM_CHOPPER2_OSHTWTH 0x0000000FU 2288 #define MCPWM_CHOPPER2_OSHTWTH_M (MCPWM_CHOPPER2_OSHTWTH_V << MCPWM_CHOPPER2_OSHTWTH_S) 2289 #define MCPWM_CHOPPER2_OSHTWTH_V 0x0000000FU 2290 #define MCPWM_CHOPPER2_OSHTWTH_S 8 2291 /** MCPWM_CHOPPER2_OUT_INVERT : R/W; bitpos: [12]; default: 0; 2292 * when set, invert the output of PWM2A and PWM2B for this submodule 2293 */ 2294 #define MCPWM_CHOPPER2_OUT_INVERT (BIT(12)) 2295 #define MCPWM_CHOPPER2_OUT_INVERT_M (MCPWM_CHOPPER2_OUT_INVERT_V << MCPWM_CHOPPER2_OUT_INVERT_S) 2296 #define MCPWM_CHOPPER2_OUT_INVERT_V 0x00000001U 2297 #define MCPWM_CHOPPER2_OUT_INVERT_S 12 2298 /** MCPWM_CHOPPER2_IN_INVERT : R/W; bitpos: [13]; default: 0; 2299 * when set, invert the input of PWM2A and PWM2B for this submodule 2300 */ 2301 #define MCPWM_CHOPPER2_IN_INVERT (BIT(13)) 2302 #define MCPWM_CHOPPER2_IN_INVERT_M (MCPWM_CHOPPER2_IN_INVERT_V << MCPWM_CHOPPER2_IN_INVERT_S) 2303 #define MCPWM_CHOPPER2_IN_INVERT_V 0x00000001U 2304 #define MCPWM_CHOPPER2_IN_INVERT_S 13 2305 2306 /** MCPWM_FH2_CFG0_REG register 2307 * Actions on PWM2A and PWM2B trip events 2308 */ 2309 #define MCPWM_FH2_CFG0_REG(i) (REG_MCPWM_BASE(i) + 0xd8) 2310 /** MCPWM_TZ2_SW_CBC : R/W; bitpos: [0]; default: 0; 2311 * Enable register for software force cycle-by-cycle mode action. 0: disable, 1: enable 2312 */ 2313 #define MCPWM_TZ2_SW_CBC (BIT(0)) 2314 #define MCPWM_TZ2_SW_CBC_M (MCPWM_TZ2_SW_CBC_V << MCPWM_TZ2_SW_CBC_S) 2315 #define MCPWM_TZ2_SW_CBC_V 0x00000001U 2316 #define MCPWM_TZ2_SW_CBC_S 0 2317 /** MCPWM_TZ2_F2_CBC : R/W; bitpos: [1]; default: 0; 2318 * event_f2 will trigger cycle-by-cycle mode action. 0: disable, 1: enable 2319 */ 2320 #define MCPWM_TZ2_F2_CBC (BIT(1)) 2321 #define MCPWM_TZ2_F2_CBC_M (MCPWM_TZ2_F2_CBC_V << MCPWM_TZ2_F2_CBC_S) 2322 #define MCPWM_TZ2_F2_CBC_V 0x00000001U 2323 #define MCPWM_TZ2_F2_CBC_S 1 2324 /** MCPWM_TZ2_F1_CBC : R/W; bitpos: [2]; default: 0; 2325 * event_f1 will trigger cycle-by-cycle mode action. 0: disable, 1: enable 2326 */ 2327 #define MCPWM_TZ2_F1_CBC (BIT(2)) 2328 #define MCPWM_TZ2_F1_CBC_M (MCPWM_TZ2_F1_CBC_V << MCPWM_TZ2_F1_CBC_S) 2329 #define MCPWM_TZ2_F1_CBC_V 0x00000001U 2330 #define MCPWM_TZ2_F1_CBC_S 2 2331 /** MCPWM_TZ2_F0_CBC : R/W; bitpos: [3]; default: 0; 2332 * event_f0 will trigger cycle-by-cycle mode action. 0: disable, 1: enable 2333 */ 2334 #define MCPWM_TZ2_F0_CBC (BIT(3)) 2335 #define MCPWM_TZ2_F0_CBC_M (MCPWM_TZ2_F0_CBC_V << MCPWM_TZ2_F0_CBC_S) 2336 #define MCPWM_TZ2_F0_CBC_V 0x00000001U 2337 #define MCPWM_TZ2_F0_CBC_S 3 2338 /** MCPWM_TZ2_SW_OST : R/W; bitpos: [4]; default: 0; 2339 * Enable register for software force one-shot mode action. 0: disable, 1: enable 2340 */ 2341 #define MCPWM_TZ2_SW_OST (BIT(4)) 2342 #define MCPWM_TZ2_SW_OST_M (MCPWM_TZ2_SW_OST_V << MCPWM_TZ2_SW_OST_S) 2343 #define MCPWM_TZ2_SW_OST_V 0x00000001U 2344 #define MCPWM_TZ2_SW_OST_S 4 2345 /** MCPWM_TZ2_F2_OST : R/W; bitpos: [5]; default: 0; 2346 * event_f2 will trigger one-shot mode action. 0: disable, 1: enable 2347 */ 2348 #define MCPWM_TZ2_F2_OST (BIT(5)) 2349 #define MCPWM_TZ2_F2_OST_M (MCPWM_TZ2_F2_OST_V << MCPWM_TZ2_F2_OST_S) 2350 #define MCPWM_TZ2_F2_OST_V 0x00000001U 2351 #define MCPWM_TZ2_F2_OST_S 5 2352 /** MCPWM_TZ2_F1_OST : R/W; bitpos: [6]; default: 0; 2353 * event_f1 will trigger one-shot mode action. 0: disable, 1: enable 2354 */ 2355 #define MCPWM_TZ2_F1_OST (BIT(6)) 2356 #define MCPWM_TZ2_F1_OST_M (MCPWM_TZ2_F1_OST_V << MCPWM_TZ2_F1_OST_S) 2357 #define MCPWM_TZ2_F1_OST_V 0x00000001U 2358 #define MCPWM_TZ2_F1_OST_S 6 2359 /** MCPWM_TZ2_F0_OST : R/W; bitpos: [7]; default: 0; 2360 * event_f0 will trigger one-shot mode action. 0: disable, 1: enable 2361 */ 2362 #define MCPWM_TZ2_F0_OST (BIT(7)) 2363 #define MCPWM_TZ2_F0_OST_M (MCPWM_TZ2_F0_OST_V << MCPWM_TZ2_F0_OST_S) 2364 #define MCPWM_TZ2_F0_OST_V 0x00000001U 2365 #define MCPWM_TZ2_F0_OST_S 7 2366 /** MCPWM_TZ2_A_CBC_D : R/W; bitpos: [9:8]; default: 0; 2367 * Cycle-by-cycle mode action on PWM2A when fault event occurs and timer is 2368 * decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle 2369 */ 2370 #define MCPWM_TZ2_A_CBC_D 0x00000003U 2371 #define MCPWM_TZ2_A_CBC_D_M (MCPWM_TZ2_A_CBC_D_V << MCPWM_TZ2_A_CBC_D_S) 2372 #define MCPWM_TZ2_A_CBC_D_V 0x00000003U 2373 #define MCPWM_TZ2_A_CBC_D_S 8 2374 /** MCPWM_TZ2_A_CBC_U : R/W; bitpos: [11:10]; default: 0; 2375 * Cycle-by-cycle mode action on PWM2A when fault event occurs and timer is 2376 * increasing. 0: do nothing, 1: force low, 2: force high, 3: toggle 2377 */ 2378 #define MCPWM_TZ2_A_CBC_U 0x00000003U 2379 #define MCPWM_TZ2_A_CBC_U_M (MCPWM_TZ2_A_CBC_U_V << MCPWM_TZ2_A_CBC_U_S) 2380 #define MCPWM_TZ2_A_CBC_U_V 0x00000003U 2381 #define MCPWM_TZ2_A_CBC_U_S 10 2382 /** MCPWM_TZ2_A_OST_D : R/W; bitpos: [13:12]; default: 0; 2383 * One-shot mode action on PWM2A when fault event occurs and timer is decreasing. 0: 2384 * do nothing, 1: force low, 2: force high, 3: toggle 2385 */ 2386 #define MCPWM_TZ2_A_OST_D 0x00000003U 2387 #define MCPWM_TZ2_A_OST_D_M (MCPWM_TZ2_A_OST_D_V << MCPWM_TZ2_A_OST_D_S) 2388 #define MCPWM_TZ2_A_OST_D_V 0x00000003U 2389 #define MCPWM_TZ2_A_OST_D_S 12 2390 /** MCPWM_TZ2_A_OST_U : R/W; bitpos: [15:14]; default: 0; 2391 * One-shot mode action on PWM2A when fault event occurs and timer is increasing. 0: 2392 * do nothing, 1: force low, 2: force high, 3: toggle 2393 */ 2394 #define MCPWM_TZ2_A_OST_U 0x00000003U 2395 #define MCPWM_TZ2_A_OST_U_M (MCPWM_TZ2_A_OST_U_V << MCPWM_TZ2_A_OST_U_S) 2396 #define MCPWM_TZ2_A_OST_U_V 0x00000003U 2397 #define MCPWM_TZ2_A_OST_U_S 14 2398 /** MCPWM_TZ2_B_CBC_D : R/W; bitpos: [17:16]; default: 0; 2399 * Cycle-by-cycle mode action on PWM2B when fault event occurs and timer is 2400 * decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle 2401 */ 2402 #define MCPWM_TZ2_B_CBC_D 0x00000003U 2403 #define MCPWM_TZ2_B_CBC_D_M (MCPWM_TZ2_B_CBC_D_V << MCPWM_TZ2_B_CBC_D_S) 2404 #define MCPWM_TZ2_B_CBC_D_V 0x00000003U 2405 #define MCPWM_TZ2_B_CBC_D_S 16 2406 /** MCPWM_TZ2_B_CBC_U : R/W; bitpos: [19:18]; default: 0; 2407 * Cycle-by-cycle mode action on PWM2B when fault event occurs and timer is 2408 * increasing. 0: do nothing, 1: force low, 2: force high, 3: toggle 2409 */ 2410 #define MCPWM_TZ2_B_CBC_U 0x00000003U 2411 #define MCPWM_TZ2_B_CBC_U_M (MCPWM_TZ2_B_CBC_U_V << MCPWM_TZ2_B_CBC_U_S) 2412 #define MCPWM_TZ2_B_CBC_U_V 0x00000003U 2413 #define MCPWM_TZ2_B_CBC_U_S 18 2414 /** MCPWM_TZ2_B_OST_D : R/W; bitpos: [21:20]; default: 0; 2415 * One-shot mode action on PWM2B when fault event occurs and timer is decreasing. 0: 2416 * do nothing, 1: force low, 2: force high, 3: toggle 2417 */ 2418 #define MCPWM_TZ2_B_OST_D 0x00000003U 2419 #define MCPWM_TZ2_B_OST_D_M (MCPWM_TZ2_B_OST_D_V << MCPWM_TZ2_B_OST_D_S) 2420 #define MCPWM_TZ2_B_OST_D_V 0x00000003U 2421 #define MCPWM_TZ2_B_OST_D_S 20 2422 /** MCPWM_TZ2_B_OST_U : R/W; bitpos: [23:22]; default: 0; 2423 * One-shot mode action on PWM2B when fault event occurs and timer is increasing. 0: 2424 * do nothing, 1: force low, 2: force high, 3: toggle 2425 */ 2426 #define MCPWM_TZ2_B_OST_U 0x00000003U 2427 #define MCPWM_TZ2_B_OST_U_M (MCPWM_TZ2_B_OST_U_V << MCPWM_TZ2_B_OST_U_S) 2428 #define MCPWM_TZ2_B_OST_U_V 0x00000003U 2429 #define MCPWM_TZ2_B_OST_U_S 22 2430 2431 /** MCPWM_FH2_CFG1_REG register 2432 * Software triggers for fault handler actions 2433 */ 2434 #define MCPWM_FH2_CFG1_REG(i) (REG_MCPWM_BASE(i) + 0xdc) 2435 /** MCPWM_TZ2_CLR_OST : R/W; bitpos: [0]; default: 0; 2436 * a rising edge will clear on going one-shot mode action 2437 */ 2438 #define MCPWM_TZ2_CLR_OST (BIT(0)) 2439 #define MCPWM_TZ2_CLR_OST_M (MCPWM_TZ2_CLR_OST_V << MCPWM_TZ2_CLR_OST_S) 2440 #define MCPWM_TZ2_CLR_OST_V 0x00000001U 2441 #define MCPWM_TZ2_CLR_OST_S 0 2442 /** MCPWM_TZ2_CBCPULSE : R/W; bitpos: [2:1]; default: 0; 2443 * cycle-by-cycle mode action refresh moment selection. When bit0 is set to 1: TEZ, 2444 * when bit1 is set to 1:TEP 2445 */ 2446 #define MCPWM_TZ2_CBCPULSE 0x00000003U 2447 #define MCPWM_TZ2_CBCPULSE_M (MCPWM_TZ2_CBCPULSE_V << MCPWM_TZ2_CBCPULSE_S) 2448 #define MCPWM_TZ2_CBCPULSE_V 0x00000003U 2449 #define MCPWM_TZ2_CBCPULSE_S 1 2450 /** MCPWM_TZ2_FORCE_CBC : R/W; bitpos: [3]; default: 0; 2451 * a toggle trigger a cycle-by-cycle mode action 2452 */ 2453 #define MCPWM_TZ2_FORCE_CBC (BIT(3)) 2454 #define MCPWM_TZ2_FORCE_CBC_M (MCPWM_TZ2_FORCE_CBC_V << MCPWM_TZ2_FORCE_CBC_S) 2455 #define MCPWM_TZ2_FORCE_CBC_V 0x00000001U 2456 #define MCPWM_TZ2_FORCE_CBC_S 3 2457 /** MCPWM_TZ2_FORCE_OST : R/W; bitpos: [4]; default: 0; 2458 * a toggle (software negate its value) triggers a one-shot mode action 2459 */ 2460 #define MCPWM_TZ2_FORCE_OST (BIT(4)) 2461 #define MCPWM_TZ2_FORCE_OST_M (MCPWM_TZ2_FORCE_OST_V << MCPWM_TZ2_FORCE_OST_S) 2462 #define MCPWM_TZ2_FORCE_OST_V 0x00000001U 2463 #define MCPWM_TZ2_FORCE_OST_S 4 2464 2465 /** MCPWM_FH2_STATUS_REG register 2466 * Status of fault events. 2467 */ 2468 #define MCPWM_FH2_STATUS_REG(i) (REG_MCPWM_BASE(i) + 0xe0) 2469 /** MCPWM_TZ2_CBC_ON : RO; bitpos: [0]; default: 0; 2470 * Set and reset by hardware. If set, a cycle-by-cycle mode action is on going 2471 */ 2472 #define MCPWM_TZ2_CBC_ON (BIT(0)) 2473 #define MCPWM_TZ2_CBC_ON_M (MCPWM_TZ2_CBC_ON_V << MCPWM_TZ2_CBC_ON_S) 2474 #define MCPWM_TZ2_CBC_ON_V 0x00000001U 2475 #define MCPWM_TZ2_CBC_ON_S 0 2476 /** MCPWM_TZ2_OST_ON : RO; bitpos: [1]; default: 0; 2477 * Set and reset by hardware. If set, an one-shot mode action is on going 2478 */ 2479 #define MCPWM_TZ2_OST_ON (BIT(1)) 2480 #define MCPWM_TZ2_OST_ON_M (MCPWM_TZ2_OST_ON_V << MCPWM_TZ2_OST_ON_S) 2481 #define MCPWM_TZ2_OST_ON_V 0x00000001U 2482 #define MCPWM_TZ2_OST_ON_S 1 2483 2484 /** MCPWM_FAULT_DETECT_REG register 2485 * Fault detection configuration and status 2486 */ 2487 #define MCPWM_FAULT_DETECT_REG(i) (REG_MCPWM_BASE(i) + 0xe4) 2488 /** MCPWM_F0_EN : R/W; bitpos: [0]; default: 0; 2489 * When set, event_f0 generation is enabled 2490 */ 2491 #define MCPWM_F0_EN (BIT(0)) 2492 #define MCPWM_F0_EN_M (MCPWM_F0_EN_V << MCPWM_F0_EN_S) 2493 #define MCPWM_F0_EN_V 0x00000001U 2494 #define MCPWM_F0_EN_S 0 2495 /** MCPWM_F1_EN : R/W; bitpos: [1]; default: 0; 2496 * When set, event_f1 generation is enabled 2497 */ 2498 #define MCPWM_F1_EN (BIT(1)) 2499 #define MCPWM_F1_EN_M (MCPWM_F1_EN_V << MCPWM_F1_EN_S) 2500 #define MCPWM_F1_EN_V 0x00000001U 2501 #define MCPWM_F1_EN_S 1 2502 /** MCPWM_F2_EN : R/W; bitpos: [2]; default: 0; 2503 * When set, event_f2 generation is enabled 2504 */ 2505 #define MCPWM_F2_EN (BIT(2)) 2506 #define MCPWM_F2_EN_M (MCPWM_F2_EN_V << MCPWM_F2_EN_S) 2507 #define MCPWM_F2_EN_V 0x00000001U 2508 #define MCPWM_F2_EN_S 2 2509 /** MCPWM_F0_POLE : R/W; bitpos: [3]; default: 0; 2510 * Set event_f0 trigger polarity on FAULT2 source from GPIO matrix. 0: level low, 1: 2511 * level high 2512 */ 2513 #define MCPWM_F0_POLE (BIT(3)) 2514 #define MCPWM_F0_POLE_M (MCPWM_F0_POLE_V << MCPWM_F0_POLE_S) 2515 #define MCPWM_F0_POLE_V 0x00000001U 2516 #define MCPWM_F0_POLE_S 3 2517 /** MCPWM_F1_POLE : R/W; bitpos: [4]; default: 0; 2518 * Set event_f1 trigger polarity on FAULT2 source from GPIO matrix. 0: level low, 1: 2519 * level high 2520 */ 2521 #define MCPWM_F1_POLE (BIT(4)) 2522 #define MCPWM_F1_POLE_M (MCPWM_F1_POLE_V << MCPWM_F1_POLE_S) 2523 #define MCPWM_F1_POLE_V 0x00000001U 2524 #define MCPWM_F1_POLE_S 4 2525 /** MCPWM_F2_POLE : R/W; bitpos: [5]; default: 0; 2526 * Set event_f2 trigger polarity on FAULT2 source from GPIO matrix. 0: level low, 1: 2527 * level high 2528 */ 2529 #define MCPWM_F2_POLE (BIT(5)) 2530 #define MCPWM_F2_POLE_M (MCPWM_F2_POLE_V << MCPWM_F2_POLE_S) 2531 #define MCPWM_F2_POLE_V 0x00000001U 2532 #define MCPWM_F2_POLE_S 5 2533 /** MCPWM_EVENT_F0 : RO; bitpos: [6]; default: 0; 2534 * Set and reset by hardware. If set, event_f0 is on going 2535 */ 2536 #define MCPWM_EVENT_F0 (BIT(6)) 2537 #define MCPWM_EVENT_F0_M (MCPWM_EVENT_F0_V << MCPWM_EVENT_F0_S) 2538 #define MCPWM_EVENT_F0_V 0x00000001U 2539 #define MCPWM_EVENT_F0_S 6 2540 /** MCPWM_EVENT_F1 : RO; bitpos: [7]; default: 0; 2541 * Set and reset by hardware. If set, event_f1 is on going 2542 */ 2543 #define MCPWM_EVENT_F1 (BIT(7)) 2544 #define MCPWM_EVENT_F1_M (MCPWM_EVENT_F1_V << MCPWM_EVENT_F1_S) 2545 #define MCPWM_EVENT_F1_V 0x00000001U 2546 #define MCPWM_EVENT_F1_S 7 2547 /** MCPWM_EVENT_F2 : RO; bitpos: [8]; default: 0; 2548 * Set and reset by hardware. If set, event_f2 is on going 2549 */ 2550 #define MCPWM_EVENT_F2 (BIT(8)) 2551 #define MCPWM_EVENT_F2_M (MCPWM_EVENT_F2_V << MCPWM_EVENT_F2_S) 2552 #define MCPWM_EVENT_F2_V 0x00000001U 2553 #define MCPWM_EVENT_F2_S 8 2554 2555 /** MCPWM_CAP_TIMER_CFG_REG register 2556 * Configure capture timer 2557 */ 2558 #define MCPWM_CAP_TIMER_CFG_REG(i) (REG_MCPWM_BASE(i) + 0xe8) 2559 /** MCPWM_CAP_TIMER_EN : R/W; bitpos: [0]; default: 0; 2560 * When set, capture timer incrementing under APB_clk is enabled. 2561 */ 2562 #define MCPWM_CAP_TIMER_EN (BIT(0)) 2563 #define MCPWM_CAP_TIMER_EN_M (MCPWM_CAP_TIMER_EN_V << MCPWM_CAP_TIMER_EN_S) 2564 #define MCPWM_CAP_TIMER_EN_V 0x00000001U 2565 #define MCPWM_CAP_TIMER_EN_S 0 2566 /** MCPWM_CAP_SYNCI_EN : R/W; bitpos: [1]; default: 0; 2567 * When set, capture timer sync is enabled. 2568 */ 2569 #define MCPWM_CAP_SYNCI_EN (BIT(1)) 2570 #define MCPWM_CAP_SYNCI_EN_M (MCPWM_CAP_SYNCI_EN_V << MCPWM_CAP_SYNCI_EN_S) 2571 #define MCPWM_CAP_SYNCI_EN_V 0x00000001U 2572 #define MCPWM_CAP_SYNCI_EN_S 1 2573 /** MCPWM_CAP_SYNCI_SEL : R/W; bitpos: [4:2]; default: 0; 2574 * capture module sync input selection. 0: none, 1: timer0 sync_out, 2: timer1 2575 * sync_out, 3: timer2 sync_out, 4: SYNC0 from GPIO matrix, 5: SYNC1 from GPIO matrix, 2576 * 6: SYNC2 from GPIO matrix 2577 */ 2578 #define MCPWM_CAP_SYNCI_SEL 0x00000007U 2579 #define MCPWM_CAP_SYNCI_SEL_M (MCPWM_CAP_SYNCI_SEL_V << MCPWM_CAP_SYNCI_SEL_S) 2580 #define MCPWM_CAP_SYNCI_SEL_V 0x00000007U 2581 #define MCPWM_CAP_SYNCI_SEL_S 2 2582 /** MCPWM_CAP_SYNC_SW : WT; bitpos: [5]; default: 0; 2583 * When reg_cap_synci_en is 1, write 1 will trigger a capture timer sync, capture 2584 * timer is loaded with value in phase register. 2585 */ 2586 #define MCPWM_CAP_SYNC_SW (BIT(5)) 2587 #define MCPWM_CAP_SYNC_SW_M (MCPWM_CAP_SYNC_SW_V << MCPWM_CAP_SYNC_SW_S) 2588 #define MCPWM_CAP_SYNC_SW_V 0x00000001U 2589 #define MCPWM_CAP_SYNC_SW_S 5 2590 2591 /** MCPWM_CAP_TIMER_PHASE_REG register 2592 * Phase for capture timer sync 2593 */ 2594 #define MCPWM_CAP_TIMER_PHASE_REG(i) (REG_MCPWM_BASE(i) + 0xec) 2595 /** MCPWM_CAP_PHASE : R/W; bitpos: [31:0]; default: 0; 2596 * Phase value for capture timer sync operation. 2597 */ 2598 #define MCPWM_CAP_PHASE 0xFFFFFFFFU 2599 #define MCPWM_CAP_PHASE_M (MCPWM_CAP_PHASE_V << MCPWM_CAP_PHASE_S) 2600 #define MCPWM_CAP_PHASE_V 0xFFFFFFFFU 2601 #define MCPWM_CAP_PHASE_S 0 2602 2603 /** MCPWM_CAP_CH0_CFG_REG register 2604 * Capture channel 0 configuration and enable 2605 */ 2606 #define MCPWM_CAP_CH0_CFG_REG(i) (REG_MCPWM_BASE(i) + 0xf0) 2607 /** MCPWM_CAP0_EN : R/W; bitpos: [0]; default: 0; 2608 * When set, capture on channel 0 is enabled 2609 */ 2610 #define MCPWM_CAP0_EN (BIT(0)) 2611 #define MCPWM_CAP0_EN_M (MCPWM_CAP0_EN_V << MCPWM_CAP0_EN_S) 2612 #define MCPWM_CAP0_EN_V 0x00000001U 2613 #define MCPWM_CAP0_EN_S 0 2614 /** MCPWM_CAP0_MODE : R/W; bitpos: [2:1]; default: 0; 2615 * Edge of capture on channel 0 after prescaling. When bit0 is set to 1: enable 2616 * capture on the negative edge, When bit1 is set to 1: enable capture on the positive 2617 * edge. 2618 */ 2619 #define MCPWM_CAP0_MODE 0x00000003U 2620 #define MCPWM_CAP0_MODE_M (MCPWM_CAP0_MODE_V << MCPWM_CAP0_MODE_S) 2621 #define MCPWM_CAP0_MODE_V 0x00000003U 2622 #define MCPWM_CAP0_MODE_S 1 2623 /** MCPWM_CAP0_PRESCALE : R/W; bitpos: [10:3]; default: 0; 2624 * Value of prescaling on possitive edge of CAP0. Prescale value = PWM_CAP0_PRESCALE + 2625 * 1 2626 */ 2627 #define MCPWM_CAP0_PRESCALE 0x000000FFU 2628 #define MCPWM_CAP0_PRESCALE_M (MCPWM_CAP0_PRESCALE_V << MCPWM_CAP0_PRESCALE_S) 2629 #define MCPWM_CAP0_PRESCALE_V 0x000000FFU 2630 #define MCPWM_CAP0_PRESCALE_S 3 2631 /** MCPWM_CAP0_IN_INVERT : R/W; bitpos: [11]; default: 0; 2632 * when set, CAP0 form GPIO matrix is inverted before prescale 2633 */ 2634 #define MCPWM_CAP0_IN_INVERT (BIT(11)) 2635 #define MCPWM_CAP0_IN_INVERT_M (MCPWM_CAP0_IN_INVERT_V << MCPWM_CAP0_IN_INVERT_S) 2636 #define MCPWM_CAP0_IN_INVERT_V 0x00000001U 2637 #define MCPWM_CAP0_IN_INVERT_S 11 2638 /** MCPWM_CAP0_SW : WT; bitpos: [12]; default: 0; 2639 * Write 1 will trigger a software forced capture on channel 0 2640 */ 2641 #define MCPWM_CAP0_SW (BIT(12)) 2642 #define MCPWM_CAP0_SW_M (MCPWM_CAP0_SW_V << MCPWM_CAP0_SW_S) 2643 #define MCPWM_CAP0_SW_V 0x00000001U 2644 #define MCPWM_CAP0_SW_S 12 2645 2646 /** MCPWM_CAP_CH1_CFG_REG register 2647 * Capture channel 1 configuration and enable 2648 */ 2649 #define MCPWM_CAP_CH1_CFG_REG(i) (REG_MCPWM_BASE(i) + 0xf4) 2650 /** MCPWM_CAP1_EN : R/W; bitpos: [0]; default: 0; 2651 * When set, capture on channel 2 is enabled 2652 */ 2653 #define MCPWM_CAP1_EN (BIT(0)) 2654 #define MCPWM_CAP1_EN_M (MCPWM_CAP1_EN_V << MCPWM_CAP1_EN_S) 2655 #define MCPWM_CAP1_EN_V 0x00000001U 2656 #define MCPWM_CAP1_EN_S 0 2657 /** MCPWM_CAP1_MODE : R/W; bitpos: [2:1]; default: 0; 2658 * Edge of capture on channel 1 after prescaling. When bit0 is set to 1: enable 2659 * capture on the negative edge, When bit1 is set to 1: enable capture on the positive 2660 * edge. 2661 */ 2662 #define MCPWM_CAP1_MODE 0x00000003U 2663 #define MCPWM_CAP1_MODE_M (MCPWM_CAP1_MODE_V << MCPWM_CAP1_MODE_S) 2664 #define MCPWM_CAP1_MODE_V 0x00000003U 2665 #define MCPWM_CAP1_MODE_S 1 2666 /** MCPWM_CAP1_PRESCALE : R/W; bitpos: [10:3]; default: 0; 2667 * Value of prescaling on possitive edge of CAP1. Prescale value = PWM_CAP1_PRESCALE + 2668 * 1 2669 */ 2670 #define MCPWM_CAP1_PRESCALE 0x000000FFU 2671 #define MCPWM_CAP1_PRESCALE_M (MCPWM_CAP1_PRESCALE_V << MCPWM_CAP1_PRESCALE_S) 2672 #define MCPWM_CAP1_PRESCALE_V 0x000000FFU 2673 #define MCPWM_CAP1_PRESCALE_S 3 2674 /** MCPWM_CAP1_IN_INVERT : R/W; bitpos: [11]; default: 0; 2675 * when set, CAP1 form GPIO matrix is inverted before prescale 2676 */ 2677 #define MCPWM_CAP1_IN_INVERT (BIT(11)) 2678 #define MCPWM_CAP1_IN_INVERT_M (MCPWM_CAP1_IN_INVERT_V << MCPWM_CAP1_IN_INVERT_S) 2679 #define MCPWM_CAP1_IN_INVERT_V 0x00000001U 2680 #define MCPWM_CAP1_IN_INVERT_S 11 2681 /** MCPWM_CAP1_SW : WT; bitpos: [12]; default: 0; 2682 * Write 1 will trigger a software forced capture on channel 1 2683 */ 2684 #define MCPWM_CAP1_SW (BIT(12)) 2685 #define MCPWM_CAP1_SW_M (MCPWM_CAP1_SW_V << MCPWM_CAP1_SW_S) 2686 #define MCPWM_CAP1_SW_V 0x00000001U 2687 #define MCPWM_CAP1_SW_S 12 2688 2689 /** MCPWM_CAP_CH2_CFG_REG register 2690 * Capture channel 2 configuration and enable 2691 */ 2692 #define MCPWM_CAP_CH2_CFG_REG(i) (REG_MCPWM_BASE(i) + 0xf8) 2693 /** MCPWM_CAP2_EN : R/W; bitpos: [0]; default: 0; 2694 * When set, capture on channel 2 is enabled 2695 */ 2696 #define MCPWM_CAP2_EN (BIT(0)) 2697 #define MCPWM_CAP2_EN_M (MCPWM_CAP2_EN_V << MCPWM_CAP2_EN_S) 2698 #define MCPWM_CAP2_EN_V 0x00000001U 2699 #define MCPWM_CAP2_EN_S 0 2700 /** MCPWM_CAP2_MODE : R/W; bitpos: [2:1]; default: 0; 2701 * Edge of capture on channel 2 after prescaling. When bit0 is set to 1: enable 2702 * capture on the negative edge, When bit1 is set to 1: enable capture on the positive 2703 * edge. 2704 */ 2705 #define MCPWM_CAP2_MODE 0x00000003U 2706 #define MCPWM_CAP2_MODE_M (MCPWM_CAP2_MODE_V << MCPWM_CAP2_MODE_S) 2707 #define MCPWM_CAP2_MODE_V 0x00000003U 2708 #define MCPWM_CAP2_MODE_S 1 2709 /** MCPWM_CAP2_PRESCALE : R/W; bitpos: [10:3]; default: 0; 2710 * Value of prescaling on possitive edge of CAP2. Prescale value = PWM_CAP2_PRESCALE + 2711 * 1 2712 */ 2713 #define MCPWM_CAP2_PRESCALE 0x000000FFU 2714 #define MCPWM_CAP2_PRESCALE_M (MCPWM_CAP2_PRESCALE_V << MCPWM_CAP2_PRESCALE_S) 2715 #define MCPWM_CAP2_PRESCALE_V 0x000000FFU 2716 #define MCPWM_CAP2_PRESCALE_S 3 2717 /** MCPWM_CAP2_IN_INVERT : R/W; bitpos: [11]; default: 0; 2718 * when set, CAP2 form GPIO matrix is inverted before prescale 2719 */ 2720 #define MCPWM_CAP2_IN_INVERT (BIT(11)) 2721 #define MCPWM_CAP2_IN_INVERT_M (MCPWM_CAP2_IN_INVERT_V << MCPWM_CAP2_IN_INVERT_S) 2722 #define MCPWM_CAP2_IN_INVERT_V 0x00000001U 2723 #define MCPWM_CAP2_IN_INVERT_S 11 2724 /** MCPWM_CAP2_SW : WT; bitpos: [12]; default: 0; 2725 * Write 1 will trigger a software forced capture on channel 2 2726 */ 2727 #define MCPWM_CAP2_SW (BIT(12)) 2728 #define MCPWM_CAP2_SW_M (MCPWM_CAP2_SW_V << MCPWM_CAP2_SW_S) 2729 #define MCPWM_CAP2_SW_V 0x00000001U 2730 #define MCPWM_CAP2_SW_S 12 2731 2732 /** MCPWM_CAP_CH0_REG register 2733 * ch0 capture value status register 2734 */ 2735 #define MCPWM_CAP_CH0_REG(i) (REG_MCPWM_BASE(i) + 0xfc) 2736 /** MCPWM_CAP0_VALUE : RO; bitpos: [31:0]; default: 0; 2737 * Value of last capture on channel 0 2738 */ 2739 #define MCPWM_CAP0_VALUE 0xFFFFFFFFU 2740 #define MCPWM_CAP0_VALUE_M (MCPWM_CAP0_VALUE_V << MCPWM_CAP0_VALUE_S) 2741 #define MCPWM_CAP0_VALUE_V 0xFFFFFFFFU 2742 #define MCPWM_CAP0_VALUE_S 0 2743 2744 /** MCPWM_CAP_CH1_REG register 2745 * ch1 capture value status register 2746 */ 2747 #define MCPWM_CAP_CH1_REG(i) (REG_MCPWM_BASE(i) + 0x100) 2748 /** MCPWM_CAP1_VALUE : RO; bitpos: [31:0]; default: 0; 2749 * Value of last capture on channel 1 2750 */ 2751 #define MCPWM_CAP1_VALUE 0xFFFFFFFFU 2752 #define MCPWM_CAP1_VALUE_M (MCPWM_CAP1_VALUE_V << MCPWM_CAP1_VALUE_S) 2753 #define MCPWM_CAP1_VALUE_V 0xFFFFFFFFU 2754 #define MCPWM_CAP1_VALUE_S 0 2755 2756 /** MCPWM_CAP_CH2_REG register 2757 * ch2 capture value status register 2758 */ 2759 #define MCPWM_CAP_CH2_REG(i) (REG_MCPWM_BASE(i) + 0x104) 2760 /** MCPWM_CAP2_VALUE : RO; bitpos: [31:0]; default: 0; 2761 * Value of last capture on channel 2 2762 */ 2763 #define MCPWM_CAP2_VALUE 0xFFFFFFFFU 2764 #define MCPWM_CAP2_VALUE_M (MCPWM_CAP2_VALUE_V << MCPWM_CAP2_VALUE_S) 2765 #define MCPWM_CAP2_VALUE_V 0xFFFFFFFFU 2766 #define MCPWM_CAP2_VALUE_S 0 2767 2768 /** MCPWM_CAP_STATUS_REG register 2769 * Edge of last capture trigger 2770 */ 2771 #define MCPWM_CAP_STATUS_REG(i) (REG_MCPWM_BASE(i) + 0x108) 2772 /** MCPWM_CAP0_EDGE : RO; bitpos: [0]; default: 0; 2773 * Edge of last capture trigger on channel 0, 0: posedge, 1: negedge 2774 */ 2775 #define MCPWM_CAP0_EDGE (BIT(0)) 2776 #define MCPWM_CAP0_EDGE_M (MCPWM_CAP0_EDGE_V << MCPWM_CAP0_EDGE_S) 2777 #define MCPWM_CAP0_EDGE_V 0x00000001U 2778 #define MCPWM_CAP0_EDGE_S 0 2779 /** MCPWM_CAP1_EDGE : RO; bitpos: [1]; default: 0; 2780 * Edge of last capture trigger on channel 1, 0: posedge, 1: negedge 2781 */ 2782 #define MCPWM_CAP1_EDGE (BIT(1)) 2783 #define MCPWM_CAP1_EDGE_M (MCPWM_CAP1_EDGE_V << MCPWM_CAP1_EDGE_S) 2784 #define MCPWM_CAP1_EDGE_V 0x00000001U 2785 #define MCPWM_CAP1_EDGE_S 1 2786 /** MCPWM_CAP2_EDGE : RO; bitpos: [2]; default: 0; 2787 * Edge of last capture trigger on channel 2, 0: posedge, 1: negedge 2788 */ 2789 #define MCPWM_CAP2_EDGE (BIT(2)) 2790 #define MCPWM_CAP2_EDGE_M (MCPWM_CAP2_EDGE_V << MCPWM_CAP2_EDGE_S) 2791 #define MCPWM_CAP2_EDGE_V 0x00000001U 2792 #define MCPWM_CAP2_EDGE_S 2 2793 2794 /** MCPWM_UPDATE_CFG_REG register 2795 * Enable update. 2796 */ 2797 #define MCPWM_UPDATE_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x10c) 2798 /** MCPWM_GLOBAL_UP_EN : R/W; bitpos: [0]; default: 1; 2799 * The global enable of update of all active registers in MCPWM module 2800 */ 2801 #define MCPWM_GLOBAL_UP_EN (BIT(0)) 2802 #define MCPWM_GLOBAL_UP_EN_M (MCPWM_GLOBAL_UP_EN_V << MCPWM_GLOBAL_UP_EN_S) 2803 #define MCPWM_GLOBAL_UP_EN_V 0x00000001U 2804 #define MCPWM_GLOBAL_UP_EN_S 0 2805 /** MCPWM_GLOBAL_FORCE_UP : R/W; bitpos: [1]; default: 0; 2806 * a toggle (software invert its value) will trigger a forced update of all active 2807 * registers in MCPWM module 2808 */ 2809 #define MCPWM_GLOBAL_FORCE_UP (BIT(1)) 2810 #define MCPWM_GLOBAL_FORCE_UP_M (MCPWM_GLOBAL_FORCE_UP_V << MCPWM_GLOBAL_FORCE_UP_S) 2811 #define MCPWM_GLOBAL_FORCE_UP_V 0x00000001U 2812 #define MCPWM_GLOBAL_FORCE_UP_S 1 2813 /** MCPWM_OP0_UP_EN : R/W; bitpos: [2]; default: 1; 2814 * When set and PWM_GLOBAL_UP_EN is set, update of active registers in PWM operator 0 2815 * are enabled 2816 */ 2817 #define MCPWM_OP0_UP_EN (BIT(2)) 2818 #define MCPWM_OP0_UP_EN_M (MCPWM_OP0_UP_EN_V << MCPWM_OP0_UP_EN_S) 2819 #define MCPWM_OP0_UP_EN_V 0x00000001U 2820 #define MCPWM_OP0_UP_EN_S 2 2821 /** MCPWM_OP0_FORCE_UP : R/W; bitpos: [3]; default: 0; 2822 * a toggle (software invert its value) will trigger a forced update of active 2823 * registers in PWM operator 0 2824 */ 2825 #define MCPWM_OP0_FORCE_UP (BIT(3)) 2826 #define MCPWM_OP0_FORCE_UP_M (MCPWM_OP0_FORCE_UP_V << MCPWM_OP0_FORCE_UP_S) 2827 #define MCPWM_OP0_FORCE_UP_V 0x00000001U 2828 #define MCPWM_OP0_FORCE_UP_S 3 2829 /** MCPWM_OP1_UP_EN : R/W; bitpos: [4]; default: 1; 2830 * When set and PWM_GLOBAL_UP_EN is set, update of active registers in PWM operator 1 2831 * are enabled 2832 */ 2833 #define MCPWM_OP1_UP_EN (BIT(4)) 2834 #define MCPWM_OP1_UP_EN_M (MCPWM_OP1_UP_EN_V << MCPWM_OP1_UP_EN_S) 2835 #define MCPWM_OP1_UP_EN_V 0x00000001U 2836 #define MCPWM_OP1_UP_EN_S 4 2837 /** MCPWM_OP1_FORCE_UP : R/W; bitpos: [5]; default: 0; 2838 * a toggle (software invert its value) will trigger a forced update of active 2839 * registers in PWM operator 1 2840 */ 2841 #define MCPWM_OP1_FORCE_UP (BIT(5)) 2842 #define MCPWM_OP1_FORCE_UP_M (MCPWM_OP1_FORCE_UP_V << MCPWM_OP1_FORCE_UP_S) 2843 #define MCPWM_OP1_FORCE_UP_V 0x00000001U 2844 #define MCPWM_OP1_FORCE_UP_S 5 2845 /** MCPWM_OP2_UP_EN : R/W; bitpos: [6]; default: 1; 2846 * When set and PWM_GLOBAL_UP_EN is set, update of active registers in PWM operator 2 2847 * are enabled 2848 */ 2849 #define MCPWM_OP2_UP_EN (BIT(6)) 2850 #define MCPWM_OP2_UP_EN_M (MCPWM_OP2_UP_EN_V << MCPWM_OP2_UP_EN_S) 2851 #define MCPWM_OP2_UP_EN_V 0x00000001U 2852 #define MCPWM_OP2_UP_EN_S 6 2853 /** MCPWM_OP2_FORCE_UP : R/W; bitpos: [7]; default: 0; 2854 * a toggle (software invert its value) will trigger a forced update of active 2855 * registers in PWM operator 2 2856 */ 2857 #define MCPWM_OP2_FORCE_UP (BIT(7)) 2858 #define MCPWM_OP2_FORCE_UP_M (MCPWM_OP2_FORCE_UP_V << MCPWM_OP2_FORCE_UP_S) 2859 #define MCPWM_OP2_FORCE_UP_V 0x00000001U 2860 #define MCPWM_OP2_FORCE_UP_S 7 2861 2862 /** MCPWM_INT_ENA_REG register 2863 * Interrupt enable bits 2864 */ 2865 #define MCPWM_INT_ENA_REG(i) (REG_MCPWM_BASE(i) + 0x110) 2866 /** MCPWM_TIMER0_STOP_INT_ENA : R/W; bitpos: [0]; default: 0; 2867 * The enable bit for the interrupt triggered when the timer 0 stops. 2868 */ 2869 #define MCPWM_TIMER0_STOP_INT_ENA (BIT(0)) 2870 #define MCPWM_TIMER0_STOP_INT_ENA_M (MCPWM_TIMER0_STOP_INT_ENA_V << MCPWM_TIMER0_STOP_INT_ENA_S) 2871 #define MCPWM_TIMER0_STOP_INT_ENA_V 0x00000001U 2872 #define MCPWM_TIMER0_STOP_INT_ENA_S 0 2873 /** MCPWM_TIMER1_STOP_INT_ENA : R/W; bitpos: [1]; default: 0; 2874 * The enable bit for the interrupt triggered when the timer 1 stops. 2875 */ 2876 #define MCPWM_TIMER1_STOP_INT_ENA (BIT(1)) 2877 #define MCPWM_TIMER1_STOP_INT_ENA_M (MCPWM_TIMER1_STOP_INT_ENA_V << MCPWM_TIMER1_STOP_INT_ENA_S) 2878 #define MCPWM_TIMER1_STOP_INT_ENA_V 0x00000001U 2879 #define MCPWM_TIMER1_STOP_INT_ENA_S 1 2880 /** MCPWM_TIMER2_STOP_INT_ENA : R/W; bitpos: [2]; default: 0; 2881 * The enable bit for the interrupt triggered when the timer 2 stops. 2882 */ 2883 #define MCPWM_TIMER2_STOP_INT_ENA (BIT(2)) 2884 #define MCPWM_TIMER2_STOP_INT_ENA_M (MCPWM_TIMER2_STOP_INT_ENA_V << MCPWM_TIMER2_STOP_INT_ENA_S) 2885 #define MCPWM_TIMER2_STOP_INT_ENA_V 0x00000001U 2886 #define MCPWM_TIMER2_STOP_INT_ENA_S 2 2887 /** MCPWM_TIMER0_TEZ_INT_ENA : R/W; bitpos: [3]; default: 0; 2888 * The enable bit for the interrupt triggered by a PWM timer 0 TEZ event. 2889 */ 2890 #define MCPWM_TIMER0_TEZ_INT_ENA (BIT(3)) 2891 #define MCPWM_TIMER0_TEZ_INT_ENA_M (MCPWM_TIMER0_TEZ_INT_ENA_V << MCPWM_TIMER0_TEZ_INT_ENA_S) 2892 #define MCPWM_TIMER0_TEZ_INT_ENA_V 0x00000001U 2893 #define MCPWM_TIMER0_TEZ_INT_ENA_S 3 2894 /** MCPWM_TIMER1_TEZ_INT_ENA : R/W; bitpos: [4]; default: 0; 2895 * The enable bit for the interrupt triggered by a PWM timer 1 TEZ event. 2896 */ 2897 #define MCPWM_TIMER1_TEZ_INT_ENA (BIT(4)) 2898 #define MCPWM_TIMER1_TEZ_INT_ENA_M (MCPWM_TIMER1_TEZ_INT_ENA_V << MCPWM_TIMER1_TEZ_INT_ENA_S) 2899 #define MCPWM_TIMER1_TEZ_INT_ENA_V 0x00000001U 2900 #define MCPWM_TIMER1_TEZ_INT_ENA_S 4 2901 /** MCPWM_TIMER2_TEZ_INT_ENA : R/W; bitpos: [5]; default: 0; 2902 * The enable bit for the interrupt triggered by a PWM timer 2 TEZ event. 2903 */ 2904 #define MCPWM_TIMER2_TEZ_INT_ENA (BIT(5)) 2905 #define MCPWM_TIMER2_TEZ_INT_ENA_M (MCPWM_TIMER2_TEZ_INT_ENA_V << MCPWM_TIMER2_TEZ_INT_ENA_S) 2906 #define MCPWM_TIMER2_TEZ_INT_ENA_V 0x00000001U 2907 #define MCPWM_TIMER2_TEZ_INT_ENA_S 5 2908 /** MCPWM_TIMER0_TEP_INT_ENA : R/W; bitpos: [6]; default: 0; 2909 * The enable bit for the interrupt triggered by a PWM timer 0 TEP event. 2910 */ 2911 #define MCPWM_TIMER0_TEP_INT_ENA (BIT(6)) 2912 #define MCPWM_TIMER0_TEP_INT_ENA_M (MCPWM_TIMER0_TEP_INT_ENA_V << MCPWM_TIMER0_TEP_INT_ENA_S) 2913 #define MCPWM_TIMER0_TEP_INT_ENA_V 0x00000001U 2914 #define MCPWM_TIMER0_TEP_INT_ENA_S 6 2915 /** MCPWM_TIMER1_TEP_INT_ENA : R/W; bitpos: [7]; default: 0; 2916 * The enable bit for the interrupt triggered by a PWM timer 1 TEP event. 2917 */ 2918 #define MCPWM_TIMER1_TEP_INT_ENA (BIT(7)) 2919 #define MCPWM_TIMER1_TEP_INT_ENA_M (MCPWM_TIMER1_TEP_INT_ENA_V << MCPWM_TIMER1_TEP_INT_ENA_S) 2920 #define MCPWM_TIMER1_TEP_INT_ENA_V 0x00000001U 2921 #define MCPWM_TIMER1_TEP_INT_ENA_S 7 2922 /** MCPWM_TIMER2_TEP_INT_ENA : R/W; bitpos: [8]; default: 0; 2923 * The enable bit for the interrupt triggered by a PWM timer 2 TEP event. 2924 */ 2925 #define MCPWM_TIMER2_TEP_INT_ENA (BIT(8)) 2926 #define MCPWM_TIMER2_TEP_INT_ENA_M (MCPWM_TIMER2_TEP_INT_ENA_V << MCPWM_TIMER2_TEP_INT_ENA_S) 2927 #define MCPWM_TIMER2_TEP_INT_ENA_V 0x00000001U 2928 #define MCPWM_TIMER2_TEP_INT_ENA_S 8 2929 /** MCPWM_FAULT0_INT_ENA : R/W; bitpos: [9]; default: 0; 2930 * The enable bit for the interrupt triggered when event_f0 starts. 2931 */ 2932 #define MCPWM_FAULT0_INT_ENA (BIT(9)) 2933 #define MCPWM_FAULT0_INT_ENA_M (MCPWM_FAULT0_INT_ENA_V << MCPWM_FAULT0_INT_ENA_S) 2934 #define MCPWM_FAULT0_INT_ENA_V 0x00000001U 2935 #define MCPWM_FAULT0_INT_ENA_S 9 2936 /** MCPWM_FAULT1_INT_ENA : R/W; bitpos: [10]; default: 0; 2937 * The enable bit for the interrupt triggered when event_f1 starts. 2938 */ 2939 #define MCPWM_FAULT1_INT_ENA (BIT(10)) 2940 #define MCPWM_FAULT1_INT_ENA_M (MCPWM_FAULT1_INT_ENA_V << MCPWM_FAULT1_INT_ENA_S) 2941 #define MCPWM_FAULT1_INT_ENA_V 0x00000001U 2942 #define MCPWM_FAULT1_INT_ENA_S 10 2943 /** MCPWM_FAULT2_INT_ENA : R/W; bitpos: [11]; default: 0; 2944 * The enable bit for the interrupt triggered when event_f2 starts. 2945 */ 2946 #define MCPWM_FAULT2_INT_ENA (BIT(11)) 2947 #define MCPWM_FAULT2_INT_ENA_M (MCPWM_FAULT2_INT_ENA_V << MCPWM_FAULT2_INT_ENA_S) 2948 #define MCPWM_FAULT2_INT_ENA_V 0x00000001U 2949 #define MCPWM_FAULT2_INT_ENA_S 11 2950 /** MCPWM_FAULT0_CLR_INT_ENA : R/W; bitpos: [12]; default: 0; 2951 * The enable bit for the interrupt triggered when event_f0 ends. 2952 */ 2953 #define MCPWM_FAULT0_CLR_INT_ENA (BIT(12)) 2954 #define MCPWM_FAULT0_CLR_INT_ENA_M (MCPWM_FAULT0_CLR_INT_ENA_V << MCPWM_FAULT0_CLR_INT_ENA_S) 2955 #define MCPWM_FAULT0_CLR_INT_ENA_V 0x00000001U 2956 #define MCPWM_FAULT0_CLR_INT_ENA_S 12 2957 /** MCPWM_FAULT1_CLR_INT_ENA : R/W; bitpos: [13]; default: 0; 2958 * The enable bit for the interrupt triggered when event_f1 ends. 2959 */ 2960 #define MCPWM_FAULT1_CLR_INT_ENA (BIT(13)) 2961 #define MCPWM_FAULT1_CLR_INT_ENA_M (MCPWM_FAULT1_CLR_INT_ENA_V << MCPWM_FAULT1_CLR_INT_ENA_S) 2962 #define MCPWM_FAULT1_CLR_INT_ENA_V 0x00000001U 2963 #define MCPWM_FAULT1_CLR_INT_ENA_S 13 2964 /** MCPWM_FAULT2_CLR_INT_ENA : R/W; bitpos: [14]; default: 0; 2965 * The enable bit for the interrupt triggered when event_f2 ends. 2966 */ 2967 #define MCPWM_FAULT2_CLR_INT_ENA (BIT(14)) 2968 #define MCPWM_FAULT2_CLR_INT_ENA_M (MCPWM_FAULT2_CLR_INT_ENA_V << MCPWM_FAULT2_CLR_INT_ENA_S) 2969 #define MCPWM_FAULT2_CLR_INT_ENA_V 0x00000001U 2970 #define MCPWM_FAULT2_CLR_INT_ENA_S 14 2971 /** MCPWM_CMPR0_TEA_INT_ENA : R/W; bitpos: [15]; default: 0; 2972 * The enable bit for the interrupt triggered by a PWM operator 0 TEA event 2973 */ 2974 #define MCPWM_CMPR0_TEA_INT_ENA (BIT(15)) 2975 #define MCPWM_CMPR0_TEA_INT_ENA_M (MCPWM_CMPR0_TEA_INT_ENA_V << MCPWM_CMPR0_TEA_INT_ENA_S) 2976 #define MCPWM_CMPR0_TEA_INT_ENA_V 0x00000001U 2977 #define MCPWM_CMPR0_TEA_INT_ENA_S 15 2978 /** MCPWM_CMPR1_TEA_INT_ENA : R/W; bitpos: [16]; default: 0; 2979 * The enable bit for the interrupt triggered by a PWM operator 1 TEA event 2980 */ 2981 #define MCPWM_CMPR1_TEA_INT_ENA (BIT(16)) 2982 #define MCPWM_CMPR1_TEA_INT_ENA_M (MCPWM_CMPR1_TEA_INT_ENA_V << MCPWM_CMPR1_TEA_INT_ENA_S) 2983 #define MCPWM_CMPR1_TEA_INT_ENA_V 0x00000001U 2984 #define MCPWM_CMPR1_TEA_INT_ENA_S 16 2985 /** MCPWM_CMPR2_TEA_INT_ENA : R/W; bitpos: [17]; default: 0; 2986 * The enable bit for the interrupt triggered by a PWM operator 2 TEA event 2987 */ 2988 #define MCPWM_CMPR2_TEA_INT_ENA (BIT(17)) 2989 #define MCPWM_CMPR2_TEA_INT_ENA_M (MCPWM_CMPR2_TEA_INT_ENA_V << MCPWM_CMPR2_TEA_INT_ENA_S) 2990 #define MCPWM_CMPR2_TEA_INT_ENA_V 0x00000001U 2991 #define MCPWM_CMPR2_TEA_INT_ENA_S 17 2992 /** MCPWM_CMPR0_TEB_INT_ENA : R/W; bitpos: [18]; default: 0; 2993 * The enable bit for the interrupt triggered by a PWM operator 0 TEB event 2994 */ 2995 #define MCPWM_CMPR0_TEB_INT_ENA (BIT(18)) 2996 #define MCPWM_CMPR0_TEB_INT_ENA_M (MCPWM_CMPR0_TEB_INT_ENA_V << MCPWM_CMPR0_TEB_INT_ENA_S) 2997 #define MCPWM_CMPR0_TEB_INT_ENA_V 0x00000001U 2998 #define MCPWM_CMPR0_TEB_INT_ENA_S 18 2999 /** MCPWM_CMPR1_TEB_INT_ENA : R/W; bitpos: [19]; default: 0; 3000 * The enable bit for the interrupt triggered by a PWM operator 1 TEB event 3001 */ 3002 #define MCPWM_CMPR1_TEB_INT_ENA (BIT(19)) 3003 #define MCPWM_CMPR1_TEB_INT_ENA_M (MCPWM_CMPR1_TEB_INT_ENA_V << MCPWM_CMPR1_TEB_INT_ENA_S) 3004 #define MCPWM_CMPR1_TEB_INT_ENA_V 0x00000001U 3005 #define MCPWM_CMPR1_TEB_INT_ENA_S 19 3006 /** MCPWM_CMPR2_TEB_INT_ENA : R/W; bitpos: [20]; default: 0; 3007 * The enable bit for the interrupt triggered by a PWM operator 2 TEB event 3008 */ 3009 #define MCPWM_CMPR2_TEB_INT_ENA (BIT(20)) 3010 #define MCPWM_CMPR2_TEB_INT_ENA_M (MCPWM_CMPR2_TEB_INT_ENA_V << MCPWM_CMPR2_TEB_INT_ENA_S) 3011 #define MCPWM_CMPR2_TEB_INT_ENA_V 0x00000001U 3012 #define MCPWM_CMPR2_TEB_INT_ENA_S 20 3013 /** MCPWM_TZ0_CBC_INT_ENA : R/W; bitpos: [21]; default: 0; 3014 * The enable bit for the interrupt triggered by a cycle-by-cycle mode action on PWM0. 3015 */ 3016 #define MCPWM_TZ0_CBC_INT_ENA (BIT(21)) 3017 #define MCPWM_TZ0_CBC_INT_ENA_M (MCPWM_TZ0_CBC_INT_ENA_V << MCPWM_TZ0_CBC_INT_ENA_S) 3018 #define MCPWM_TZ0_CBC_INT_ENA_V 0x00000001U 3019 #define MCPWM_TZ0_CBC_INT_ENA_S 21 3020 /** MCPWM_TZ1_CBC_INT_ENA : R/W; bitpos: [22]; default: 0; 3021 * The enable bit for the interrupt triggered by a cycle-by-cycle mode action on PWM1. 3022 */ 3023 #define MCPWM_TZ1_CBC_INT_ENA (BIT(22)) 3024 #define MCPWM_TZ1_CBC_INT_ENA_M (MCPWM_TZ1_CBC_INT_ENA_V << MCPWM_TZ1_CBC_INT_ENA_S) 3025 #define MCPWM_TZ1_CBC_INT_ENA_V 0x00000001U 3026 #define MCPWM_TZ1_CBC_INT_ENA_S 22 3027 /** MCPWM_TZ2_CBC_INT_ENA : R/W; bitpos: [23]; default: 0; 3028 * The enable bit for the interrupt triggered by a cycle-by-cycle mode action on PWM2. 3029 */ 3030 #define MCPWM_TZ2_CBC_INT_ENA (BIT(23)) 3031 #define MCPWM_TZ2_CBC_INT_ENA_M (MCPWM_TZ2_CBC_INT_ENA_V << MCPWM_TZ2_CBC_INT_ENA_S) 3032 #define MCPWM_TZ2_CBC_INT_ENA_V 0x00000001U 3033 #define MCPWM_TZ2_CBC_INT_ENA_S 23 3034 /** MCPWM_TZ0_OST_INT_ENA : R/W; bitpos: [24]; default: 0; 3035 * The enable bit for the interrupt triggered by a one-shot mode action on PWM0. 3036 */ 3037 #define MCPWM_TZ0_OST_INT_ENA (BIT(24)) 3038 #define MCPWM_TZ0_OST_INT_ENA_M (MCPWM_TZ0_OST_INT_ENA_V << MCPWM_TZ0_OST_INT_ENA_S) 3039 #define MCPWM_TZ0_OST_INT_ENA_V 0x00000001U 3040 #define MCPWM_TZ0_OST_INT_ENA_S 24 3041 /** MCPWM_TZ1_OST_INT_ENA : R/W; bitpos: [25]; default: 0; 3042 * The enable bit for the interrupt triggered by a one-shot mode action on PWM1. 3043 */ 3044 #define MCPWM_TZ1_OST_INT_ENA (BIT(25)) 3045 #define MCPWM_TZ1_OST_INT_ENA_M (MCPWM_TZ1_OST_INT_ENA_V << MCPWM_TZ1_OST_INT_ENA_S) 3046 #define MCPWM_TZ1_OST_INT_ENA_V 0x00000001U 3047 #define MCPWM_TZ1_OST_INT_ENA_S 25 3048 /** MCPWM_TZ2_OST_INT_ENA : R/W; bitpos: [26]; default: 0; 3049 * The enable bit for the interrupt triggered by a one-shot mode action on PWM2. 3050 */ 3051 #define MCPWM_TZ2_OST_INT_ENA (BIT(26)) 3052 #define MCPWM_TZ2_OST_INT_ENA_M (MCPWM_TZ2_OST_INT_ENA_V << MCPWM_TZ2_OST_INT_ENA_S) 3053 #define MCPWM_TZ2_OST_INT_ENA_V 0x00000001U 3054 #define MCPWM_TZ2_OST_INT_ENA_S 26 3055 /** MCPWM_CAP0_INT_ENA : R/W; bitpos: [27]; default: 0; 3056 * The enable bit for the interrupt triggered by capture on channel 0. 3057 */ 3058 #define MCPWM_CAP0_INT_ENA (BIT(27)) 3059 #define MCPWM_CAP0_INT_ENA_M (MCPWM_CAP0_INT_ENA_V << MCPWM_CAP0_INT_ENA_S) 3060 #define MCPWM_CAP0_INT_ENA_V 0x00000001U 3061 #define MCPWM_CAP0_INT_ENA_S 27 3062 /** MCPWM_CAP1_INT_ENA : R/W; bitpos: [28]; default: 0; 3063 * The enable bit for the interrupt triggered by capture on channel 1. 3064 */ 3065 #define MCPWM_CAP1_INT_ENA (BIT(28)) 3066 #define MCPWM_CAP1_INT_ENA_M (MCPWM_CAP1_INT_ENA_V << MCPWM_CAP1_INT_ENA_S) 3067 #define MCPWM_CAP1_INT_ENA_V 0x00000001U 3068 #define MCPWM_CAP1_INT_ENA_S 28 3069 /** MCPWM_CAP2_INT_ENA : R/W; bitpos: [29]; default: 0; 3070 * The enable bit for the interrupt triggered by capture on channel 2. 3071 */ 3072 #define MCPWM_CAP2_INT_ENA (BIT(29)) 3073 #define MCPWM_CAP2_INT_ENA_M (MCPWM_CAP2_INT_ENA_V << MCPWM_CAP2_INT_ENA_S) 3074 #define MCPWM_CAP2_INT_ENA_V 0x00000001U 3075 #define MCPWM_CAP2_INT_ENA_S 29 3076 3077 /** MCPWM_INT_RAW_REG register 3078 * Raw interrupt status 3079 */ 3080 #define MCPWM_INT_RAW_REG(i) (REG_MCPWM_BASE(i) + 0x114) 3081 /** MCPWM_TIMER0_STOP_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; 3082 * The raw status bit for the interrupt triggered when the timer 0 stops. 3083 */ 3084 #define MCPWM_TIMER0_STOP_INT_RAW (BIT(0)) 3085 #define MCPWM_TIMER0_STOP_INT_RAW_M (MCPWM_TIMER0_STOP_INT_RAW_V << MCPWM_TIMER0_STOP_INT_RAW_S) 3086 #define MCPWM_TIMER0_STOP_INT_RAW_V 0x00000001U 3087 #define MCPWM_TIMER0_STOP_INT_RAW_S 0 3088 /** MCPWM_TIMER1_STOP_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; 3089 * The raw status bit for the interrupt triggered when the timer 1 stops. 3090 */ 3091 #define MCPWM_TIMER1_STOP_INT_RAW (BIT(1)) 3092 #define MCPWM_TIMER1_STOP_INT_RAW_M (MCPWM_TIMER1_STOP_INT_RAW_V << MCPWM_TIMER1_STOP_INT_RAW_S) 3093 #define MCPWM_TIMER1_STOP_INT_RAW_V 0x00000001U 3094 #define MCPWM_TIMER1_STOP_INT_RAW_S 1 3095 /** MCPWM_TIMER2_STOP_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; 3096 * The raw status bit for the interrupt triggered when the timer 2 stops. 3097 */ 3098 #define MCPWM_TIMER2_STOP_INT_RAW (BIT(2)) 3099 #define MCPWM_TIMER2_STOP_INT_RAW_M (MCPWM_TIMER2_STOP_INT_RAW_V << MCPWM_TIMER2_STOP_INT_RAW_S) 3100 #define MCPWM_TIMER2_STOP_INT_RAW_V 0x00000001U 3101 #define MCPWM_TIMER2_STOP_INT_RAW_S 2 3102 /** MCPWM_TIMER0_TEZ_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; 3103 * The raw status bit for the interrupt triggered by a PWM timer 0 TEZ event. 3104 */ 3105 #define MCPWM_TIMER0_TEZ_INT_RAW (BIT(3)) 3106 #define MCPWM_TIMER0_TEZ_INT_RAW_M (MCPWM_TIMER0_TEZ_INT_RAW_V << MCPWM_TIMER0_TEZ_INT_RAW_S) 3107 #define MCPWM_TIMER0_TEZ_INT_RAW_V 0x00000001U 3108 #define MCPWM_TIMER0_TEZ_INT_RAW_S 3 3109 /** MCPWM_TIMER1_TEZ_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; 3110 * The raw status bit for the interrupt triggered by a PWM timer 1 TEZ event. 3111 */ 3112 #define MCPWM_TIMER1_TEZ_INT_RAW (BIT(4)) 3113 #define MCPWM_TIMER1_TEZ_INT_RAW_M (MCPWM_TIMER1_TEZ_INT_RAW_V << MCPWM_TIMER1_TEZ_INT_RAW_S) 3114 #define MCPWM_TIMER1_TEZ_INT_RAW_V 0x00000001U 3115 #define MCPWM_TIMER1_TEZ_INT_RAW_S 4 3116 /** MCPWM_TIMER2_TEZ_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; 3117 * The raw status bit for the interrupt triggered by a PWM timer 2 TEZ event. 3118 */ 3119 #define MCPWM_TIMER2_TEZ_INT_RAW (BIT(5)) 3120 #define MCPWM_TIMER2_TEZ_INT_RAW_M (MCPWM_TIMER2_TEZ_INT_RAW_V << MCPWM_TIMER2_TEZ_INT_RAW_S) 3121 #define MCPWM_TIMER2_TEZ_INT_RAW_V 0x00000001U 3122 #define MCPWM_TIMER2_TEZ_INT_RAW_S 5 3123 /** MCPWM_TIMER0_TEP_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0; 3124 * The raw status bit for the interrupt triggered by a PWM timer 0 TEP event. 3125 */ 3126 #define MCPWM_TIMER0_TEP_INT_RAW (BIT(6)) 3127 #define MCPWM_TIMER0_TEP_INT_RAW_M (MCPWM_TIMER0_TEP_INT_RAW_V << MCPWM_TIMER0_TEP_INT_RAW_S) 3128 #define MCPWM_TIMER0_TEP_INT_RAW_V 0x00000001U 3129 #define MCPWM_TIMER0_TEP_INT_RAW_S 6 3130 /** MCPWM_TIMER1_TEP_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0; 3131 * The raw status bit for the interrupt triggered by a PWM timer 1 TEP event. 3132 */ 3133 #define MCPWM_TIMER1_TEP_INT_RAW (BIT(7)) 3134 #define MCPWM_TIMER1_TEP_INT_RAW_M (MCPWM_TIMER1_TEP_INT_RAW_V << MCPWM_TIMER1_TEP_INT_RAW_S) 3135 #define MCPWM_TIMER1_TEP_INT_RAW_V 0x00000001U 3136 #define MCPWM_TIMER1_TEP_INT_RAW_S 7 3137 /** MCPWM_TIMER2_TEP_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0; 3138 * The raw status bit for the interrupt triggered by a PWM timer 2 TEP event. 3139 */ 3140 #define MCPWM_TIMER2_TEP_INT_RAW (BIT(8)) 3141 #define MCPWM_TIMER2_TEP_INT_RAW_M (MCPWM_TIMER2_TEP_INT_RAW_V << MCPWM_TIMER2_TEP_INT_RAW_S) 3142 #define MCPWM_TIMER2_TEP_INT_RAW_V 0x00000001U 3143 #define MCPWM_TIMER2_TEP_INT_RAW_S 8 3144 /** MCPWM_FAULT0_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0; 3145 * The raw status bit for the interrupt triggered when event_f0 starts. 3146 */ 3147 #define MCPWM_FAULT0_INT_RAW (BIT(9)) 3148 #define MCPWM_FAULT0_INT_RAW_M (MCPWM_FAULT0_INT_RAW_V << MCPWM_FAULT0_INT_RAW_S) 3149 #define MCPWM_FAULT0_INT_RAW_V 0x00000001U 3150 #define MCPWM_FAULT0_INT_RAW_S 9 3151 /** MCPWM_FAULT1_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0; 3152 * The raw status bit for the interrupt triggered when event_f1 starts. 3153 */ 3154 #define MCPWM_FAULT1_INT_RAW (BIT(10)) 3155 #define MCPWM_FAULT1_INT_RAW_M (MCPWM_FAULT1_INT_RAW_V << MCPWM_FAULT1_INT_RAW_S) 3156 #define MCPWM_FAULT1_INT_RAW_V 0x00000001U 3157 #define MCPWM_FAULT1_INT_RAW_S 10 3158 /** MCPWM_FAULT2_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0; 3159 * The raw status bit for the interrupt triggered when event_f2 starts. 3160 */ 3161 #define MCPWM_FAULT2_INT_RAW (BIT(11)) 3162 #define MCPWM_FAULT2_INT_RAW_M (MCPWM_FAULT2_INT_RAW_V << MCPWM_FAULT2_INT_RAW_S) 3163 #define MCPWM_FAULT2_INT_RAW_V 0x00000001U 3164 #define MCPWM_FAULT2_INT_RAW_S 11 3165 /** MCPWM_FAULT0_CLR_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0; 3166 * The raw status bit for the interrupt triggered when event_f0 ends. 3167 */ 3168 #define MCPWM_FAULT0_CLR_INT_RAW (BIT(12)) 3169 #define MCPWM_FAULT0_CLR_INT_RAW_M (MCPWM_FAULT0_CLR_INT_RAW_V << MCPWM_FAULT0_CLR_INT_RAW_S) 3170 #define MCPWM_FAULT0_CLR_INT_RAW_V 0x00000001U 3171 #define MCPWM_FAULT0_CLR_INT_RAW_S 12 3172 /** MCPWM_FAULT1_CLR_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0; 3173 * The raw status bit for the interrupt triggered when event_f1 ends. 3174 */ 3175 #define MCPWM_FAULT1_CLR_INT_RAW (BIT(13)) 3176 #define MCPWM_FAULT1_CLR_INT_RAW_M (MCPWM_FAULT1_CLR_INT_RAW_V << MCPWM_FAULT1_CLR_INT_RAW_S) 3177 #define MCPWM_FAULT1_CLR_INT_RAW_V 0x00000001U 3178 #define MCPWM_FAULT1_CLR_INT_RAW_S 13 3179 /** MCPWM_FAULT2_CLR_INT_RAW : R/WTC/SS; bitpos: [14]; default: 0; 3180 * The raw status bit for the interrupt triggered when event_f2 ends. 3181 */ 3182 #define MCPWM_FAULT2_CLR_INT_RAW (BIT(14)) 3183 #define MCPWM_FAULT2_CLR_INT_RAW_M (MCPWM_FAULT2_CLR_INT_RAW_V << MCPWM_FAULT2_CLR_INT_RAW_S) 3184 #define MCPWM_FAULT2_CLR_INT_RAW_V 0x00000001U 3185 #define MCPWM_FAULT2_CLR_INT_RAW_S 14 3186 /** MCPWM_CMPR0_TEA_INT_RAW : R/WTC/SS; bitpos: [15]; default: 0; 3187 * The raw status bit for the interrupt triggered by a PWM operator 0 TEA event 3188 */ 3189 #define MCPWM_CMPR0_TEA_INT_RAW (BIT(15)) 3190 #define MCPWM_CMPR0_TEA_INT_RAW_M (MCPWM_CMPR0_TEA_INT_RAW_V << MCPWM_CMPR0_TEA_INT_RAW_S) 3191 #define MCPWM_CMPR0_TEA_INT_RAW_V 0x00000001U 3192 #define MCPWM_CMPR0_TEA_INT_RAW_S 15 3193 /** MCPWM_CMPR1_TEA_INT_RAW : R/WTC/SS; bitpos: [16]; default: 0; 3194 * The raw status bit for the interrupt triggered by a PWM operator 1 TEA event 3195 */ 3196 #define MCPWM_CMPR1_TEA_INT_RAW (BIT(16)) 3197 #define MCPWM_CMPR1_TEA_INT_RAW_M (MCPWM_CMPR1_TEA_INT_RAW_V << MCPWM_CMPR1_TEA_INT_RAW_S) 3198 #define MCPWM_CMPR1_TEA_INT_RAW_V 0x00000001U 3199 #define MCPWM_CMPR1_TEA_INT_RAW_S 16 3200 /** MCPWM_CMPR2_TEA_INT_RAW : R/WTC/SS; bitpos: [17]; default: 0; 3201 * The raw status bit for the interrupt triggered by a PWM operator 2 TEA event 3202 */ 3203 #define MCPWM_CMPR2_TEA_INT_RAW (BIT(17)) 3204 #define MCPWM_CMPR2_TEA_INT_RAW_M (MCPWM_CMPR2_TEA_INT_RAW_V << MCPWM_CMPR2_TEA_INT_RAW_S) 3205 #define MCPWM_CMPR2_TEA_INT_RAW_V 0x00000001U 3206 #define MCPWM_CMPR2_TEA_INT_RAW_S 17 3207 /** MCPWM_CMPR0_TEB_INT_RAW : R/WTC/SS; bitpos: [18]; default: 0; 3208 * The raw status bit for the interrupt triggered by a PWM operator 0 TEB event 3209 */ 3210 #define MCPWM_CMPR0_TEB_INT_RAW (BIT(18)) 3211 #define MCPWM_CMPR0_TEB_INT_RAW_M (MCPWM_CMPR0_TEB_INT_RAW_V << MCPWM_CMPR0_TEB_INT_RAW_S) 3212 #define MCPWM_CMPR0_TEB_INT_RAW_V 0x00000001U 3213 #define MCPWM_CMPR0_TEB_INT_RAW_S 18 3214 /** MCPWM_CMPR1_TEB_INT_RAW : R/WTC/SS; bitpos: [19]; default: 0; 3215 * The raw status bit for the interrupt triggered by a PWM operator 1 TEB event 3216 */ 3217 #define MCPWM_CMPR1_TEB_INT_RAW (BIT(19)) 3218 #define MCPWM_CMPR1_TEB_INT_RAW_M (MCPWM_CMPR1_TEB_INT_RAW_V << MCPWM_CMPR1_TEB_INT_RAW_S) 3219 #define MCPWM_CMPR1_TEB_INT_RAW_V 0x00000001U 3220 #define MCPWM_CMPR1_TEB_INT_RAW_S 19 3221 /** MCPWM_CMPR2_TEB_INT_RAW : R/WTC/SS; bitpos: [20]; default: 0; 3222 * The raw status bit for the interrupt triggered by a PWM operator 2 TEB event 3223 */ 3224 #define MCPWM_CMPR2_TEB_INT_RAW (BIT(20)) 3225 #define MCPWM_CMPR2_TEB_INT_RAW_M (MCPWM_CMPR2_TEB_INT_RAW_V << MCPWM_CMPR2_TEB_INT_RAW_S) 3226 #define MCPWM_CMPR2_TEB_INT_RAW_V 0x00000001U 3227 #define MCPWM_CMPR2_TEB_INT_RAW_S 20 3228 /** MCPWM_TZ0_CBC_INT_RAW : R/WTC/SS; bitpos: [21]; default: 0; 3229 * The raw status bit for the interrupt triggered by a cycle-by-cycle mode action on 3230 * PWM0. 3231 */ 3232 #define MCPWM_TZ0_CBC_INT_RAW (BIT(21)) 3233 #define MCPWM_TZ0_CBC_INT_RAW_M (MCPWM_TZ0_CBC_INT_RAW_V << MCPWM_TZ0_CBC_INT_RAW_S) 3234 #define MCPWM_TZ0_CBC_INT_RAW_V 0x00000001U 3235 #define MCPWM_TZ0_CBC_INT_RAW_S 21 3236 /** MCPWM_TZ1_CBC_INT_RAW : R/WTC/SS; bitpos: [22]; default: 0; 3237 * The raw status bit for the interrupt triggered by a cycle-by-cycle mode action on 3238 * PWM1. 3239 */ 3240 #define MCPWM_TZ1_CBC_INT_RAW (BIT(22)) 3241 #define MCPWM_TZ1_CBC_INT_RAW_M (MCPWM_TZ1_CBC_INT_RAW_V << MCPWM_TZ1_CBC_INT_RAW_S) 3242 #define MCPWM_TZ1_CBC_INT_RAW_V 0x00000001U 3243 #define MCPWM_TZ1_CBC_INT_RAW_S 22 3244 /** MCPWM_TZ2_CBC_INT_RAW : R/WTC/SS; bitpos: [23]; default: 0; 3245 * The raw status bit for the interrupt triggered by a cycle-by-cycle mode action on 3246 * PWM2. 3247 */ 3248 #define MCPWM_TZ2_CBC_INT_RAW (BIT(23)) 3249 #define MCPWM_TZ2_CBC_INT_RAW_M (MCPWM_TZ2_CBC_INT_RAW_V << MCPWM_TZ2_CBC_INT_RAW_S) 3250 #define MCPWM_TZ2_CBC_INT_RAW_V 0x00000001U 3251 #define MCPWM_TZ2_CBC_INT_RAW_S 23 3252 /** MCPWM_TZ0_OST_INT_RAW : R/WTC/SS; bitpos: [24]; default: 0; 3253 * The raw status bit for the interrupt triggered by a one-shot mode action on PWM0. 3254 */ 3255 #define MCPWM_TZ0_OST_INT_RAW (BIT(24)) 3256 #define MCPWM_TZ0_OST_INT_RAW_M (MCPWM_TZ0_OST_INT_RAW_V << MCPWM_TZ0_OST_INT_RAW_S) 3257 #define MCPWM_TZ0_OST_INT_RAW_V 0x00000001U 3258 #define MCPWM_TZ0_OST_INT_RAW_S 24 3259 /** MCPWM_TZ1_OST_INT_RAW : R/WTC/SS; bitpos: [25]; default: 0; 3260 * The raw status bit for the interrupt triggered by a one-shot mode action on PWM1. 3261 */ 3262 #define MCPWM_TZ1_OST_INT_RAW (BIT(25)) 3263 #define MCPWM_TZ1_OST_INT_RAW_M (MCPWM_TZ1_OST_INT_RAW_V << MCPWM_TZ1_OST_INT_RAW_S) 3264 #define MCPWM_TZ1_OST_INT_RAW_V 0x00000001U 3265 #define MCPWM_TZ1_OST_INT_RAW_S 25 3266 /** MCPWM_TZ2_OST_INT_RAW : R/WTC/SS; bitpos: [26]; default: 0; 3267 * The raw status bit for the interrupt triggered by a one-shot mode action on PWM2. 3268 */ 3269 #define MCPWM_TZ2_OST_INT_RAW (BIT(26)) 3270 #define MCPWM_TZ2_OST_INT_RAW_M (MCPWM_TZ2_OST_INT_RAW_V << MCPWM_TZ2_OST_INT_RAW_S) 3271 #define MCPWM_TZ2_OST_INT_RAW_V 0x00000001U 3272 #define MCPWM_TZ2_OST_INT_RAW_S 26 3273 /** MCPWM_CAP0_INT_RAW : R/WTC/SS; bitpos: [27]; default: 0; 3274 * The raw status bit for the interrupt triggered by capture on channel 0. 3275 */ 3276 #define MCPWM_CAP0_INT_RAW (BIT(27)) 3277 #define MCPWM_CAP0_INT_RAW_M (MCPWM_CAP0_INT_RAW_V << MCPWM_CAP0_INT_RAW_S) 3278 #define MCPWM_CAP0_INT_RAW_V 0x00000001U 3279 #define MCPWM_CAP0_INT_RAW_S 27 3280 /** MCPWM_CAP1_INT_RAW : R/WTC/SS; bitpos: [28]; default: 0; 3281 * The raw status bit for the interrupt triggered by capture on channel 1. 3282 */ 3283 #define MCPWM_CAP1_INT_RAW (BIT(28)) 3284 #define MCPWM_CAP1_INT_RAW_M (MCPWM_CAP1_INT_RAW_V << MCPWM_CAP1_INT_RAW_S) 3285 #define MCPWM_CAP1_INT_RAW_V 0x00000001U 3286 #define MCPWM_CAP1_INT_RAW_S 28 3287 /** MCPWM_CAP2_INT_RAW : R/WTC/SS; bitpos: [29]; default: 0; 3288 * The raw status bit for the interrupt triggered by capture on channel 2. 3289 */ 3290 #define MCPWM_CAP2_INT_RAW (BIT(29)) 3291 #define MCPWM_CAP2_INT_RAW_M (MCPWM_CAP2_INT_RAW_V << MCPWM_CAP2_INT_RAW_S) 3292 #define MCPWM_CAP2_INT_RAW_V 0x00000001U 3293 #define MCPWM_CAP2_INT_RAW_S 29 3294 3295 /** MCPWM_INT_ST_REG register 3296 * Masked interrupt status 3297 */ 3298 #define MCPWM_INT_ST_REG(i) (REG_MCPWM_BASE(i) + 0x118) 3299 /** MCPWM_TIMER0_STOP_INT_ST : RO; bitpos: [0]; default: 0; 3300 * The masked status bit for the interrupt triggered when the timer 0 stops. 3301 */ 3302 #define MCPWM_TIMER0_STOP_INT_ST (BIT(0)) 3303 #define MCPWM_TIMER0_STOP_INT_ST_M (MCPWM_TIMER0_STOP_INT_ST_V << MCPWM_TIMER0_STOP_INT_ST_S) 3304 #define MCPWM_TIMER0_STOP_INT_ST_V 0x00000001U 3305 #define MCPWM_TIMER0_STOP_INT_ST_S 0 3306 /** MCPWM_TIMER1_STOP_INT_ST : RO; bitpos: [1]; default: 0; 3307 * The masked status bit for the interrupt triggered when the timer 1 stops. 3308 */ 3309 #define MCPWM_TIMER1_STOP_INT_ST (BIT(1)) 3310 #define MCPWM_TIMER1_STOP_INT_ST_M (MCPWM_TIMER1_STOP_INT_ST_V << MCPWM_TIMER1_STOP_INT_ST_S) 3311 #define MCPWM_TIMER1_STOP_INT_ST_V 0x00000001U 3312 #define MCPWM_TIMER1_STOP_INT_ST_S 1 3313 /** MCPWM_TIMER2_STOP_INT_ST : RO; bitpos: [2]; default: 0; 3314 * The masked status bit for the interrupt triggered when the timer 2 stops. 3315 */ 3316 #define MCPWM_TIMER2_STOP_INT_ST (BIT(2)) 3317 #define MCPWM_TIMER2_STOP_INT_ST_M (MCPWM_TIMER2_STOP_INT_ST_V << MCPWM_TIMER2_STOP_INT_ST_S) 3318 #define MCPWM_TIMER2_STOP_INT_ST_V 0x00000001U 3319 #define MCPWM_TIMER2_STOP_INT_ST_S 2 3320 /** MCPWM_TIMER0_TEZ_INT_ST : RO; bitpos: [3]; default: 0; 3321 * The masked status bit for the interrupt triggered by a PWM timer 0 TEZ event. 3322 */ 3323 #define MCPWM_TIMER0_TEZ_INT_ST (BIT(3)) 3324 #define MCPWM_TIMER0_TEZ_INT_ST_M (MCPWM_TIMER0_TEZ_INT_ST_V << MCPWM_TIMER0_TEZ_INT_ST_S) 3325 #define MCPWM_TIMER0_TEZ_INT_ST_V 0x00000001U 3326 #define MCPWM_TIMER0_TEZ_INT_ST_S 3 3327 /** MCPWM_TIMER1_TEZ_INT_ST : RO; bitpos: [4]; default: 0; 3328 * The masked status bit for the interrupt triggered by a PWM timer 1 TEZ event. 3329 */ 3330 #define MCPWM_TIMER1_TEZ_INT_ST (BIT(4)) 3331 #define MCPWM_TIMER1_TEZ_INT_ST_M (MCPWM_TIMER1_TEZ_INT_ST_V << MCPWM_TIMER1_TEZ_INT_ST_S) 3332 #define MCPWM_TIMER1_TEZ_INT_ST_V 0x00000001U 3333 #define MCPWM_TIMER1_TEZ_INT_ST_S 4 3334 /** MCPWM_TIMER2_TEZ_INT_ST : RO; bitpos: [5]; default: 0; 3335 * The masked status bit for the interrupt triggered by a PWM timer 2 TEZ event. 3336 */ 3337 #define MCPWM_TIMER2_TEZ_INT_ST (BIT(5)) 3338 #define MCPWM_TIMER2_TEZ_INT_ST_M (MCPWM_TIMER2_TEZ_INT_ST_V << MCPWM_TIMER2_TEZ_INT_ST_S) 3339 #define MCPWM_TIMER2_TEZ_INT_ST_V 0x00000001U 3340 #define MCPWM_TIMER2_TEZ_INT_ST_S 5 3341 /** MCPWM_TIMER0_TEP_INT_ST : RO; bitpos: [6]; default: 0; 3342 * The masked status bit for the interrupt triggered by a PWM timer 0 TEP event. 3343 */ 3344 #define MCPWM_TIMER0_TEP_INT_ST (BIT(6)) 3345 #define MCPWM_TIMER0_TEP_INT_ST_M (MCPWM_TIMER0_TEP_INT_ST_V << MCPWM_TIMER0_TEP_INT_ST_S) 3346 #define MCPWM_TIMER0_TEP_INT_ST_V 0x00000001U 3347 #define MCPWM_TIMER0_TEP_INT_ST_S 6 3348 /** MCPWM_TIMER1_TEP_INT_ST : RO; bitpos: [7]; default: 0; 3349 * The masked status bit for the interrupt triggered by a PWM timer 1 TEP event. 3350 */ 3351 #define MCPWM_TIMER1_TEP_INT_ST (BIT(7)) 3352 #define MCPWM_TIMER1_TEP_INT_ST_M (MCPWM_TIMER1_TEP_INT_ST_V << MCPWM_TIMER1_TEP_INT_ST_S) 3353 #define MCPWM_TIMER1_TEP_INT_ST_V 0x00000001U 3354 #define MCPWM_TIMER1_TEP_INT_ST_S 7 3355 /** MCPWM_TIMER2_TEP_INT_ST : RO; bitpos: [8]; default: 0; 3356 * The masked status bit for the interrupt triggered by a PWM timer 2 TEP event. 3357 */ 3358 #define MCPWM_TIMER2_TEP_INT_ST (BIT(8)) 3359 #define MCPWM_TIMER2_TEP_INT_ST_M (MCPWM_TIMER2_TEP_INT_ST_V << MCPWM_TIMER2_TEP_INT_ST_S) 3360 #define MCPWM_TIMER2_TEP_INT_ST_V 0x00000001U 3361 #define MCPWM_TIMER2_TEP_INT_ST_S 8 3362 /** MCPWM_FAULT0_INT_ST : RO; bitpos: [9]; default: 0; 3363 * The masked status bit for the interrupt triggered when event_f0 starts. 3364 */ 3365 #define MCPWM_FAULT0_INT_ST (BIT(9)) 3366 #define MCPWM_FAULT0_INT_ST_M (MCPWM_FAULT0_INT_ST_V << MCPWM_FAULT0_INT_ST_S) 3367 #define MCPWM_FAULT0_INT_ST_V 0x00000001U 3368 #define MCPWM_FAULT0_INT_ST_S 9 3369 /** MCPWM_FAULT1_INT_ST : RO; bitpos: [10]; default: 0; 3370 * The masked status bit for the interrupt triggered when event_f1 starts. 3371 */ 3372 #define MCPWM_FAULT1_INT_ST (BIT(10)) 3373 #define MCPWM_FAULT1_INT_ST_M (MCPWM_FAULT1_INT_ST_V << MCPWM_FAULT1_INT_ST_S) 3374 #define MCPWM_FAULT1_INT_ST_V 0x00000001U 3375 #define MCPWM_FAULT1_INT_ST_S 10 3376 /** MCPWM_FAULT2_INT_ST : RO; bitpos: [11]; default: 0; 3377 * The masked status bit for the interrupt triggered when event_f2 starts. 3378 */ 3379 #define MCPWM_FAULT2_INT_ST (BIT(11)) 3380 #define MCPWM_FAULT2_INT_ST_M (MCPWM_FAULT2_INT_ST_V << MCPWM_FAULT2_INT_ST_S) 3381 #define MCPWM_FAULT2_INT_ST_V 0x00000001U 3382 #define MCPWM_FAULT2_INT_ST_S 11 3383 /** MCPWM_FAULT0_CLR_INT_ST : RO; bitpos: [12]; default: 0; 3384 * The masked status bit for the interrupt triggered when event_f0 ends. 3385 */ 3386 #define MCPWM_FAULT0_CLR_INT_ST (BIT(12)) 3387 #define MCPWM_FAULT0_CLR_INT_ST_M (MCPWM_FAULT0_CLR_INT_ST_V << MCPWM_FAULT0_CLR_INT_ST_S) 3388 #define MCPWM_FAULT0_CLR_INT_ST_V 0x00000001U 3389 #define MCPWM_FAULT0_CLR_INT_ST_S 12 3390 /** MCPWM_FAULT1_CLR_INT_ST : RO; bitpos: [13]; default: 0; 3391 * The masked status bit for the interrupt triggered when event_f1 ends. 3392 */ 3393 #define MCPWM_FAULT1_CLR_INT_ST (BIT(13)) 3394 #define MCPWM_FAULT1_CLR_INT_ST_M (MCPWM_FAULT1_CLR_INT_ST_V << MCPWM_FAULT1_CLR_INT_ST_S) 3395 #define MCPWM_FAULT1_CLR_INT_ST_V 0x00000001U 3396 #define MCPWM_FAULT1_CLR_INT_ST_S 13 3397 /** MCPWM_FAULT2_CLR_INT_ST : RO; bitpos: [14]; default: 0; 3398 * The masked status bit for the interrupt triggered when event_f2 ends. 3399 */ 3400 #define MCPWM_FAULT2_CLR_INT_ST (BIT(14)) 3401 #define MCPWM_FAULT2_CLR_INT_ST_M (MCPWM_FAULT2_CLR_INT_ST_V << MCPWM_FAULT2_CLR_INT_ST_S) 3402 #define MCPWM_FAULT2_CLR_INT_ST_V 0x00000001U 3403 #define MCPWM_FAULT2_CLR_INT_ST_S 14 3404 /** MCPWM_CMPR0_TEA_INT_ST : RO; bitpos: [15]; default: 0; 3405 * The masked status bit for the interrupt triggered by a PWM operator 0 TEA event 3406 */ 3407 #define MCPWM_CMPR0_TEA_INT_ST (BIT(15)) 3408 #define MCPWM_CMPR0_TEA_INT_ST_M (MCPWM_CMPR0_TEA_INT_ST_V << MCPWM_CMPR0_TEA_INT_ST_S) 3409 #define MCPWM_CMPR0_TEA_INT_ST_V 0x00000001U 3410 #define MCPWM_CMPR0_TEA_INT_ST_S 15 3411 /** MCPWM_CMPR1_TEA_INT_ST : RO; bitpos: [16]; default: 0; 3412 * The masked status bit for the interrupt triggered by a PWM operator 1 TEA event 3413 */ 3414 #define MCPWM_CMPR1_TEA_INT_ST (BIT(16)) 3415 #define MCPWM_CMPR1_TEA_INT_ST_M (MCPWM_CMPR1_TEA_INT_ST_V << MCPWM_CMPR1_TEA_INT_ST_S) 3416 #define MCPWM_CMPR1_TEA_INT_ST_V 0x00000001U 3417 #define MCPWM_CMPR1_TEA_INT_ST_S 16 3418 /** MCPWM_CMPR2_TEA_INT_ST : RO; bitpos: [17]; default: 0; 3419 * The masked status bit for the interrupt triggered by a PWM operator 2 TEA event 3420 */ 3421 #define MCPWM_CMPR2_TEA_INT_ST (BIT(17)) 3422 #define MCPWM_CMPR2_TEA_INT_ST_M (MCPWM_CMPR2_TEA_INT_ST_V << MCPWM_CMPR2_TEA_INT_ST_S) 3423 #define MCPWM_CMPR2_TEA_INT_ST_V 0x00000001U 3424 #define MCPWM_CMPR2_TEA_INT_ST_S 17 3425 /** MCPWM_CMPR0_TEB_INT_ST : RO; bitpos: [18]; default: 0; 3426 * The masked status bit for the interrupt triggered by a PWM operator 0 TEB event 3427 */ 3428 #define MCPWM_CMPR0_TEB_INT_ST (BIT(18)) 3429 #define MCPWM_CMPR0_TEB_INT_ST_M (MCPWM_CMPR0_TEB_INT_ST_V << MCPWM_CMPR0_TEB_INT_ST_S) 3430 #define MCPWM_CMPR0_TEB_INT_ST_V 0x00000001U 3431 #define MCPWM_CMPR0_TEB_INT_ST_S 18 3432 /** MCPWM_CMPR1_TEB_INT_ST : RO; bitpos: [19]; default: 0; 3433 * The masked status bit for the interrupt triggered by a PWM operator 1 TEB event 3434 */ 3435 #define MCPWM_CMPR1_TEB_INT_ST (BIT(19)) 3436 #define MCPWM_CMPR1_TEB_INT_ST_M (MCPWM_CMPR1_TEB_INT_ST_V << MCPWM_CMPR1_TEB_INT_ST_S) 3437 #define MCPWM_CMPR1_TEB_INT_ST_V 0x00000001U 3438 #define MCPWM_CMPR1_TEB_INT_ST_S 19 3439 /** MCPWM_CMPR2_TEB_INT_ST : RO; bitpos: [20]; default: 0; 3440 * The masked status bit for the interrupt triggered by a PWM operator 2 TEB event 3441 */ 3442 #define MCPWM_CMPR2_TEB_INT_ST (BIT(20)) 3443 #define MCPWM_CMPR2_TEB_INT_ST_M (MCPWM_CMPR2_TEB_INT_ST_V << MCPWM_CMPR2_TEB_INT_ST_S) 3444 #define MCPWM_CMPR2_TEB_INT_ST_V 0x00000001U 3445 #define MCPWM_CMPR2_TEB_INT_ST_S 20 3446 /** MCPWM_TZ0_CBC_INT_ST : RO; bitpos: [21]; default: 0; 3447 * The masked status bit for the interrupt triggered by a cycle-by-cycle mode action 3448 * on PWM0. 3449 */ 3450 #define MCPWM_TZ0_CBC_INT_ST (BIT(21)) 3451 #define MCPWM_TZ0_CBC_INT_ST_M (MCPWM_TZ0_CBC_INT_ST_V << MCPWM_TZ0_CBC_INT_ST_S) 3452 #define MCPWM_TZ0_CBC_INT_ST_V 0x00000001U 3453 #define MCPWM_TZ0_CBC_INT_ST_S 21 3454 /** MCPWM_TZ1_CBC_INT_ST : RO; bitpos: [22]; default: 0; 3455 * The masked status bit for the interrupt triggered by a cycle-by-cycle mode action 3456 * on PWM1. 3457 */ 3458 #define MCPWM_TZ1_CBC_INT_ST (BIT(22)) 3459 #define MCPWM_TZ1_CBC_INT_ST_M (MCPWM_TZ1_CBC_INT_ST_V << MCPWM_TZ1_CBC_INT_ST_S) 3460 #define MCPWM_TZ1_CBC_INT_ST_V 0x00000001U 3461 #define MCPWM_TZ1_CBC_INT_ST_S 22 3462 /** MCPWM_TZ2_CBC_INT_ST : RO; bitpos: [23]; default: 0; 3463 * The masked status bit for the interrupt triggered by a cycle-by-cycle mode action 3464 * on PWM2. 3465 */ 3466 #define MCPWM_TZ2_CBC_INT_ST (BIT(23)) 3467 #define MCPWM_TZ2_CBC_INT_ST_M (MCPWM_TZ2_CBC_INT_ST_V << MCPWM_TZ2_CBC_INT_ST_S) 3468 #define MCPWM_TZ2_CBC_INT_ST_V 0x00000001U 3469 #define MCPWM_TZ2_CBC_INT_ST_S 23 3470 /** MCPWM_TZ0_OST_INT_ST : RO; bitpos: [24]; default: 0; 3471 * The masked status bit for the interrupt triggered by a one-shot mode action on PWM0. 3472 */ 3473 #define MCPWM_TZ0_OST_INT_ST (BIT(24)) 3474 #define MCPWM_TZ0_OST_INT_ST_M (MCPWM_TZ0_OST_INT_ST_V << MCPWM_TZ0_OST_INT_ST_S) 3475 #define MCPWM_TZ0_OST_INT_ST_V 0x00000001U 3476 #define MCPWM_TZ0_OST_INT_ST_S 24 3477 /** MCPWM_TZ1_OST_INT_ST : RO; bitpos: [25]; default: 0; 3478 * The masked status bit for the interrupt triggered by a one-shot mode action on PWM1. 3479 */ 3480 #define MCPWM_TZ1_OST_INT_ST (BIT(25)) 3481 #define MCPWM_TZ1_OST_INT_ST_M (MCPWM_TZ1_OST_INT_ST_V << MCPWM_TZ1_OST_INT_ST_S) 3482 #define MCPWM_TZ1_OST_INT_ST_V 0x00000001U 3483 #define MCPWM_TZ1_OST_INT_ST_S 25 3484 /** MCPWM_TZ2_OST_INT_ST : RO; bitpos: [26]; default: 0; 3485 * The masked status bit for the interrupt triggered by a one-shot mode action on PWM2. 3486 */ 3487 #define MCPWM_TZ2_OST_INT_ST (BIT(26)) 3488 #define MCPWM_TZ2_OST_INT_ST_M (MCPWM_TZ2_OST_INT_ST_V << MCPWM_TZ2_OST_INT_ST_S) 3489 #define MCPWM_TZ2_OST_INT_ST_V 0x00000001U 3490 #define MCPWM_TZ2_OST_INT_ST_S 26 3491 /** MCPWM_CAP0_INT_ST : RO; bitpos: [27]; default: 0; 3492 * The masked status bit for the interrupt triggered by capture on channel 0. 3493 */ 3494 #define MCPWM_CAP0_INT_ST (BIT(27)) 3495 #define MCPWM_CAP0_INT_ST_M (MCPWM_CAP0_INT_ST_V << MCPWM_CAP0_INT_ST_S) 3496 #define MCPWM_CAP0_INT_ST_V 0x00000001U 3497 #define MCPWM_CAP0_INT_ST_S 27 3498 /** MCPWM_CAP1_INT_ST : RO; bitpos: [28]; default: 0; 3499 * The masked status bit for the interrupt triggered by capture on channel 1. 3500 */ 3501 #define MCPWM_CAP1_INT_ST (BIT(28)) 3502 #define MCPWM_CAP1_INT_ST_M (MCPWM_CAP1_INT_ST_V << MCPWM_CAP1_INT_ST_S) 3503 #define MCPWM_CAP1_INT_ST_V 0x00000001U 3504 #define MCPWM_CAP1_INT_ST_S 28 3505 /** MCPWM_CAP2_INT_ST : RO; bitpos: [29]; default: 0; 3506 * The masked status bit for the interrupt triggered by capture on channel 2. 3507 */ 3508 #define MCPWM_CAP2_INT_ST (BIT(29)) 3509 #define MCPWM_CAP2_INT_ST_M (MCPWM_CAP2_INT_ST_V << MCPWM_CAP2_INT_ST_S) 3510 #define MCPWM_CAP2_INT_ST_V 0x00000001U 3511 #define MCPWM_CAP2_INT_ST_S 29 3512 3513 /** MCPWM_INT_CLR_REG register 3514 * Interrupt clear bits 3515 */ 3516 #define MCPWM_INT_CLR_REG(i) (REG_MCPWM_BASE(i) + 0x11c) 3517 /** MCPWM_TIMER0_STOP_INT_CLR : WT; bitpos: [0]; default: 0; 3518 * Set this bit to clear the interrupt triggered when the timer 0 stops. 3519 */ 3520 #define MCPWM_TIMER0_STOP_INT_CLR (BIT(0)) 3521 #define MCPWM_TIMER0_STOP_INT_CLR_M (MCPWM_TIMER0_STOP_INT_CLR_V << MCPWM_TIMER0_STOP_INT_CLR_S) 3522 #define MCPWM_TIMER0_STOP_INT_CLR_V 0x00000001U 3523 #define MCPWM_TIMER0_STOP_INT_CLR_S 0 3524 /** MCPWM_TIMER1_STOP_INT_CLR : WT; bitpos: [1]; default: 0; 3525 * Set this bit to clear the interrupt triggered when the timer 1 stops. 3526 */ 3527 #define MCPWM_TIMER1_STOP_INT_CLR (BIT(1)) 3528 #define MCPWM_TIMER1_STOP_INT_CLR_M (MCPWM_TIMER1_STOP_INT_CLR_V << MCPWM_TIMER1_STOP_INT_CLR_S) 3529 #define MCPWM_TIMER1_STOP_INT_CLR_V 0x00000001U 3530 #define MCPWM_TIMER1_STOP_INT_CLR_S 1 3531 /** MCPWM_TIMER2_STOP_INT_CLR : WT; bitpos: [2]; default: 0; 3532 * Set this bit to clear the interrupt triggered when the timer 2 stops. 3533 */ 3534 #define MCPWM_TIMER2_STOP_INT_CLR (BIT(2)) 3535 #define MCPWM_TIMER2_STOP_INT_CLR_M (MCPWM_TIMER2_STOP_INT_CLR_V << MCPWM_TIMER2_STOP_INT_CLR_S) 3536 #define MCPWM_TIMER2_STOP_INT_CLR_V 0x00000001U 3537 #define MCPWM_TIMER2_STOP_INT_CLR_S 2 3538 /** MCPWM_TIMER0_TEZ_INT_CLR : WT; bitpos: [3]; default: 0; 3539 * Set this bit to clear the interrupt triggered by a PWM timer 0 TEZ event. 3540 */ 3541 #define MCPWM_TIMER0_TEZ_INT_CLR (BIT(3)) 3542 #define MCPWM_TIMER0_TEZ_INT_CLR_M (MCPWM_TIMER0_TEZ_INT_CLR_V << MCPWM_TIMER0_TEZ_INT_CLR_S) 3543 #define MCPWM_TIMER0_TEZ_INT_CLR_V 0x00000001U 3544 #define MCPWM_TIMER0_TEZ_INT_CLR_S 3 3545 /** MCPWM_TIMER1_TEZ_INT_CLR : WT; bitpos: [4]; default: 0; 3546 * Set this bit to clear the interrupt triggered by a PWM timer 1 TEZ event. 3547 */ 3548 #define MCPWM_TIMER1_TEZ_INT_CLR (BIT(4)) 3549 #define MCPWM_TIMER1_TEZ_INT_CLR_M (MCPWM_TIMER1_TEZ_INT_CLR_V << MCPWM_TIMER1_TEZ_INT_CLR_S) 3550 #define MCPWM_TIMER1_TEZ_INT_CLR_V 0x00000001U 3551 #define MCPWM_TIMER1_TEZ_INT_CLR_S 4 3552 /** MCPWM_TIMER2_TEZ_INT_CLR : WT; bitpos: [5]; default: 0; 3553 * Set this bit to clear the interrupt triggered by a PWM timer 2 TEZ event. 3554 */ 3555 #define MCPWM_TIMER2_TEZ_INT_CLR (BIT(5)) 3556 #define MCPWM_TIMER2_TEZ_INT_CLR_M (MCPWM_TIMER2_TEZ_INT_CLR_V << MCPWM_TIMER2_TEZ_INT_CLR_S) 3557 #define MCPWM_TIMER2_TEZ_INT_CLR_V 0x00000001U 3558 #define MCPWM_TIMER2_TEZ_INT_CLR_S 5 3559 /** MCPWM_TIMER0_TEP_INT_CLR : WT; bitpos: [6]; default: 0; 3560 * Set this bit to clear the interrupt triggered by a PWM timer 0 TEP event. 3561 */ 3562 #define MCPWM_TIMER0_TEP_INT_CLR (BIT(6)) 3563 #define MCPWM_TIMER0_TEP_INT_CLR_M (MCPWM_TIMER0_TEP_INT_CLR_V << MCPWM_TIMER0_TEP_INT_CLR_S) 3564 #define MCPWM_TIMER0_TEP_INT_CLR_V 0x00000001U 3565 #define MCPWM_TIMER0_TEP_INT_CLR_S 6 3566 /** MCPWM_TIMER1_TEP_INT_CLR : WT; bitpos: [7]; default: 0; 3567 * Set this bit to clear the interrupt triggered by a PWM timer 1 TEP event. 3568 */ 3569 #define MCPWM_TIMER1_TEP_INT_CLR (BIT(7)) 3570 #define MCPWM_TIMER1_TEP_INT_CLR_M (MCPWM_TIMER1_TEP_INT_CLR_V << MCPWM_TIMER1_TEP_INT_CLR_S) 3571 #define MCPWM_TIMER1_TEP_INT_CLR_V 0x00000001U 3572 #define MCPWM_TIMER1_TEP_INT_CLR_S 7 3573 /** MCPWM_TIMER2_TEP_INT_CLR : WT; bitpos: [8]; default: 0; 3574 * Set this bit to clear the interrupt triggered by a PWM timer 2 TEP event. 3575 */ 3576 #define MCPWM_TIMER2_TEP_INT_CLR (BIT(8)) 3577 #define MCPWM_TIMER2_TEP_INT_CLR_M (MCPWM_TIMER2_TEP_INT_CLR_V << MCPWM_TIMER2_TEP_INT_CLR_S) 3578 #define MCPWM_TIMER2_TEP_INT_CLR_V 0x00000001U 3579 #define MCPWM_TIMER2_TEP_INT_CLR_S 8 3580 /** MCPWM_FAULT0_INT_CLR : WT; bitpos: [9]; default: 0; 3581 * Set this bit to clear the interrupt triggered when event_f0 starts. 3582 */ 3583 #define MCPWM_FAULT0_INT_CLR (BIT(9)) 3584 #define MCPWM_FAULT0_INT_CLR_M (MCPWM_FAULT0_INT_CLR_V << MCPWM_FAULT0_INT_CLR_S) 3585 #define MCPWM_FAULT0_INT_CLR_V 0x00000001U 3586 #define MCPWM_FAULT0_INT_CLR_S 9 3587 /** MCPWM_FAULT1_INT_CLR : WT; bitpos: [10]; default: 0; 3588 * Set this bit to clear the interrupt triggered when event_f1 starts. 3589 */ 3590 #define MCPWM_FAULT1_INT_CLR (BIT(10)) 3591 #define MCPWM_FAULT1_INT_CLR_M (MCPWM_FAULT1_INT_CLR_V << MCPWM_FAULT1_INT_CLR_S) 3592 #define MCPWM_FAULT1_INT_CLR_V 0x00000001U 3593 #define MCPWM_FAULT1_INT_CLR_S 10 3594 /** MCPWM_FAULT2_INT_CLR : WT; bitpos: [11]; default: 0; 3595 * Set this bit to clear the interrupt triggered when event_f2 starts. 3596 */ 3597 #define MCPWM_FAULT2_INT_CLR (BIT(11)) 3598 #define MCPWM_FAULT2_INT_CLR_M (MCPWM_FAULT2_INT_CLR_V << MCPWM_FAULT2_INT_CLR_S) 3599 #define MCPWM_FAULT2_INT_CLR_V 0x00000001U 3600 #define MCPWM_FAULT2_INT_CLR_S 11 3601 /** MCPWM_FAULT0_CLR_INT_CLR : WT; bitpos: [12]; default: 0; 3602 * Set this bit to clear the interrupt triggered when event_f0 ends. 3603 */ 3604 #define MCPWM_FAULT0_CLR_INT_CLR (BIT(12)) 3605 #define MCPWM_FAULT0_CLR_INT_CLR_M (MCPWM_FAULT0_CLR_INT_CLR_V << MCPWM_FAULT0_CLR_INT_CLR_S) 3606 #define MCPWM_FAULT0_CLR_INT_CLR_V 0x00000001U 3607 #define MCPWM_FAULT0_CLR_INT_CLR_S 12 3608 /** MCPWM_FAULT1_CLR_INT_CLR : WT; bitpos: [13]; default: 0; 3609 * Set this bit to clear the interrupt triggered when event_f1 ends. 3610 */ 3611 #define MCPWM_FAULT1_CLR_INT_CLR (BIT(13)) 3612 #define MCPWM_FAULT1_CLR_INT_CLR_M (MCPWM_FAULT1_CLR_INT_CLR_V << MCPWM_FAULT1_CLR_INT_CLR_S) 3613 #define MCPWM_FAULT1_CLR_INT_CLR_V 0x00000001U 3614 #define MCPWM_FAULT1_CLR_INT_CLR_S 13 3615 /** MCPWM_FAULT2_CLR_INT_CLR : WT; bitpos: [14]; default: 0; 3616 * Set this bit to clear the interrupt triggered when event_f2 ends. 3617 */ 3618 #define MCPWM_FAULT2_CLR_INT_CLR (BIT(14)) 3619 #define MCPWM_FAULT2_CLR_INT_CLR_M (MCPWM_FAULT2_CLR_INT_CLR_V << MCPWM_FAULT2_CLR_INT_CLR_S) 3620 #define MCPWM_FAULT2_CLR_INT_CLR_V 0x00000001U 3621 #define MCPWM_FAULT2_CLR_INT_CLR_S 14 3622 /** MCPWM_CMPR0_TEA_INT_CLR : WT; bitpos: [15]; default: 0; 3623 * Set this bit to clear the interrupt triggered by a PWM operator 0 TEA event 3624 */ 3625 #define MCPWM_CMPR0_TEA_INT_CLR (BIT(15)) 3626 #define MCPWM_CMPR0_TEA_INT_CLR_M (MCPWM_CMPR0_TEA_INT_CLR_V << MCPWM_CMPR0_TEA_INT_CLR_S) 3627 #define MCPWM_CMPR0_TEA_INT_CLR_V 0x00000001U 3628 #define MCPWM_CMPR0_TEA_INT_CLR_S 15 3629 /** MCPWM_CMPR1_TEA_INT_CLR : WT; bitpos: [16]; default: 0; 3630 * Set this bit to clear the interrupt triggered by a PWM operator 1 TEA event 3631 */ 3632 #define MCPWM_CMPR1_TEA_INT_CLR (BIT(16)) 3633 #define MCPWM_CMPR1_TEA_INT_CLR_M (MCPWM_CMPR1_TEA_INT_CLR_V << MCPWM_CMPR1_TEA_INT_CLR_S) 3634 #define MCPWM_CMPR1_TEA_INT_CLR_V 0x00000001U 3635 #define MCPWM_CMPR1_TEA_INT_CLR_S 16 3636 /** MCPWM_CMPR2_TEA_INT_CLR : WT; bitpos: [17]; default: 0; 3637 * Set this bit to clear the interrupt triggered by a PWM operator 2 TEA event 3638 */ 3639 #define MCPWM_CMPR2_TEA_INT_CLR (BIT(17)) 3640 #define MCPWM_CMPR2_TEA_INT_CLR_M (MCPWM_CMPR2_TEA_INT_CLR_V << MCPWM_CMPR2_TEA_INT_CLR_S) 3641 #define MCPWM_CMPR2_TEA_INT_CLR_V 0x00000001U 3642 #define MCPWM_CMPR2_TEA_INT_CLR_S 17 3643 /** MCPWM_CMPR0_TEB_INT_CLR : WT; bitpos: [18]; default: 0; 3644 * Set this bit to clear the interrupt triggered by a PWM operator 0 TEB event 3645 */ 3646 #define MCPWM_CMPR0_TEB_INT_CLR (BIT(18)) 3647 #define MCPWM_CMPR0_TEB_INT_CLR_M (MCPWM_CMPR0_TEB_INT_CLR_V << MCPWM_CMPR0_TEB_INT_CLR_S) 3648 #define MCPWM_CMPR0_TEB_INT_CLR_V 0x00000001U 3649 #define MCPWM_CMPR0_TEB_INT_CLR_S 18 3650 /** MCPWM_CMPR1_TEB_INT_CLR : WT; bitpos: [19]; default: 0; 3651 * Set this bit to clear the interrupt triggered by a PWM operator 1 TEB event 3652 */ 3653 #define MCPWM_CMPR1_TEB_INT_CLR (BIT(19)) 3654 #define MCPWM_CMPR1_TEB_INT_CLR_M (MCPWM_CMPR1_TEB_INT_CLR_V << MCPWM_CMPR1_TEB_INT_CLR_S) 3655 #define MCPWM_CMPR1_TEB_INT_CLR_V 0x00000001U 3656 #define MCPWM_CMPR1_TEB_INT_CLR_S 19 3657 /** MCPWM_CMPR2_TEB_INT_CLR : WT; bitpos: [20]; default: 0; 3658 * Set this bit to clear the interrupt triggered by a PWM operator 2 TEB event 3659 */ 3660 #define MCPWM_CMPR2_TEB_INT_CLR (BIT(20)) 3661 #define MCPWM_CMPR2_TEB_INT_CLR_M (MCPWM_CMPR2_TEB_INT_CLR_V << MCPWM_CMPR2_TEB_INT_CLR_S) 3662 #define MCPWM_CMPR2_TEB_INT_CLR_V 0x00000001U 3663 #define MCPWM_CMPR2_TEB_INT_CLR_S 20 3664 /** MCPWM_TZ0_CBC_INT_CLR : WT; bitpos: [21]; default: 0; 3665 * Set this bit to clear the interrupt triggered by a cycle-by-cycle mode action on 3666 * PWM0. 3667 */ 3668 #define MCPWM_TZ0_CBC_INT_CLR (BIT(21)) 3669 #define MCPWM_TZ0_CBC_INT_CLR_M (MCPWM_TZ0_CBC_INT_CLR_V << MCPWM_TZ0_CBC_INT_CLR_S) 3670 #define MCPWM_TZ0_CBC_INT_CLR_V 0x00000001U 3671 #define MCPWM_TZ0_CBC_INT_CLR_S 21 3672 /** MCPWM_TZ1_CBC_INT_CLR : WT; bitpos: [22]; default: 0; 3673 * Set this bit to clear the interrupt triggered by a cycle-by-cycle mode action on 3674 * PWM1. 3675 */ 3676 #define MCPWM_TZ1_CBC_INT_CLR (BIT(22)) 3677 #define MCPWM_TZ1_CBC_INT_CLR_M (MCPWM_TZ1_CBC_INT_CLR_V << MCPWM_TZ1_CBC_INT_CLR_S) 3678 #define MCPWM_TZ1_CBC_INT_CLR_V 0x00000001U 3679 #define MCPWM_TZ1_CBC_INT_CLR_S 22 3680 /** MCPWM_TZ2_CBC_INT_CLR : WT; bitpos: [23]; default: 0; 3681 * Set this bit to clear the interrupt triggered by a cycle-by-cycle mode action on 3682 * PWM2. 3683 */ 3684 #define MCPWM_TZ2_CBC_INT_CLR (BIT(23)) 3685 #define MCPWM_TZ2_CBC_INT_CLR_M (MCPWM_TZ2_CBC_INT_CLR_V << MCPWM_TZ2_CBC_INT_CLR_S) 3686 #define MCPWM_TZ2_CBC_INT_CLR_V 0x00000001U 3687 #define MCPWM_TZ2_CBC_INT_CLR_S 23 3688 /** MCPWM_TZ0_OST_INT_CLR : WT; bitpos: [24]; default: 0; 3689 * Set this bit to clear the interrupt triggered by a one-shot mode action on PWM0. 3690 */ 3691 #define MCPWM_TZ0_OST_INT_CLR (BIT(24)) 3692 #define MCPWM_TZ0_OST_INT_CLR_M (MCPWM_TZ0_OST_INT_CLR_V << MCPWM_TZ0_OST_INT_CLR_S) 3693 #define MCPWM_TZ0_OST_INT_CLR_V 0x00000001U 3694 #define MCPWM_TZ0_OST_INT_CLR_S 24 3695 /** MCPWM_TZ1_OST_INT_CLR : WT; bitpos: [25]; default: 0; 3696 * Set this bit to clear the interrupt triggered by a one-shot mode action on PWM1. 3697 */ 3698 #define MCPWM_TZ1_OST_INT_CLR (BIT(25)) 3699 #define MCPWM_TZ1_OST_INT_CLR_M (MCPWM_TZ1_OST_INT_CLR_V << MCPWM_TZ1_OST_INT_CLR_S) 3700 #define MCPWM_TZ1_OST_INT_CLR_V 0x00000001U 3701 #define MCPWM_TZ1_OST_INT_CLR_S 25 3702 /** MCPWM_TZ2_OST_INT_CLR : WT; bitpos: [26]; default: 0; 3703 * Set this bit to clear the interrupt triggered by a one-shot mode action on PWM2. 3704 */ 3705 #define MCPWM_TZ2_OST_INT_CLR (BIT(26)) 3706 #define MCPWM_TZ2_OST_INT_CLR_M (MCPWM_TZ2_OST_INT_CLR_V << MCPWM_TZ2_OST_INT_CLR_S) 3707 #define MCPWM_TZ2_OST_INT_CLR_V 0x00000001U 3708 #define MCPWM_TZ2_OST_INT_CLR_S 26 3709 /** MCPWM_CAP0_INT_CLR : WT; bitpos: [27]; default: 0; 3710 * Set this bit to clear the interrupt triggered by capture on channel 0. 3711 */ 3712 #define MCPWM_CAP0_INT_CLR (BIT(27)) 3713 #define MCPWM_CAP0_INT_CLR_M (MCPWM_CAP0_INT_CLR_V << MCPWM_CAP0_INT_CLR_S) 3714 #define MCPWM_CAP0_INT_CLR_V 0x00000001U 3715 #define MCPWM_CAP0_INT_CLR_S 27 3716 /** MCPWM_CAP1_INT_CLR : WT; bitpos: [28]; default: 0; 3717 * Set this bit to clear the interrupt triggered by capture on channel 1. 3718 */ 3719 #define MCPWM_CAP1_INT_CLR (BIT(28)) 3720 #define MCPWM_CAP1_INT_CLR_M (MCPWM_CAP1_INT_CLR_V << MCPWM_CAP1_INT_CLR_S) 3721 #define MCPWM_CAP1_INT_CLR_V 0x00000001U 3722 #define MCPWM_CAP1_INT_CLR_S 28 3723 /** MCPWM_CAP2_INT_CLR : WT; bitpos: [29]; default: 0; 3724 * Set this bit to clear the interrupt triggered by capture on channel 2. 3725 */ 3726 #define MCPWM_CAP2_INT_CLR (BIT(29)) 3727 #define MCPWM_CAP2_INT_CLR_M (MCPWM_CAP2_INT_CLR_V << MCPWM_CAP2_INT_CLR_S) 3728 #define MCPWM_CAP2_INT_CLR_V 0x00000001U 3729 #define MCPWM_CAP2_INT_CLR_S 29 3730 3731 /** MCPWM_EVT_EN_REG register 3732 * MCPWM event enable register 3733 */ 3734 #define MCPWM_EVT_EN_REG(i) (REG_MCPWM_BASE(i) + 0x120) 3735 /** MCPWM_EVT_TIMER0_STOP_EN : R/W; bitpos: [0]; default: 0; 3736 * set this bit high to enable timer0 stop event generate 3737 */ 3738 #define MCPWM_EVT_TIMER0_STOP_EN (BIT(0)) 3739 #define MCPWM_EVT_TIMER0_STOP_EN_M (MCPWM_EVT_TIMER0_STOP_EN_V << MCPWM_EVT_TIMER0_STOP_EN_S) 3740 #define MCPWM_EVT_TIMER0_STOP_EN_V 0x00000001U 3741 #define MCPWM_EVT_TIMER0_STOP_EN_S 0 3742 /** MCPWM_EVT_TIMER1_STOP_EN : R/W; bitpos: [1]; default: 0; 3743 * set this bit high to enable timer1 stop event generate 3744 */ 3745 #define MCPWM_EVT_TIMER1_STOP_EN (BIT(1)) 3746 #define MCPWM_EVT_TIMER1_STOP_EN_M (MCPWM_EVT_TIMER1_STOP_EN_V << MCPWM_EVT_TIMER1_STOP_EN_S) 3747 #define MCPWM_EVT_TIMER1_STOP_EN_V 0x00000001U 3748 #define MCPWM_EVT_TIMER1_STOP_EN_S 1 3749 /** MCPWM_EVT_TIMER2_STOP_EN : R/W; bitpos: [2]; default: 0; 3750 * set this bit high to enable timer2 stop event generate 3751 */ 3752 #define MCPWM_EVT_TIMER2_STOP_EN (BIT(2)) 3753 #define MCPWM_EVT_TIMER2_STOP_EN_M (MCPWM_EVT_TIMER2_STOP_EN_V << MCPWM_EVT_TIMER2_STOP_EN_S) 3754 #define MCPWM_EVT_TIMER2_STOP_EN_V 0x00000001U 3755 #define MCPWM_EVT_TIMER2_STOP_EN_S 2 3756 /** MCPWM_EVT_TIMER0_TEZ_EN : R/W; bitpos: [3]; default: 0; 3757 * set this bit high to enable timer0 equal zero event generate 3758 */ 3759 #define MCPWM_EVT_TIMER0_TEZ_EN (BIT(3)) 3760 #define MCPWM_EVT_TIMER0_TEZ_EN_M (MCPWM_EVT_TIMER0_TEZ_EN_V << MCPWM_EVT_TIMER0_TEZ_EN_S) 3761 #define MCPWM_EVT_TIMER0_TEZ_EN_V 0x00000001U 3762 #define MCPWM_EVT_TIMER0_TEZ_EN_S 3 3763 /** MCPWM_EVT_TIMER1_TEZ_EN : R/W; bitpos: [4]; default: 0; 3764 * set this bit high to enable timer1 equal zero event generate 3765 */ 3766 #define MCPWM_EVT_TIMER1_TEZ_EN (BIT(4)) 3767 #define MCPWM_EVT_TIMER1_TEZ_EN_M (MCPWM_EVT_TIMER1_TEZ_EN_V << MCPWM_EVT_TIMER1_TEZ_EN_S) 3768 #define MCPWM_EVT_TIMER1_TEZ_EN_V 0x00000001U 3769 #define MCPWM_EVT_TIMER1_TEZ_EN_S 4 3770 /** MCPWM_EVT_TIMER2_TEZ_EN : R/W; bitpos: [5]; default: 0; 3771 * set this bit high to enable timer2 equal zero event generate 3772 */ 3773 #define MCPWM_EVT_TIMER2_TEZ_EN (BIT(5)) 3774 #define MCPWM_EVT_TIMER2_TEZ_EN_M (MCPWM_EVT_TIMER2_TEZ_EN_V << MCPWM_EVT_TIMER2_TEZ_EN_S) 3775 #define MCPWM_EVT_TIMER2_TEZ_EN_V 0x00000001U 3776 #define MCPWM_EVT_TIMER2_TEZ_EN_S 5 3777 /** MCPWM_EVT_TIMER0_TEP_EN : R/W; bitpos: [6]; default: 0; 3778 * set this bit high to enable timer0 equal period event generate 3779 */ 3780 #define MCPWM_EVT_TIMER0_TEP_EN (BIT(6)) 3781 #define MCPWM_EVT_TIMER0_TEP_EN_M (MCPWM_EVT_TIMER0_TEP_EN_V << MCPWM_EVT_TIMER0_TEP_EN_S) 3782 #define MCPWM_EVT_TIMER0_TEP_EN_V 0x00000001U 3783 #define MCPWM_EVT_TIMER0_TEP_EN_S 6 3784 /** MCPWM_EVT_TIMER1_TEP_EN : R/W; bitpos: [7]; default: 0; 3785 * set this bit high to enable timer1 equal period event generate 3786 */ 3787 #define MCPWM_EVT_TIMER1_TEP_EN (BIT(7)) 3788 #define MCPWM_EVT_TIMER1_TEP_EN_M (MCPWM_EVT_TIMER1_TEP_EN_V << MCPWM_EVT_TIMER1_TEP_EN_S) 3789 #define MCPWM_EVT_TIMER1_TEP_EN_V 0x00000001U 3790 #define MCPWM_EVT_TIMER1_TEP_EN_S 7 3791 /** MCPWM_EVT_TIMER2_TEP_EN : R/W; bitpos: [8]; default: 0; 3792 * set this bit high to enable timer2 equal period event generate 3793 */ 3794 #define MCPWM_EVT_TIMER2_TEP_EN (BIT(8)) 3795 #define MCPWM_EVT_TIMER2_TEP_EN_M (MCPWM_EVT_TIMER2_TEP_EN_V << MCPWM_EVT_TIMER2_TEP_EN_S) 3796 #define MCPWM_EVT_TIMER2_TEP_EN_V 0x00000001U 3797 #define MCPWM_EVT_TIMER2_TEP_EN_S 8 3798 /** MCPWM_EVT_OP0_TEA_EN : R/W; bitpos: [9]; default: 0; 3799 * set this bit high to enable PWM generator0 timer equal a event generate 3800 */ 3801 #define MCPWM_EVT_OP0_TEA_EN (BIT(9)) 3802 #define MCPWM_EVT_OP0_TEA_EN_M (MCPWM_EVT_OP0_TEA_EN_V << MCPWM_EVT_OP0_TEA_EN_S) 3803 #define MCPWM_EVT_OP0_TEA_EN_V 0x00000001U 3804 #define MCPWM_EVT_OP0_TEA_EN_S 9 3805 /** MCPWM_EVT_OP1_TEA_EN : R/W; bitpos: [10]; default: 0; 3806 * set this bit high to enable PWM generator1 timer equal a event generate 3807 */ 3808 #define MCPWM_EVT_OP1_TEA_EN (BIT(10)) 3809 #define MCPWM_EVT_OP1_TEA_EN_M (MCPWM_EVT_OP1_TEA_EN_V << MCPWM_EVT_OP1_TEA_EN_S) 3810 #define MCPWM_EVT_OP1_TEA_EN_V 0x00000001U 3811 #define MCPWM_EVT_OP1_TEA_EN_S 10 3812 /** MCPWM_EVT_OP2_TEA_EN : R/W; bitpos: [11]; default: 0; 3813 * set this bit high to enable PWM generator2 timer equal a event generate 3814 */ 3815 #define MCPWM_EVT_OP2_TEA_EN (BIT(11)) 3816 #define MCPWM_EVT_OP2_TEA_EN_M (MCPWM_EVT_OP2_TEA_EN_V << MCPWM_EVT_OP2_TEA_EN_S) 3817 #define MCPWM_EVT_OP2_TEA_EN_V 0x00000001U 3818 #define MCPWM_EVT_OP2_TEA_EN_S 11 3819 /** MCPWM_EVT_OP0_TEB_EN : R/W; bitpos: [12]; default: 0; 3820 * set this bit high to enable PWM generator0 timer equal b event generate 3821 */ 3822 #define MCPWM_EVT_OP0_TEB_EN (BIT(12)) 3823 #define MCPWM_EVT_OP0_TEB_EN_M (MCPWM_EVT_OP0_TEB_EN_V << MCPWM_EVT_OP0_TEB_EN_S) 3824 #define MCPWM_EVT_OP0_TEB_EN_V 0x00000001U 3825 #define MCPWM_EVT_OP0_TEB_EN_S 12 3826 /** MCPWM_EVT_OP1_TEB_EN : R/W; bitpos: [13]; default: 0; 3827 * set this bit high to enable PWM generator1 timer equal b event generate 3828 */ 3829 #define MCPWM_EVT_OP1_TEB_EN (BIT(13)) 3830 #define MCPWM_EVT_OP1_TEB_EN_M (MCPWM_EVT_OP1_TEB_EN_V << MCPWM_EVT_OP1_TEB_EN_S) 3831 #define MCPWM_EVT_OP1_TEB_EN_V 0x00000001U 3832 #define MCPWM_EVT_OP1_TEB_EN_S 13 3833 /** MCPWM_EVT_OP2_TEB_EN : R/W; bitpos: [14]; default: 0; 3834 * set this bit high to enable PWM generator2 timer equal b event generate 3835 */ 3836 #define MCPWM_EVT_OP2_TEB_EN (BIT(14)) 3837 #define MCPWM_EVT_OP2_TEB_EN_M (MCPWM_EVT_OP2_TEB_EN_V << MCPWM_EVT_OP2_TEB_EN_S) 3838 #define MCPWM_EVT_OP2_TEB_EN_V 0x00000001U 3839 #define MCPWM_EVT_OP2_TEB_EN_S 14 3840 /** MCPWM_EVT_F0_EN : R/W; bitpos: [15]; default: 0; 3841 * set this bit high to enable fault0 event generate 3842 */ 3843 #define MCPWM_EVT_F0_EN (BIT(15)) 3844 #define MCPWM_EVT_F0_EN_M (MCPWM_EVT_F0_EN_V << MCPWM_EVT_F0_EN_S) 3845 #define MCPWM_EVT_F0_EN_V 0x00000001U 3846 #define MCPWM_EVT_F0_EN_S 15 3847 /** MCPWM_EVT_F1_EN : R/W; bitpos: [16]; default: 0; 3848 * set this bit high to enable fault1 event generate 3849 */ 3850 #define MCPWM_EVT_F1_EN (BIT(16)) 3851 #define MCPWM_EVT_F1_EN_M (MCPWM_EVT_F1_EN_V << MCPWM_EVT_F1_EN_S) 3852 #define MCPWM_EVT_F1_EN_V 0x00000001U 3853 #define MCPWM_EVT_F1_EN_S 16 3854 /** MCPWM_EVT_F2_EN : R/W; bitpos: [17]; default: 0; 3855 * set this bit high to enable fault2 event generate 3856 */ 3857 #define MCPWM_EVT_F2_EN (BIT(17)) 3858 #define MCPWM_EVT_F2_EN_M (MCPWM_EVT_F2_EN_V << MCPWM_EVT_F2_EN_S) 3859 #define MCPWM_EVT_F2_EN_V 0x00000001U 3860 #define MCPWM_EVT_F2_EN_S 17 3861 /** MCPWM_EVT_F0_CLR_EN : R/W; bitpos: [18]; default: 0; 3862 * set this bit high to enable fault0 clear event generate 3863 */ 3864 #define MCPWM_EVT_F0_CLR_EN (BIT(18)) 3865 #define MCPWM_EVT_F0_CLR_EN_M (MCPWM_EVT_F0_CLR_EN_V << MCPWM_EVT_F0_CLR_EN_S) 3866 #define MCPWM_EVT_F0_CLR_EN_V 0x00000001U 3867 #define MCPWM_EVT_F0_CLR_EN_S 18 3868 /** MCPWM_EVT_F1_CLR_EN : R/W; bitpos: [19]; default: 0; 3869 * set this bit high to enable fault1 clear event generate 3870 */ 3871 #define MCPWM_EVT_F1_CLR_EN (BIT(19)) 3872 #define MCPWM_EVT_F1_CLR_EN_M (MCPWM_EVT_F1_CLR_EN_V << MCPWM_EVT_F1_CLR_EN_S) 3873 #define MCPWM_EVT_F1_CLR_EN_V 0x00000001U 3874 #define MCPWM_EVT_F1_CLR_EN_S 19 3875 /** MCPWM_EVT_F2_CLR_EN : R/W; bitpos: [20]; default: 0; 3876 * set this bit high to enable fault2 clear event generate 3877 */ 3878 #define MCPWM_EVT_F2_CLR_EN (BIT(20)) 3879 #define MCPWM_EVT_F2_CLR_EN_M (MCPWM_EVT_F2_CLR_EN_V << MCPWM_EVT_F2_CLR_EN_S) 3880 #define MCPWM_EVT_F2_CLR_EN_V 0x00000001U 3881 #define MCPWM_EVT_F2_CLR_EN_S 20 3882 /** MCPWM_EVT_TZ0_CBC_EN : R/W; bitpos: [21]; default: 0; 3883 * set this bit high to enable cycle by cycle trip0 event generate 3884 */ 3885 #define MCPWM_EVT_TZ0_CBC_EN (BIT(21)) 3886 #define MCPWM_EVT_TZ0_CBC_EN_M (MCPWM_EVT_TZ0_CBC_EN_V << MCPWM_EVT_TZ0_CBC_EN_S) 3887 #define MCPWM_EVT_TZ0_CBC_EN_V 0x00000001U 3888 #define MCPWM_EVT_TZ0_CBC_EN_S 21 3889 /** MCPWM_EVT_TZ1_CBC_EN : R/W; bitpos: [22]; default: 0; 3890 * set this bit high to enable cycle by cycle trip1 event generate 3891 */ 3892 #define MCPWM_EVT_TZ1_CBC_EN (BIT(22)) 3893 #define MCPWM_EVT_TZ1_CBC_EN_M (MCPWM_EVT_TZ1_CBC_EN_V << MCPWM_EVT_TZ1_CBC_EN_S) 3894 #define MCPWM_EVT_TZ1_CBC_EN_V 0x00000001U 3895 #define MCPWM_EVT_TZ1_CBC_EN_S 22 3896 /** MCPWM_EVT_TZ2_CBC_EN : R/W; bitpos: [23]; default: 0; 3897 * set this bit high to enable cycle by cycle trip2 event generate 3898 */ 3899 #define MCPWM_EVT_TZ2_CBC_EN (BIT(23)) 3900 #define MCPWM_EVT_TZ2_CBC_EN_M (MCPWM_EVT_TZ2_CBC_EN_V << MCPWM_EVT_TZ2_CBC_EN_S) 3901 #define MCPWM_EVT_TZ2_CBC_EN_V 0x00000001U 3902 #define MCPWM_EVT_TZ2_CBC_EN_S 23 3903 /** MCPWM_EVT_TZ0_OST_EN : R/W; bitpos: [24]; default: 0; 3904 * set this bit high to enable one shot trip0 event generate 3905 */ 3906 #define MCPWM_EVT_TZ0_OST_EN (BIT(24)) 3907 #define MCPWM_EVT_TZ0_OST_EN_M (MCPWM_EVT_TZ0_OST_EN_V << MCPWM_EVT_TZ0_OST_EN_S) 3908 #define MCPWM_EVT_TZ0_OST_EN_V 0x00000001U 3909 #define MCPWM_EVT_TZ0_OST_EN_S 24 3910 /** MCPWM_EVT_TZ1_OST_EN : R/W; bitpos: [25]; default: 0; 3911 * set this bit high to enable one shot trip1 event generate 3912 */ 3913 #define MCPWM_EVT_TZ1_OST_EN (BIT(25)) 3914 #define MCPWM_EVT_TZ1_OST_EN_M (MCPWM_EVT_TZ1_OST_EN_V << MCPWM_EVT_TZ1_OST_EN_S) 3915 #define MCPWM_EVT_TZ1_OST_EN_V 0x00000001U 3916 #define MCPWM_EVT_TZ1_OST_EN_S 25 3917 /** MCPWM_EVT_TZ2_OST_EN : R/W; bitpos: [26]; default: 0; 3918 * set this bit high to enable one shot trip2 event generate 3919 */ 3920 #define MCPWM_EVT_TZ2_OST_EN (BIT(26)) 3921 #define MCPWM_EVT_TZ2_OST_EN_M (MCPWM_EVT_TZ2_OST_EN_V << MCPWM_EVT_TZ2_OST_EN_S) 3922 #define MCPWM_EVT_TZ2_OST_EN_V 0x00000001U 3923 #define MCPWM_EVT_TZ2_OST_EN_S 26 3924 /** MCPWM_EVT_CAP0_EN : R/W; bitpos: [27]; default: 0; 3925 * set this bit high to enable capture0 event generate 3926 */ 3927 #define MCPWM_EVT_CAP0_EN (BIT(27)) 3928 #define MCPWM_EVT_CAP0_EN_M (MCPWM_EVT_CAP0_EN_V << MCPWM_EVT_CAP0_EN_S) 3929 #define MCPWM_EVT_CAP0_EN_V 0x00000001U 3930 #define MCPWM_EVT_CAP0_EN_S 27 3931 /** MCPWM_EVT_CAP1_EN : R/W; bitpos: [28]; default: 0; 3932 * set this bit high to enable capture1 event generate 3933 */ 3934 #define MCPWM_EVT_CAP1_EN (BIT(28)) 3935 #define MCPWM_EVT_CAP1_EN_M (MCPWM_EVT_CAP1_EN_V << MCPWM_EVT_CAP1_EN_S) 3936 #define MCPWM_EVT_CAP1_EN_V 0x00000001U 3937 #define MCPWM_EVT_CAP1_EN_S 28 3938 /** MCPWM_EVT_CAP2_EN : R/W; bitpos: [29]; default: 0; 3939 * set this bit high to enable capture2 event generate 3940 */ 3941 #define MCPWM_EVT_CAP2_EN (BIT(29)) 3942 #define MCPWM_EVT_CAP2_EN_M (MCPWM_EVT_CAP2_EN_V << MCPWM_EVT_CAP2_EN_S) 3943 #define MCPWM_EVT_CAP2_EN_V 0x00000001U 3944 #define MCPWM_EVT_CAP2_EN_S 29 3945 3946 /** MCPWM_TASK_EN_REG register 3947 * MCPWM task enable register 3948 */ 3949 #define MCPWM_TASK_EN_REG(i) (REG_MCPWM_BASE(i) + 0x124) 3950 /** MCPWM_TASK_CMPR0_A_UP_EN : R/W; bitpos: [0]; default: 0; 3951 * set this bit high to enable PWM generator0 timer stamp A's shadow register update 3952 * task receive 3953 */ 3954 #define MCPWM_TASK_CMPR0_A_UP_EN (BIT(0)) 3955 #define MCPWM_TASK_CMPR0_A_UP_EN_M (MCPWM_TASK_CMPR0_A_UP_EN_V << MCPWM_TASK_CMPR0_A_UP_EN_S) 3956 #define MCPWM_TASK_CMPR0_A_UP_EN_V 0x00000001U 3957 #define MCPWM_TASK_CMPR0_A_UP_EN_S 0 3958 /** MCPWM_TASK_CMPR1_A_UP_EN : R/W; bitpos: [1]; default: 0; 3959 * set this bit high to enable PWM generator1 timer stamp A's shadow register update 3960 * task receive 3961 */ 3962 #define MCPWM_TASK_CMPR1_A_UP_EN (BIT(1)) 3963 #define MCPWM_TASK_CMPR1_A_UP_EN_M (MCPWM_TASK_CMPR1_A_UP_EN_V << MCPWM_TASK_CMPR1_A_UP_EN_S) 3964 #define MCPWM_TASK_CMPR1_A_UP_EN_V 0x00000001U 3965 #define MCPWM_TASK_CMPR1_A_UP_EN_S 1 3966 /** MCPWM_TASK_CMPR2_A_UP_EN : R/W; bitpos: [2]; default: 0; 3967 * set this bit high to enable PWM generator2 timer stamp A's shadow register update 3968 * task receive 3969 */ 3970 #define MCPWM_TASK_CMPR2_A_UP_EN (BIT(2)) 3971 #define MCPWM_TASK_CMPR2_A_UP_EN_M (MCPWM_TASK_CMPR2_A_UP_EN_V << MCPWM_TASK_CMPR2_A_UP_EN_S) 3972 #define MCPWM_TASK_CMPR2_A_UP_EN_V 0x00000001U 3973 #define MCPWM_TASK_CMPR2_A_UP_EN_S 2 3974 /** MCPWM_TASK_CMPR0_B_UP_EN : R/W; bitpos: [3]; default: 0; 3975 * set this bit high to enable PWM generator0 timer stamp B's shadow register update 3976 * task receive 3977 */ 3978 #define MCPWM_TASK_CMPR0_B_UP_EN (BIT(3)) 3979 #define MCPWM_TASK_CMPR0_B_UP_EN_M (MCPWM_TASK_CMPR0_B_UP_EN_V << MCPWM_TASK_CMPR0_B_UP_EN_S) 3980 #define MCPWM_TASK_CMPR0_B_UP_EN_V 0x00000001U 3981 #define MCPWM_TASK_CMPR0_B_UP_EN_S 3 3982 /** MCPWM_TASK_CMPR1_B_UP_EN : R/W; bitpos: [4]; default: 0; 3983 * set this bit high to enable PWM generator1 timer stamp B's shadow register update 3984 * task receive 3985 */ 3986 #define MCPWM_TASK_CMPR1_B_UP_EN (BIT(4)) 3987 #define MCPWM_TASK_CMPR1_B_UP_EN_M (MCPWM_TASK_CMPR1_B_UP_EN_V << MCPWM_TASK_CMPR1_B_UP_EN_S) 3988 #define MCPWM_TASK_CMPR1_B_UP_EN_V 0x00000001U 3989 #define MCPWM_TASK_CMPR1_B_UP_EN_S 4 3990 /** MCPWM_TASK_CMPR2_B_UP_EN : R/W; bitpos: [5]; default: 0; 3991 * set this bit high to enable PWM generator2 timer stamp B's shadow register update 3992 * task receive 3993 */ 3994 #define MCPWM_TASK_CMPR2_B_UP_EN (BIT(5)) 3995 #define MCPWM_TASK_CMPR2_B_UP_EN_M (MCPWM_TASK_CMPR2_B_UP_EN_V << MCPWM_TASK_CMPR2_B_UP_EN_S) 3996 #define MCPWM_TASK_CMPR2_B_UP_EN_V 0x00000001U 3997 #define MCPWM_TASK_CMPR2_B_UP_EN_S 5 3998 /** MCPWM_TASK_GEN_STOP_EN : R/W; bitpos: [6]; default: 0; 3999 * set this bit high to enable all PWM generate stop task receive 4000 */ 4001 #define MCPWM_TASK_GEN_STOP_EN (BIT(6)) 4002 #define MCPWM_TASK_GEN_STOP_EN_M (MCPWM_TASK_GEN_STOP_EN_V << MCPWM_TASK_GEN_STOP_EN_S) 4003 #define MCPWM_TASK_GEN_STOP_EN_V 0x00000001U 4004 #define MCPWM_TASK_GEN_STOP_EN_S 6 4005 /** MCPWM_TASK_TIMER0_SYNC_EN : R/W; bitpos: [7]; default: 0; 4006 * set this bit high to enable timer0 sync task receive 4007 */ 4008 #define MCPWM_TASK_TIMER0_SYNC_EN (BIT(7)) 4009 #define MCPWM_TASK_TIMER0_SYNC_EN_M (MCPWM_TASK_TIMER0_SYNC_EN_V << MCPWM_TASK_TIMER0_SYNC_EN_S) 4010 #define MCPWM_TASK_TIMER0_SYNC_EN_V 0x00000001U 4011 #define MCPWM_TASK_TIMER0_SYNC_EN_S 7 4012 /** MCPWM_TASK_TIMER1_SYNC_EN : R/W; bitpos: [8]; default: 0; 4013 * set this bit high to enable timer1 sync task receive 4014 */ 4015 #define MCPWM_TASK_TIMER1_SYNC_EN (BIT(8)) 4016 #define MCPWM_TASK_TIMER1_SYNC_EN_M (MCPWM_TASK_TIMER1_SYNC_EN_V << MCPWM_TASK_TIMER1_SYNC_EN_S) 4017 #define MCPWM_TASK_TIMER1_SYNC_EN_V 0x00000001U 4018 #define MCPWM_TASK_TIMER1_SYNC_EN_S 8 4019 /** MCPWM_TASK_TIMER2_SYNC_EN : R/W; bitpos: [9]; default: 0; 4020 * set this bit high to enable timer2 sync task receive 4021 */ 4022 #define MCPWM_TASK_TIMER2_SYNC_EN (BIT(9)) 4023 #define MCPWM_TASK_TIMER2_SYNC_EN_M (MCPWM_TASK_TIMER2_SYNC_EN_V << MCPWM_TASK_TIMER2_SYNC_EN_S) 4024 #define MCPWM_TASK_TIMER2_SYNC_EN_V 0x00000001U 4025 #define MCPWM_TASK_TIMER2_SYNC_EN_S 9 4026 /** MCPWM_TASK_TIMER0_PERIOD_UP_EN : R/W; bitpos: [10]; default: 0; 4027 * set this bit high to enable timer0 period update task receive 4028 */ 4029 #define MCPWM_TASK_TIMER0_PERIOD_UP_EN (BIT(10)) 4030 #define MCPWM_TASK_TIMER0_PERIOD_UP_EN_M (MCPWM_TASK_TIMER0_PERIOD_UP_EN_V << MCPWM_TASK_TIMER0_PERIOD_UP_EN_S) 4031 #define MCPWM_TASK_TIMER0_PERIOD_UP_EN_V 0x00000001U 4032 #define MCPWM_TASK_TIMER0_PERIOD_UP_EN_S 10 4033 /** MCPWM_TASK_TIMER1_PERIOD_UP_EN : R/W; bitpos: [11]; default: 0; 4034 * set this bit high to enable timer1 period update task receive 4035 */ 4036 #define MCPWM_TASK_TIMER1_PERIOD_UP_EN (BIT(11)) 4037 #define MCPWM_TASK_TIMER1_PERIOD_UP_EN_M (MCPWM_TASK_TIMER1_PERIOD_UP_EN_V << MCPWM_TASK_TIMER1_PERIOD_UP_EN_S) 4038 #define MCPWM_TASK_TIMER1_PERIOD_UP_EN_V 0x00000001U 4039 #define MCPWM_TASK_TIMER1_PERIOD_UP_EN_S 11 4040 /** MCPWM_TASK_TIMER2_PERIOD_UP_EN : R/W; bitpos: [12]; default: 0; 4041 * set this bit high to enable timer2 period update task receive 4042 */ 4043 #define MCPWM_TASK_TIMER2_PERIOD_UP_EN (BIT(12)) 4044 #define MCPWM_TASK_TIMER2_PERIOD_UP_EN_M (MCPWM_TASK_TIMER2_PERIOD_UP_EN_V << MCPWM_TASK_TIMER2_PERIOD_UP_EN_S) 4045 #define MCPWM_TASK_TIMER2_PERIOD_UP_EN_V 0x00000001U 4046 #define MCPWM_TASK_TIMER2_PERIOD_UP_EN_S 12 4047 /** MCPWM_TASK_TZ0_OST_EN : R/W; bitpos: [13]; default: 0; 4048 * set this bit high to enable one shot trip0 task receive 4049 */ 4050 #define MCPWM_TASK_TZ0_OST_EN (BIT(13)) 4051 #define MCPWM_TASK_TZ0_OST_EN_M (MCPWM_TASK_TZ0_OST_EN_V << MCPWM_TASK_TZ0_OST_EN_S) 4052 #define MCPWM_TASK_TZ0_OST_EN_V 0x00000001U 4053 #define MCPWM_TASK_TZ0_OST_EN_S 13 4054 /** MCPWM_TASK_TZ1_OST_EN : R/W; bitpos: [14]; default: 0; 4055 * set this bit high to enable one shot trip1 task receive 4056 */ 4057 #define MCPWM_TASK_TZ1_OST_EN (BIT(14)) 4058 #define MCPWM_TASK_TZ1_OST_EN_M (MCPWM_TASK_TZ1_OST_EN_V << MCPWM_TASK_TZ1_OST_EN_S) 4059 #define MCPWM_TASK_TZ1_OST_EN_V 0x00000001U 4060 #define MCPWM_TASK_TZ1_OST_EN_S 14 4061 /** MCPWM_TASK_TZ2_OST_EN : R/W; bitpos: [15]; default: 0; 4062 * set this bit high to enable one shot trip2 task receive 4063 */ 4064 #define MCPWM_TASK_TZ2_OST_EN (BIT(15)) 4065 #define MCPWM_TASK_TZ2_OST_EN_M (MCPWM_TASK_TZ2_OST_EN_V << MCPWM_TASK_TZ2_OST_EN_S) 4066 #define MCPWM_TASK_TZ2_OST_EN_V 0x00000001U 4067 #define MCPWM_TASK_TZ2_OST_EN_S 15 4068 /** MCPWM_TASK_CLR0_OST_EN : R/W; bitpos: [16]; default: 0; 4069 * set this bit high to enable one shot trip0 clear task receive 4070 */ 4071 #define MCPWM_TASK_CLR0_OST_EN (BIT(16)) 4072 #define MCPWM_TASK_CLR0_OST_EN_M (MCPWM_TASK_CLR0_OST_EN_V << MCPWM_TASK_CLR0_OST_EN_S) 4073 #define MCPWM_TASK_CLR0_OST_EN_V 0x00000001U 4074 #define MCPWM_TASK_CLR0_OST_EN_S 16 4075 /** MCPWM_TASK_CLR1_OST_EN : R/W; bitpos: [17]; default: 0; 4076 * set this bit high to enable one shot trip1 clear task receive 4077 */ 4078 #define MCPWM_TASK_CLR1_OST_EN (BIT(17)) 4079 #define MCPWM_TASK_CLR1_OST_EN_M (MCPWM_TASK_CLR1_OST_EN_V << MCPWM_TASK_CLR1_OST_EN_S) 4080 #define MCPWM_TASK_CLR1_OST_EN_V 0x00000001U 4081 #define MCPWM_TASK_CLR1_OST_EN_S 17 4082 /** MCPWM_TASK_CLR2_OST_EN : R/W; bitpos: [18]; default: 0; 4083 * set this bit high to enable one shot trip2 clear task receive 4084 */ 4085 #define MCPWM_TASK_CLR2_OST_EN (BIT(18)) 4086 #define MCPWM_TASK_CLR2_OST_EN_M (MCPWM_TASK_CLR2_OST_EN_V << MCPWM_TASK_CLR2_OST_EN_S) 4087 #define MCPWM_TASK_CLR2_OST_EN_V 0x00000001U 4088 #define MCPWM_TASK_CLR2_OST_EN_S 18 4089 /** MCPWM_TASK_CAP0_EN : R/W; bitpos: [19]; default: 0; 4090 * set this bit high to enable capture0 task receive 4091 */ 4092 #define MCPWM_TASK_CAP0_EN (BIT(19)) 4093 #define MCPWM_TASK_CAP0_EN_M (MCPWM_TASK_CAP0_EN_V << MCPWM_TASK_CAP0_EN_S) 4094 #define MCPWM_TASK_CAP0_EN_V 0x00000001U 4095 #define MCPWM_TASK_CAP0_EN_S 19 4096 /** MCPWM_TASK_CAP1_EN : R/W; bitpos: [20]; default: 0; 4097 * set this bit high to enable capture1 task receive 4098 */ 4099 #define MCPWM_TASK_CAP1_EN (BIT(20)) 4100 #define MCPWM_TASK_CAP1_EN_M (MCPWM_TASK_CAP1_EN_V << MCPWM_TASK_CAP1_EN_S) 4101 #define MCPWM_TASK_CAP1_EN_V 0x00000001U 4102 #define MCPWM_TASK_CAP1_EN_S 20 4103 /** MCPWM_TASK_CAP2_EN : R/W; bitpos: [21]; default: 0; 4104 * set this bit high to enable capture2 task receive 4105 */ 4106 #define MCPWM_TASK_CAP2_EN (BIT(21)) 4107 #define MCPWM_TASK_CAP2_EN_M (MCPWM_TASK_CAP2_EN_V << MCPWM_TASK_CAP2_EN_S) 4108 #define MCPWM_TASK_CAP2_EN_V 0x00000001U 4109 #define MCPWM_TASK_CAP2_EN_S 21 4110 4111 /** MCPWM_CLK_REG register 4112 * MCPWM APB configuration register 4113 */ 4114 #define MCPWM_CLK_REG(i) (REG_MCPWM_BASE(i) + 0x128) 4115 /** MCPWM_CLK_EN : R/W; bitpos: [0]; default: 0; 4116 * Force clock on for this register file 4117 */ 4118 #define MCPWM_CLK_EN (BIT(0)) 4119 #define MCPWM_CLK_EN_M (MCPWM_CLK_EN_V << MCPWM_CLK_EN_S) 4120 #define MCPWM_CLK_EN_V 0x00000001U 4121 #define MCPWM_CLK_EN_S 0 4122 4123 /** MCPWM_VERSION_REG register 4124 * Version register. 4125 */ 4126 #define MCPWM_VERSION_REG(i) (REG_MCPWM_BASE(i) + 0x12c) 4127 /** MCPWM_DATE : R/W; bitpos: [27:0]; default: 35656256; 4128 * Version of this register file 4129 */ 4130 #define MCPWM_DATE 0x0FFFFFFFU 4131 #define MCPWM_DATE_M (MCPWM_DATE_V << MCPWM_DATE_S) 4132 #define MCPWM_DATE_V 0x0FFFFFFFU 4133 #define MCPWM_DATE_S 0 4134 4135 #ifdef __cplusplus 4136 } 4137 #endif 4138
