1 /*
2  * SPDX-FileCopyrightText: 2017-2023 Espressif Systems (Shanghai) CO LTD
3  *
4  * SPDX-License-Identifier: Apache-2.0
5  */
6 
7 #include "sdkconfig.h"
8 #include "esp_efuse.h"
9 #include <assert.h>
10 #include "esp_efuse_table.h"
11 
12 // md5_digest_table 0d9c0c6a65ccf2d4a7279ede32b6f797
13 // This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY.
14 // If you want to change some fields, you need to change esp_efuse_table.csv file
15 // then run `efuse_common_table` or `efuse_custom_table` command it will generate this file.
16 // To show efuse_table run the command 'show_efuse_table'.
17 
18 static const esp_efuse_desc_t WR_DIS[] = {
19     {EFUSE_BLK0, 0, 32}, 	 // [] Disable programming of individual eFuses,
20 };
21 
22 static const esp_efuse_desc_t WR_DIS_RD_DIS[] = {
23     {EFUSE_BLK0, 0, 1}, 	 // [] wr_dis of RD_DIS,
24 };
25 
26 static const esp_efuse_desc_t WR_DIS_CRYPT_DPA_ENABLE[] = {
27     {EFUSE_BLK0, 1, 1}, 	 // [] wr_dis of CRYPT_DPA_ENABLE,
28 };
29 
30 static const esp_efuse_desc_t WR_DIS_SWAP_UART_SDIO_EN[] = {
31     {EFUSE_BLK0, 2, 1}, 	 // [] wr_dis of SWAP_UART_SDIO_EN,
32 };
33 
34 static const esp_efuse_desc_t WR_DIS_DIS_ICACHE[] = {
35     {EFUSE_BLK0, 2, 1}, 	 // [] wr_dis of DIS_ICACHE,
36 };
37 
38 static const esp_efuse_desc_t WR_DIS_DIS_USB_JTAG[] = {
39     {EFUSE_BLK0, 2, 1}, 	 // [] wr_dis of DIS_USB_JTAG,
40 };
41 
42 static const esp_efuse_desc_t WR_DIS_DIS_DOWNLOAD_ICACHE[] = {
43     {EFUSE_BLK0, 2, 1}, 	 // [] wr_dis of DIS_DOWNLOAD_ICACHE,
44 };
45 
46 static const esp_efuse_desc_t WR_DIS_DIS_USB_SERIAL_JTAG[] = {
47     {EFUSE_BLK0, 2, 1}, 	 // [] wr_dis of DIS_USB_SERIAL_JTAG,
48 };
49 
50 static const esp_efuse_desc_t WR_DIS_DIS_FORCE_DOWNLOAD[] = {
51     {EFUSE_BLK0, 2, 1}, 	 // [] wr_dis of DIS_FORCE_DOWNLOAD,
52 };
53 
54 static const esp_efuse_desc_t WR_DIS_DIS_TWAI[] = {
55     {EFUSE_BLK0, 2, 1}, 	 // [WR_DIS.DIS_CAN] wr_dis of DIS_TWAI,
56 };
57 
58 static const esp_efuse_desc_t WR_DIS_JTAG_SEL_ENABLE[] = {
59     {EFUSE_BLK0, 2, 1}, 	 // [] wr_dis of JTAG_SEL_ENABLE,
60 };
61 
62 static const esp_efuse_desc_t WR_DIS_DIS_PAD_JTAG[] = {
63     {EFUSE_BLK0, 2, 1}, 	 // [] wr_dis of DIS_PAD_JTAG,
64 };
65 
66 static const esp_efuse_desc_t WR_DIS_DIS_DOWNLOAD_MANUAL_ENCRYPT[] = {
67     {EFUSE_BLK0, 2, 1}, 	 // [] wr_dis of DIS_DOWNLOAD_MANUAL_ENCRYPT,
68 };
69 
70 static const esp_efuse_desc_t WR_DIS_WDT_DELAY_SEL[] = {
71     {EFUSE_BLK0, 3, 1}, 	 // [] wr_dis of WDT_DELAY_SEL,
72 };
73 
74 static const esp_efuse_desc_t WR_DIS_SPI_BOOT_CRYPT_CNT[] = {
75     {EFUSE_BLK0, 4, 1}, 	 // [] wr_dis of SPI_BOOT_CRYPT_CNT,
76 };
77 
78 static const esp_efuse_desc_t WR_DIS_SECURE_BOOT_KEY_REVOKE0[] = {
79     {EFUSE_BLK0, 5, 1}, 	 // [] wr_dis of SECURE_BOOT_KEY_REVOKE0,
80 };
81 
82 static const esp_efuse_desc_t WR_DIS_SECURE_BOOT_KEY_REVOKE1[] = {
83     {EFUSE_BLK0, 6, 1}, 	 // [] wr_dis of SECURE_BOOT_KEY_REVOKE1,
84 };
85 
86 static const esp_efuse_desc_t WR_DIS_SECURE_BOOT_KEY_REVOKE2[] = {
87     {EFUSE_BLK0, 7, 1}, 	 // [] wr_dis of SECURE_BOOT_KEY_REVOKE2,
88 };
89 
90 static const esp_efuse_desc_t WR_DIS_KEY_PURPOSE_0[] = {
91     {EFUSE_BLK0, 8, 1}, 	 // [WR_DIS.KEY0_PURPOSE] wr_dis of KEY_PURPOSE_0,
92 };
93 
94 static const esp_efuse_desc_t WR_DIS_KEY_PURPOSE_1[] = {
95     {EFUSE_BLK0, 9, 1}, 	 // [WR_DIS.KEY1_PURPOSE] wr_dis of KEY_PURPOSE_1,
96 };
97 
98 static const esp_efuse_desc_t WR_DIS_KEY_PURPOSE_2[] = {
99     {EFUSE_BLK0, 10, 1}, 	 // [WR_DIS.KEY2_PURPOSE] wr_dis of KEY_PURPOSE_2,
100 };
101 
102 static const esp_efuse_desc_t WR_DIS_KEY_PURPOSE_3[] = {
103     {EFUSE_BLK0, 11, 1}, 	 // [WR_DIS.KEY3_PURPOSE] wr_dis of KEY_PURPOSE_3,
104 };
105 
106 static const esp_efuse_desc_t WR_DIS_KEY_PURPOSE_4[] = {
107     {EFUSE_BLK0, 12, 1}, 	 // [WR_DIS.KEY4_PURPOSE] wr_dis of KEY_PURPOSE_4,
108 };
109 
110 static const esp_efuse_desc_t WR_DIS_KEY_PURPOSE_5[] = {
111     {EFUSE_BLK0, 13, 1}, 	 // [WR_DIS.KEY5_PURPOSE] wr_dis of KEY_PURPOSE_5,
112 };
113 
114 static const esp_efuse_desc_t WR_DIS_SEC_DPA_LEVEL[] = {
115     {EFUSE_BLK0, 14, 1}, 	 // [WR_DIS.DPA_SEC_LEVEL] wr_dis of SEC_DPA_LEVEL,
116 };
117 
118 static const esp_efuse_desc_t WR_DIS_SECURE_BOOT_EN[] = {
119     {EFUSE_BLK0, 15, 1}, 	 // [] wr_dis of SECURE_BOOT_EN,
120 };
121 
122 static const esp_efuse_desc_t WR_DIS_SECURE_BOOT_AGGRESSIVE_REVOKE[] = {
123     {EFUSE_BLK0, 16, 1}, 	 // [] wr_dis of SECURE_BOOT_AGGRESSIVE_REVOKE,
124 };
125 
126 static const esp_efuse_desc_t WR_DIS_SPI_DOWNLOAD_MSPI_DIS[] = {
127     {EFUSE_BLK0, 17, 1}, 	 // [] wr_dis of SPI_DOWNLOAD_MSPI_DIS,
128 };
129 
130 static const esp_efuse_desc_t WR_DIS_FLASH_TPUW[] = {
131     {EFUSE_BLK0, 18, 1}, 	 // [] wr_dis of FLASH_TPUW,
132 };
133 
134 static const esp_efuse_desc_t WR_DIS_DIS_DOWNLOAD_MODE[] = {
135     {EFUSE_BLK0, 18, 1}, 	 // [] wr_dis of DIS_DOWNLOAD_MODE,
136 };
137 
138 static const esp_efuse_desc_t WR_DIS_DIS_DIRECT_BOOT[] = {
139     {EFUSE_BLK0, 18, 1}, 	 // [] wr_dis of DIS_DIRECT_BOOT,
140 };
141 
142 static const esp_efuse_desc_t WR_DIS_DIS_USB_SERIAL_JTAG_ROM_PRINT[] = {
143     {EFUSE_BLK0, 18, 1}, 	 // [WR_DIS.DIS_USB_PRINT] wr_dis of DIS_USB_SERIAL_JTAG_ROM_PRINT,
144 };
145 
146 static const esp_efuse_desc_t WR_DIS_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE[] = {
147     {EFUSE_BLK0, 18, 1}, 	 // [] wr_dis of DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE,
148 };
149 
150 static const esp_efuse_desc_t WR_DIS_ENABLE_SECURITY_DOWNLOAD[] = {
151     {EFUSE_BLK0, 18, 1}, 	 // [] wr_dis of ENABLE_SECURITY_DOWNLOAD,
152 };
153 
154 static const esp_efuse_desc_t WR_DIS_UART_PRINT_CONTROL[] = {
155     {EFUSE_BLK0, 18, 1}, 	 // [] wr_dis of UART_PRINT_CONTROL,
156 };
157 
158 static const esp_efuse_desc_t WR_DIS_FORCE_SEND_RESUME[] = {
159     {EFUSE_BLK0, 18, 1}, 	 // [] wr_dis of FORCE_SEND_RESUME,
160 };
161 
162 static const esp_efuse_desc_t WR_DIS_SECURE_VERSION[] = {
163     {EFUSE_BLK0, 18, 1}, 	 // [] wr_dis of SECURE_VERSION,
164 };
165 
166 static const esp_efuse_desc_t WR_DIS_SECURE_BOOT_DISABLE_FAST_WAKE[] = {
167     {EFUSE_BLK0, 19, 1}, 	 // [] wr_dis of SECURE_BOOT_DISABLE_FAST_WAKE,
168 };
169 
170 static const esp_efuse_desc_t WR_DIS_DISABLE_WAFER_VERSION_MAJOR[] = {
171     {EFUSE_BLK0, 19, 1}, 	 // [] wr_dis of DISABLE_WAFER_VERSION_MAJOR,
172 };
173 
174 static const esp_efuse_desc_t WR_DIS_DISABLE_BLK_VERSION_MAJOR[] = {
175     {EFUSE_BLK0, 19, 1}, 	 // [] wr_dis of DISABLE_BLK_VERSION_MAJOR,
176 };
177 
178 static const esp_efuse_desc_t WR_DIS_BLK1[] = {
179     {EFUSE_BLK0, 20, 1}, 	 // [] wr_dis of BLOCK1,
180 };
181 
182 static const esp_efuse_desc_t WR_DIS_MAC[] = {
183     {EFUSE_BLK0, 20, 1}, 	 // [WR_DIS.MAC_FACTORY] wr_dis of MAC,
184 };
185 
186 static const esp_efuse_desc_t WR_DIS_MAC_EXT[] = {
187     {EFUSE_BLK0, 20, 1}, 	 // [] wr_dis of MAC_EXT,
188 };
189 
190 static const esp_efuse_desc_t WR_DIS_ACTIVE_HP_DBIAS[] = {
191     {EFUSE_BLK0, 20, 1}, 	 // [] wr_dis of ACTIVE_HP_DBIAS,
192 };
193 
194 static const esp_efuse_desc_t WR_DIS_ACTIVE_LP_DBIAS[] = {
195     {EFUSE_BLK0, 20, 1}, 	 // [] wr_dis of ACTIVE_LP_DBIAS,
196 };
197 
198 static const esp_efuse_desc_t WR_DIS_LSLP_HP_DBG[] = {
199     {EFUSE_BLK0, 20, 1}, 	 // [] wr_dis of LSLP_HP_DBG,
200 };
201 
202 static const esp_efuse_desc_t WR_DIS_LSLP_HP_DBIAS[] = {
203     {EFUSE_BLK0, 20, 1}, 	 // [] wr_dis of LSLP_HP_DBIAS,
204 };
205 
206 static const esp_efuse_desc_t WR_DIS_DSLP_LP_DBG[] = {
207     {EFUSE_BLK0, 20, 1}, 	 // [] wr_dis of DSLP_LP_DBG,
208 };
209 
210 static const esp_efuse_desc_t WR_DIS_DSLP_LP_DBIAS[] = {
211     {EFUSE_BLK0, 20, 1}, 	 // [] wr_dis of DSLP_LP_DBIAS,
212 };
213 
214 static const esp_efuse_desc_t WR_DIS_DBIAS_VOL_GAP[] = {
215     {EFUSE_BLK0, 20, 1}, 	 // [] wr_dis of DBIAS_VOL_GAP,
216 };
217 
218 static const esp_efuse_desc_t WR_DIS_WAFER_VERSION_MINOR[] = {
219     {EFUSE_BLK0, 20, 1}, 	 // [] wr_dis of WAFER_VERSION_MINOR,
220 };
221 
222 static const esp_efuse_desc_t WR_DIS_WAFER_VERSION_MAJOR[] = {
223     {EFUSE_BLK0, 20, 1}, 	 // [] wr_dis of WAFER_VERSION_MAJOR,
224 };
225 
226 static const esp_efuse_desc_t WR_DIS_PKG_VERSION[] = {
227     {EFUSE_BLK0, 20, 1}, 	 // [] wr_dis of PKG_VERSION,
228 };
229 
230 static const esp_efuse_desc_t WR_DIS_BLK_VERSION_MINOR[] = {
231     {EFUSE_BLK0, 20, 1}, 	 // [] wr_dis of BLK_VERSION_MINOR,
232 };
233 
234 static const esp_efuse_desc_t WR_DIS_BLK_VERSION_MAJOR[] = {
235     {EFUSE_BLK0, 20, 1}, 	 // [] wr_dis of BLK_VERSION_MAJOR,
236 };
237 
238 static const esp_efuse_desc_t WR_DIS_FLASH_CAP[] = {
239     {EFUSE_BLK0, 20, 1}, 	 // [] wr_dis of FLASH_CAP,
240 };
241 
242 static const esp_efuse_desc_t WR_DIS_FLASH_TEMP[] = {
243     {EFUSE_BLK0, 20, 1}, 	 // [] wr_dis of FLASH_TEMP,
244 };
245 
246 static const esp_efuse_desc_t WR_DIS_FLASH_VENDOR[] = {
247     {EFUSE_BLK0, 20, 1}, 	 // [] wr_dis of FLASH_VENDOR,
248 };
249 
250 static const esp_efuse_desc_t WR_DIS_SYS_DATA_PART1[] = {
251     {EFUSE_BLK0, 21, 1}, 	 // [] wr_dis of BLOCK2,
252 };
253 
254 static const esp_efuse_desc_t WR_DIS_OPTIONAL_UNIQUE_ID[] = {
255     {EFUSE_BLK0, 21, 1}, 	 // [] wr_dis of OPTIONAL_UNIQUE_ID,
256 };
257 
258 static const esp_efuse_desc_t WR_DIS_TEMP_CALIB[] = {
259     {EFUSE_BLK0, 21, 1}, 	 // [] wr_dis of TEMP_CALIB,
260 };
261 
262 static const esp_efuse_desc_t WR_DIS_OCODE[] = {
263     {EFUSE_BLK0, 21, 1}, 	 // [] wr_dis of OCODE,
264 };
265 
266 static const esp_efuse_desc_t WR_DIS_ADC1_INIT_CODE_ATTEN0[] = {
267     {EFUSE_BLK0, 21, 1}, 	 // [] wr_dis of ADC1_INIT_CODE_ATTEN0,
268 };
269 
270 static const esp_efuse_desc_t WR_DIS_ADC1_INIT_CODE_ATTEN1[] = {
271     {EFUSE_BLK0, 21, 1}, 	 // [] wr_dis of ADC1_INIT_CODE_ATTEN1,
272 };
273 
274 static const esp_efuse_desc_t WR_DIS_ADC1_INIT_CODE_ATTEN2[] = {
275     {EFUSE_BLK0, 21, 1}, 	 // [] wr_dis of ADC1_INIT_CODE_ATTEN2,
276 };
277 
278 static const esp_efuse_desc_t WR_DIS_ADC1_INIT_CODE_ATTEN3[] = {
279     {EFUSE_BLK0, 21, 1}, 	 // [] wr_dis of ADC1_INIT_CODE_ATTEN3,
280 };
281 
282 static const esp_efuse_desc_t WR_DIS_ADC1_CAL_VOL_ATTEN0[] = {
283     {EFUSE_BLK0, 21, 1}, 	 // [] wr_dis of ADC1_CAL_VOL_ATTEN0,
284 };
285 
286 static const esp_efuse_desc_t WR_DIS_ADC1_CAL_VOL_ATTEN1[] = {
287     {EFUSE_BLK0, 21, 1}, 	 // [] wr_dis of ADC1_CAL_VOL_ATTEN1,
288 };
289 
290 static const esp_efuse_desc_t WR_DIS_ADC1_CAL_VOL_ATTEN2[] = {
291     {EFUSE_BLK0, 21, 1}, 	 // [] wr_dis of ADC1_CAL_VOL_ATTEN2,
292 };
293 
294 static const esp_efuse_desc_t WR_DIS_ADC1_CAL_VOL_ATTEN3[] = {
295     {EFUSE_BLK0, 21, 1}, 	 // [] wr_dis of ADC1_CAL_VOL_ATTEN3,
296 };
297 
298 static const esp_efuse_desc_t WR_DIS_ADC1_INIT_CODE_ATTEN0_CH0[] = {
299     {EFUSE_BLK0, 21, 1}, 	 // [] wr_dis of ADC1_INIT_CODE_ATTEN0_CH0,
300 };
301 
302 static const esp_efuse_desc_t WR_DIS_ADC1_INIT_CODE_ATTEN0_CH1[] = {
303     {EFUSE_BLK0, 21, 1}, 	 // [] wr_dis of ADC1_INIT_CODE_ATTEN0_CH1,
304 };
305 
306 static const esp_efuse_desc_t WR_DIS_ADC1_INIT_CODE_ATTEN0_CH2[] = {
307     {EFUSE_BLK0, 21, 1}, 	 // [] wr_dis of ADC1_INIT_CODE_ATTEN0_CH2,
308 };
309 
310 static const esp_efuse_desc_t WR_DIS_ADC1_INIT_CODE_ATTEN0_CH3[] = {
311     {EFUSE_BLK0, 21, 1}, 	 // [] wr_dis of ADC1_INIT_CODE_ATTEN0_CH3,
312 };
313 
314 static const esp_efuse_desc_t WR_DIS_ADC1_INIT_CODE_ATTEN0_CH4[] = {
315     {EFUSE_BLK0, 21, 1}, 	 // [] wr_dis of ADC1_INIT_CODE_ATTEN0_CH4,
316 };
317 
318 static const esp_efuse_desc_t WR_DIS_ADC1_INIT_CODE_ATTEN0_CH5[] = {
319     {EFUSE_BLK0, 21, 1}, 	 // [] wr_dis of ADC1_INIT_CODE_ATTEN0_CH5,
320 };
321 
322 static const esp_efuse_desc_t WR_DIS_ADC1_INIT_CODE_ATTEN0_CH6[] = {
323     {EFUSE_BLK0, 21, 1}, 	 // [] wr_dis of ADC1_INIT_CODE_ATTEN0_CH6,
324 };
325 
326 static const esp_efuse_desc_t WR_DIS_BLOCK_USR_DATA[] = {
327     {EFUSE_BLK0, 22, 1}, 	 // [WR_DIS.USER_DATA] wr_dis of BLOCK_USR_DATA,
328 };
329 
330 static const esp_efuse_desc_t WR_DIS_CUSTOM_MAC[] = {
331     {EFUSE_BLK0, 22, 1}, 	 // [WR_DIS.MAC_CUSTOM WR_DIS.USER_DATA_MAC_CUSTOM] wr_dis of CUSTOM_MAC,
332 };
333 
334 static const esp_efuse_desc_t WR_DIS_BLOCK_KEY0[] = {
335     {EFUSE_BLK0, 23, 1}, 	 // [WR_DIS.KEY0] wr_dis of BLOCK_KEY0,
336 };
337 
338 static const esp_efuse_desc_t WR_DIS_BLOCK_KEY1[] = {
339     {EFUSE_BLK0, 24, 1}, 	 // [WR_DIS.KEY1] wr_dis of BLOCK_KEY1,
340 };
341 
342 static const esp_efuse_desc_t WR_DIS_BLOCK_KEY2[] = {
343     {EFUSE_BLK0, 25, 1}, 	 // [WR_DIS.KEY2] wr_dis of BLOCK_KEY2,
344 };
345 
346 static const esp_efuse_desc_t WR_DIS_BLOCK_KEY3[] = {
347     {EFUSE_BLK0, 26, 1}, 	 // [WR_DIS.KEY3] wr_dis of BLOCK_KEY3,
348 };
349 
350 static const esp_efuse_desc_t WR_DIS_BLOCK_KEY4[] = {
351     {EFUSE_BLK0, 27, 1}, 	 // [WR_DIS.KEY4] wr_dis of BLOCK_KEY4,
352 };
353 
354 static const esp_efuse_desc_t WR_DIS_BLOCK_KEY5[] = {
355     {EFUSE_BLK0, 28, 1}, 	 // [WR_DIS.KEY5] wr_dis of BLOCK_KEY5,
356 };
357 
358 static const esp_efuse_desc_t WR_DIS_BLOCK_SYS_DATA2[] = {
359     {EFUSE_BLK0, 29, 1}, 	 // [WR_DIS.SYS_DATA_PART2] wr_dis of BLOCK_SYS_DATA2,
360 };
361 
362 static const esp_efuse_desc_t WR_DIS_USB_EXCHG_PINS[] = {
363     {EFUSE_BLK0, 30, 1}, 	 // [] wr_dis of USB_EXCHG_PINS,
364 };
365 
366 static const esp_efuse_desc_t WR_DIS_VDD_SPI_AS_GPIO[] = {
367     {EFUSE_BLK0, 30, 1}, 	 // [] wr_dis of VDD_SPI_AS_GPIO,
368 };
369 
370 static const esp_efuse_desc_t WR_DIS_SOFT_DIS_JTAG[] = {
371     {EFUSE_BLK0, 31, 1}, 	 // [] wr_dis of SOFT_DIS_JTAG,
372 };
373 
374 static const esp_efuse_desc_t RD_DIS[] = {
375     {EFUSE_BLK0, 32, 7}, 	 // [] Disable reading from BlOCK4-10,
376 };
377 
378 static const esp_efuse_desc_t RD_DIS_BLOCK_KEY0[] = {
379     {EFUSE_BLK0, 32, 1}, 	 // [RD_DIS.KEY0] rd_dis of BLOCK_KEY0,
380 };
381 
382 static const esp_efuse_desc_t RD_DIS_BLOCK_KEY1[] = {
383     {EFUSE_BLK0, 33, 1}, 	 // [RD_DIS.KEY1] rd_dis of BLOCK_KEY1,
384 };
385 
386 static const esp_efuse_desc_t RD_DIS_BLOCK_KEY2[] = {
387     {EFUSE_BLK0, 34, 1}, 	 // [RD_DIS.KEY2] rd_dis of BLOCK_KEY2,
388 };
389 
390 static const esp_efuse_desc_t RD_DIS_BLOCK_KEY3[] = {
391     {EFUSE_BLK0, 35, 1}, 	 // [RD_DIS.KEY3] rd_dis of BLOCK_KEY3,
392 };
393 
394 static const esp_efuse_desc_t RD_DIS_BLOCK_KEY4[] = {
395     {EFUSE_BLK0, 36, 1}, 	 // [RD_DIS.KEY4] rd_dis of BLOCK_KEY4,
396 };
397 
398 static const esp_efuse_desc_t RD_DIS_BLOCK_KEY5[] = {
399     {EFUSE_BLK0, 37, 1}, 	 // [RD_DIS.KEY5] rd_dis of BLOCK_KEY5,
400 };
401 
402 static const esp_efuse_desc_t RD_DIS_BLOCK_SYS_DATA2[] = {
403     {EFUSE_BLK0, 38, 1}, 	 // [RD_DIS.SYS_DATA_PART2] rd_dis of BLOCK_SYS_DATA2,
404 };
405 
406 static const esp_efuse_desc_t SWAP_UART_SDIO_EN[] = {
407     {EFUSE_BLK0, 39, 1}, 	 // [] Represents whether pad of uart and sdio is swapped or not. 1: swapped. 0: not swapped,
408 };
409 
410 static const esp_efuse_desc_t DIS_ICACHE[] = {
411     {EFUSE_BLK0, 40, 1}, 	 // [] Represents whether icache is disabled or enabled. 1: disabled. 0: enabled,
412 };
413 
414 static const esp_efuse_desc_t DIS_USB_JTAG[] = {
415     {EFUSE_BLK0, 41, 1}, 	 // [] Represents whether the function of usb switch to jtag is disabled or enabled. 1: disabled. 0: enabled,
416 };
417 
418 static const esp_efuse_desc_t DIS_DOWNLOAD_ICACHE[] = {
419     {EFUSE_BLK0, 42, 1}, 	 // [] Represents whether icache is disabled or enabled in Download mode. 1: disabled. 0: enabled,
420 };
421 
422 static const esp_efuse_desc_t DIS_USB_SERIAL_JTAG[] = {
423     {EFUSE_BLK0, 43, 1}, 	 // [] Represents whether USB-Serial-JTAG is disabled or enabled. 1: disabled. 0: enabled,
424 };
425 
426 static const esp_efuse_desc_t DIS_FORCE_DOWNLOAD[] = {
427     {EFUSE_BLK0, 44, 1}, 	 // [] Represents whether the function that forces chip into download mode is disabled or enabled. 1: disabled. 0: enabled,
428 };
429 
430 static const esp_efuse_desc_t SPI_DOWNLOAD_MSPI_DIS[] = {
431     {EFUSE_BLK0, 45, 1}, 	 // [] Represents whether SPI0 controller during boot_mode_download is disabled or enabled. 1: disabled. 0: enabled,
432 };
433 
434 static const esp_efuse_desc_t DIS_TWAI[] = {
435     {EFUSE_BLK0, 46, 1}, 	 // [DIS_CAN] Represents whether TWAI function is disabled or enabled. 1: disabled. 0: enabled,
436 };
437 
438 static const esp_efuse_desc_t JTAG_SEL_ENABLE[] = {
439     {EFUSE_BLK0, 47, 1}, 	 // [] Represents whether the selection between usb_to_jtag and pad_to_jtag through strapping gpio15 when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are equal to 0 is enabled or disabled. 1: enabled. 0: disabled,
440 };
441 
442 static const esp_efuse_desc_t SOFT_DIS_JTAG[] = {
443     {EFUSE_BLK0, 48, 3}, 	 // [] Represents whether JTAG is disabled in soft way. Odd number: disabled. Even number: enabled,
444 };
445 
446 static const esp_efuse_desc_t DIS_PAD_JTAG[] = {
447     {EFUSE_BLK0, 51, 1}, 	 // [] Represents whether JTAG is disabled in the hard way(permanently). 1: disabled. 0: enabled,
448 };
449 
450 static const esp_efuse_desc_t DIS_DOWNLOAD_MANUAL_ENCRYPT[] = {
451     {EFUSE_BLK0, 52, 1}, 	 // [] Represents whether flash encrypt function is disabled or enabled(except in SPI boot mode). 1: disabled. 0: enabled,
452 };
453 
454 static const esp_efuse_desc_t USB_EXCHG_PINS[] = {
455     {EFUSE_BLK0, 57, 1}, 	 // [] Represents whether the D+ and D- pins is exchanged. 1: exchanged. 0: not exchanged,
456 };
457 
458 static const esp_efuse_desc_t VDD_SPI_AS_GPIO[] = {
459     {EFUSE_BLK0, 58, 1}, 	 // [] Represents whether vdd spi pin is functioned as gpio. 1: functioned. 0: not functioned,
460 };
461 
462 static const esp_efuse_desc_t WDT_DELAY_SEL[] = {
463     {EFUSE_BLK0, 80, 2}, 	 // [] Represents whether RTC watchdog timeout threshold is selected at startup. 1: selected. 0: not selected,
464 };
465 
466 static const esp_efuse_desc_t SPI_BOOT_CRYPT_CNT[] = {
467     {EFUSE_BLK0, 82, 3}, 	 // [] Enables flash encryption when 1 or 3 bits are set and disables otherwise {0: "Disable"; 1: "Enable"; 3: "Disable"; 7: "Enable"},
468 };
469 
470 static const esp_efuse_desc_t SECURE_BOOT_KEY_REVOKE0[] = {
471     {EFUSE_BLK0, 85, 1}, 	 // [] Revoke 1st secure boot key,
472 };
473 
474 static const esp_efuse_desc_t SECURE_BOOT_KEY_REVOKE1[] = {
475     {EFUSE_BLK0, 86, 1}, 	 // [] Revoke 2nd secure boot key,
476 };
477 
478 static const esp_efuse_desc_t SECURE_BOOT_KEY_REVOKE2[] = {
479     {EFUSE_BLK0, 87, 1}, 	 // [] Revoke 3rd secure boot key,
480 };
481 
482 static const esp_efuse_desc_t KEY_PURPOSE_0[] = {
483     {EFUSE_BLK0, 88, 4}, 	 // [KEY0_PURPOSE] Represents the purpose of Key0,
484 };
485 
486 static const esp_efuse_desc_t KEY_PURPOSE_1[] = {
487     {EFUSE_BLK0, 92, 4}, 	 // [KEY1_PURPOSE] Represents the purpose of Key1,
488 };
489 
490 static const esp_efuse_desc_t KEY_PURPOSE_2[] = {
491     {EFUSE_BLK0, 96, 4}, 	 // [KEY2_PURPOSE] Represents the purpose of Key2,
492 };
493 
494 static const esp_efuse_desc_t KEY_PURPOSE_3[] = {
495     {EFUSE_BLK0, 100, 4}, 	 // [KEY3_PURPOSE] Represents the purpose of Key3,
496 };
497 
498 static const esp_efuse_desc_t KEY_PURPOSE_4[] = {
499     {EFUSE_BLK0, 104, 4}, 	 // [KEY4_PURPOSE] Represents the purpose of Key4,
500 };
501 
502 static const esp_efuse_desc_t KEY_PURPOSE_5[] = {
503     {EFUSE_BLK0, 108, 4}, 	 // [KEY5_PURPOSE] Represents the purpose of Key5,
504 };
505 
506 static const esp_efuse_desc_t SEC_DPA_LEVEL[] = {
507     {EFUSE_BLK0, 112, 2}, 	 // [DPA_SEC_LEVEL] Represents the spa secure level by configuring the clock random divide mode,
508 };
509 
510 static const esp_efuse_desc_t CRYPT_DPA_ENABLE[] = {
511     {EFUSE_BLK0, 114, 1}, 	 // [] Represents whether anti-dpa attack is enabled. 1:enabled. 0: disabled,
512 };
513 
514 static const esp_efuse_desc_t SECURE_BOOT_EN[] = {
515     {EFUSE_BLK0, 116, 1}, 	 // [] Represents whether secure boot is enabled or disabled. 1: enabled. 0: disabled,
516 };
517 
518 static const esp_efuse_desc_t SECURE_BOOT_AGGRESSIVE_REVOKE[] = {
519     {EFUSE_BLK0, 117, 1}, 	 // [] Represents whether revoking aggressive secure boot is enabled or disabled. 1: enabled. 0: disabled,
520 };
521 
522 static const esp_efuse_desc_t FLASH_TPUW[] = {
523     {EFUSE_BLK0, 124, 4}, 	 // [] Represents the flash waiting time after power-up; in unit of ms. When the value less than 15; the waiting time is the programmed value. Otherwise; the waiting time is 2 times the programmed value,
524 };
525 
526 static const esp_efuse_desc_t DIS_DOWNLOAD_MODE[] = {
527     {EFUSE_BLK0, 128, 1}, 	 // [] Represents whether Download mode is disabled or enabled. 1: disabled. 0: enabled,
528 };
529 
530 static const esp_efuse_desc_t DIS_DIRECT_BOOT[] = {
531     {EFUSE_BLK0, 129, 1}, 	 // [] Represents whether direct boot mode is disabled or enabled. 1: disabled. 0: enabled,
532 };
533 
534 static const esp_efuse_desc_t DIS_USB_SERIAL_JTAG_ROM_PRINT[] = {
535     {EFUSE_BLK0, 130, 1}, 	 // [DIS_USB_PRINT] Represents whether print from USB-Serial-JTAG is disabled or enabled. 1: disabled. 0: enabled,
536 };
537 
538 static const esp_efuse_desc_t DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE[] = {
539     {EFUSE_BLK0, 132, 1}, 	 // [] Represents whether the USB-Serial-JTAG download function is disabled or enabled. 1: disabled. 0: enabled,
540 };
541 
542 static const esp_efuse_desc_t ENABLE_SECURITY_DOWNLOAD[] = {
543     {EFUSE_BLK0, 133, 1}, 	 // [] Represents whether security download is enabled or disabled. 1: enabled. 0: disabled,
544 };
545 
546 static const esp_efuse_desc_t UART_PRINT_CONTROL[] = {
547     {EFUSE_BLK0, 134, 2}, 	 // [] Set the default UARTboot message output mode {0: "Enable"; 1: "Enable when GPIO8 is low at reset"; 2: "Enable when GPIO8 is high at reset"; 3: "Disable"},
548 };
549 
550 static const esp_efuse_desc_t FORCE_SEND_RESUME[] = {
551     {EFUSE_BLK0, 141, 1}, 	 // [] Represents whether ROM code is forced to send a resume command during SPI boot. 1: forced. 0:not forced,
552 };
553 
554 static const esp_efuse_desc_t SECURE_VERSION[] = {
555     {EFUSE_BLK0, 142, 16}, 	 // [] Represents the version used by ESP-IDF anti-rollback feature,
556 };
557 
558 static const esp_efuse_desc_t SECURE_BOOT_DISABLE_FAST_WAKE[] = {
559     {EFUSE_BLK0, 158, 1}, 	 // [] Represents whether FAST VERIFY ON WAKE is disabled or enabled when Secure Boot is enabled. 1: disabled. 0: enabled,
560 };
561 
562 static const esp_efuse_desc_t DISABLE_WAFER_VERSION_MAJOR[] = {
563     {EFUSE_BLK0, 160, 1}, 	 // [] Disables check of wafer version major,
564 };
565 
566 static const esp_efuse_desc_t DISABLE_BLK_VERSION_MAJOR[] = {
567     {EFUSE_BLK0, 161, 1}, 	 // [] Disables check of blk version major,
568 };
569 
570 static const esp_efuse_desc_t MAC[] = {
571     {EFUSE_BLK1, 40, 8}, 	 // [MAC_FACTORY] MAC address,
572     {EFUSE_BLK1, 32, 8}, 	 // [MAC_FACTORY] MAC address,
573     {EFUSE_BLK1, 24, 8}, 	 // [MAC_FACTORY] MAC address,
574     {EFUSE_BLK1, 16, 8}, 	 // [MAC_FACTORY] MAC address,
575     {EFUSE_BLK1, 8, 8}, 	 // [MAC_FACTORY] MAC address,
576     {EFUSE_BLK1, 0, 8}, 	 // [MAC_FACTORY] MAC address,
577 };
578 
579 static const esp_efuse_desc_t MAC_EXT[] = {
580     {EFUSE_BLK1, 56, 8}, 	 // [] Stores the extended bits of MAC address,
581     {EFUSE_BLK1, 48, 8}, 	 // [] Stores the extended bits of MAC address,
582 };
583 
584 static const esp_efuse_desc_t ACTIVE_HP_DBIAS[] = {
585     {EFUSE_BLK1, 64, 5}, 	 // [] Stores the active hp dbias,
586 };
587 
588 static const esp_efuse_desc_t ACTIVE_LP_DBIAS[] = {
589     {EFUSE_BLK1, 69, 5}, 	 // [] Stores the active lp dbias,
590 };
591 
592 static const esp_efuse_desc_t LSLP_HP_DBG[] = {
593     {EFUSE_BLK1, 74, 2}, 	 // [] Stores the lslp hp dbg,
594 };
595 
596 static const esp_efuse_desc_t LSLP_HP_DBIAS[] = {
597     {EFUSE_BLK1, 76, 4}, 	 // [] Stores the lslp hp dbias,
598 };
599 
600 static const esp_efuse_desc_t DSLP_LP_DBG[] = {
601     {EFUSE_BLK1, 80, 3}, 	 // [] Stores the dslp lp dbg,
602 };
603 
604 static const esp_efuse_desc_t DSLP_LP_DBIAS[] = {
605     {EFUSE_BLK1, 83, 4}, 	 // [] Stores the dslp lp dbias,
606 };
607 
608 static const esp_efuse_desc_t DBIAS_VOL_GAP[] = {
609     {EFUSE_BLK1, 87, 5}, 	 // [] Stores the hp and lp dbias vol gap,
610 };
611 
612 static const esp_efuse_desc_t WAFER_VERSION_MINOR[] = {
613     {EFUSE_BLK1, 114, 4}, 	 // [],
614 };
615 
616 static const esp_efuse_desc_t WAFER_VERSION_MAJOR[] = {
617     {EFUSE_BLK1, 118, 2}, 	 // [],
618 };
619 
620 static const esp_efuse_desc_t PKG_VERSION[] = {
621     {EFUSE_BLK1, 120, 3}, 	 // [] Package version,
622 };
623 
624 static const esp_efuse_desc_t BLK_VERSION_MINOR[] = {
625     {EFUSE_BLK1, 123, 3}, 	 // [] BLK_VERSION_MINOR of BLOCK2,
626 };
627 
628 static const esp_efuse_desc_t BLK_VERSION_MAJOR[] = {
629     {EFUSE_BLK1, 126, 2}, 	 // [] BLK_VERSION_MAJOR of BLOCK2,
630 };
631 
632 static const esp_efuse_desc_t FLASH_CAP[] = {
633     {EFUSE_BLK1, 128, 3}, 	 // [],
634 };
635 
636 static const esp_efuse_desc_t FLASH_TEMP[] = {
637     {EFUSE_BLK1, 131, 2}, 	 // [],
638 };
639 
640 static const esp_efuse_desc_t FLASH_VENDOR[] = {
641     {EFUSE_BLK1, 133, 3}, 	 // [],
642 };
643 
644 static const esp_efuse_desc_t OPTIONAL_UNIQUE_ID[] = {
645     {EFUSE_BLK2, 0, 128}, 	 // [] Optional unique 128-bit ID,
646 };
647 
648 static const esp_efuse_desc_t TEMP_CALIB[] = {
649     {EFUSE_BLK2, 128, 9}, 	 // [] Temperature calibration data,
650 };
651 
652 static const esp_efuse_desc_t OCODE[] = {
653     {EFUSE_BLK2, 137, 8}, 	 // [] ADC OCode,
654 };
655 
656 static const esp_efuse_desc_t ADC1_INIT_CODE_ATTEN0[] = {
657     {EFUSE_BLK2, 145, 10}, 	 // [] ADC1 init code at atten0,
658 };
659 
660 static const esp_efuse_desc_t ADC1_INIT_CODE_ATTEN1[] = {
661     {EFUSE_BLK2, 155, 10}, 	 // [] ADC1 init code at atten1,
662 };
663 
664 static const esp_efuse_desc_t ADC1_INIT_CODE_ATTEN2[] = {
665     {EFUSE_BLK2, 165, 10}, 	 // [] ADC1 init code at atten2,
666 };
667 
668 static const esp_efuse_desc_t ADC1_INIT_CODE_ATTEN3[] = {
669     {EFUSE_BLK2, 175, 10}, 	 // [] ADC1 init code at atten3,
670 };
671 
672 static const esp_efuse_desc_t ADC1_CAL_VOL_ATTEN0[] = {
673     {EFUSE_BLK2, 185, 10}, 	 // [] ADC1 calibration voltage at atten0,
674 };
675 
676 static const esp_efuse_desc_t ADC1_CAL_VOL_ATTEN1[] = {
677     {EFUSE_BLK2, 195, 10}, 	 // [] ADC1 calibration voltage at atten1,
678 };
679 
680 static const esp_efuse_desc_t ADC1_CAL_VOL_ATTEN2[] = {
681     {EFUSE_BLK2, 205, 10}, 	 // [] ADC1 calibration voltage at atten2,
682 };
683 
684 static const esp_efuse_desc_t ADC1_CAL_VOL_ATTEN3[] = {
685     {EFUSE_BLK2, 215, 10}, 	 // [] ADC1 calibration voltage at atten3,
686 };
687 
688 static const esp_efuse_desc_t ADC1_INIT_CODE_ATTEN0_CH0[] = {
689     {EFUSE_BLK2, 225, 4}, 	 // [] ADC1 init code at atten0 ch0,
690 };
691 
692 static const esp_efuse_desc_t ADC1_INIT_CODE_ATTEN0_CH1[] = {
693     {EFUSE_BLK2, 229, 4}, 	 // [] ADC1 init code at atten0 ch1,
694 };
695 
696 static const esp_efuse_desc_t ADC1_INIT_CODE_ATTEN0_CH2[] = {
697     {EFUSE_BLK2, 233, 4}, 	 // [] ADC1 init code at atten0 ch2,
698 };
699 
700 static const esp_efuse_desc_t ADC1_INIT_CODE_ATTEN0_CH3[] = {
701     {EFUSE_BLK2, 237, 4}, 	 // [] ADC1 init code at atten0 ch3,
702 };
703 
704 static const esp_efuse_desc_t ADC1_INIT_CODE_ATTEN0_CH4[] = {
705     {EFUSE_BLK2, 241, 4}, 	 // [] ADC1 init code at atten0 ch4,
706 };
707 
708 static const esp_efuse_desc_t ADC1_INIT_CODE_ATTEN0_CH5[] = {
709     {EFUSE_BLK2, 245, 4}, 	 // [] ADC1 init code at atten0 ch5,
710 };
711 
712 static const esp_efuse_desc_t ADC1_INIT_CODE_ATTEN0_CH6[] = {
713     {EFUSE_BLK2, 249, 4}, 	 // [] ADC1 init code at atten0 ch6,
714 };
715 
716 static const esp_efuse_desc_t USER_DATA[] = {
717     {EFUSE_BLK3, 0, 256}, 	 // [BLOCK_USR_DATA] User data,
718 };
719 
720 static const esp_efuse_desc_t USER_DATA_MAC_CUSTOM[] = {
721     {EFUSE_BLK3, 200, 48}, 	 // [MAC_CUSTOM CUSTOM_MAC] Custom MAC,
722 };
723 
724 static const esp_efuse_desc_t KEY0[] = {
725     {EFUSE_BLK4, 0, 256}, 	 // [BLOCK_KEY0] Key0 or user data,
726 };
727 
728 static const esp_efuse_desc_t KEY1[] = {
729     {EFUSE_BLK5, 0, 256}, 	 // [BLOCK_KEY1] Key1 or user data,
730 };
731 
732 static const esp_efuse_desc_t KEY2[] = {
733     {EFUSE_BLK6, 0, 256}, 	 // [BLOCK_KEY2] Key2 or user data,
734 };
735 
736 static const esp_efuse_desc_t KEY3[] = {
737     {EFUSE_BLK7, 0, 256}, 	 // [BLOCK_KEY3] Key3 or user data,
738 };
739 
740 static const esp_efuse_desc_t KEY4[] = {
741     {EFUSE_BLK8, 0, 256}, 	 // [BLOCK_KEY4] Key4 or user data,
742 };
743 
744 static const esp_efuse_desc_t KEY5[] = {
745     {EFUSE_BLK9, 0, 256}, 	 // [BLOCK_KEY5] Key5 or user data,
746 };
747 
748 static const esp_efuse_desc_t SYS_DATA_PART2[] = {
749     {EFUSE_BLK10, 0, 256}, 	 // [BLOCK_SYS_DATA2] System data part 2 (reserved),
750 };
751 
752 
753 
754 
755 
756 const esp_efuse_desc_t* ESP_EFUSE_WR_DIS[] = {
757     &WR_DIS[0],    		// [] Disable programming of individual eFuses
758     NULL
759 };
760 
761 const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RD_DIS[] = {
762     &WR_DIS_RD_DIS[0],    		// [] wr_dis of RD_DIS
763     NULL
764 };
765 
766 const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_CRYPT_DPA_ENABLE[] = {
767     &WR_DIS_CRYPT_DPA_ENABLE[0],    		// [] wr_dis of CRYPT_DPA_ENABLE
768     NULL
769 };
770 
771 const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SWAP_UART_SDIO_EN[] = {
772     &WR_DIS_SWAP_UART_SDIO_EN[0],    		// [] wr_dis of SWAP_UART_SDIO_EN
773     NULL
774 };
775 
776 const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_ICACHE[] = {
777     &WR_DIS_DIS_ICACHE[0],    		// [] wr_dis of DIS_ICACHE
778     NULL
779 };
780 
781 const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_USB_JTAG[] = {
782     &WR_DIS_DIS_USB_JTAG[0],    		// [] wr_dis of DIS_USB_JTAG
783     NULL
784 };
785 
786 const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DOWNLOAD_ICACHE[] = {
787     &WR_DIS_DIS_DOWNLOAD_ICACHE[0],    		// [] wr_dis of DIS_DOWNLOAD_ICACHE
788     NULL
789 };
790 
791 const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_USB_SERIAL_JTAG[] = {
792     &WR_DIS_DIS_USB_SERIAL_JTAG[0],    		// [] wr_dis of DIS_USB_SERIAL_JTAG
793     NULL
794 };
795 
796 const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_FORCE_DOWNLOAD[] = {
797     &WR_DIS_DIS_FORCE_DOWNLOAD[0],    		// [] wr_dis of DIS_FORCE_DOWNLOAD
798     NULL
799 };
800 
801 const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_TWAI[] = {
802     &WR_DIS_DIS_TWAI[0],    		// [WR_DIS.DIS_CAN] wr_dis of DIS_TWAI
803     NULL
804 };
805 
806 const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_JTAG_SEL_ENABLE[] = {
807     &WR_DIS_JTAG_SEL_ENABLE[0],    		// [] wr_dis of JTAG_SEL_ENABLE
808     NULL
809 };
810 
811 const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_PAD_JTAG[] = {
812     &WR_DIS_DIS_PAD_JTAG[0],    		// [] wr_dis of DIS_PAD_JTAG
813     NULL
814 };
815 
816 const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DOWNLOAD_MANUAL_ENCRYPT[] = {
817     &WR_DIS_DIS_DOWNLOAD_MANUAL_ENCRYPT[0],    		// [] wr_dis of DIS_DOWNLOAD_MANUAL_ENCRYPT
818     NULL
819 };
820 
821 const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WDT_DELAY_SEL[] = {
822     &WR_DIS_WDT_DELAY_SEL[0],    		// [] wr_dis of WDT_DELAY_SEL
823     NULL
824 };
825 
826 const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_BOOT_CRYPT_CNT[] = {
827     &WR_DIS_SPI_BOOT_CRYPT_CNT[0],    		// [] wr_dis of SPI_BOOT_CRYPT_CNT
828     NULL
829 };
830 
831 const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE0[] = {
832     &WR_DIS_SECURE_BOOT_KEY_REVOKE0[0],    		// [] wr_dis of SECURE_BOOT_KEY_REVOKE0
833     NULL
834 };
835 
836 const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE1[] = {
837     &WR_DIS_SECURE_BOOT_KEY_REVOKE1[0],    		// [] wr_dis of SECURE_BOOT_KEY_REVOKE1
838     NULL
839 };
840 
841 const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE2[] = {
842     &WR_DIS_SECURE_BOOT_KEY_REVOKE2[0],    		// [] wr_dis of SECURE_BOOT_KEY_REVOKE2
843     NULL
844 };
845 
846 const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_0[] = {
847     &WR_DIS_KEY_PURPOSE_0[0],    		// [WR_DIS.KEY0_PURPOSE] wr_dis of KEY_PURPOSE_0
848     NULL
849 };
850 
851 const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_1[] = {
852     &WR_DIS_KEY_PURPOSE_1[0],    		// [WR_DIS.KEY1_PURPOSE] wr_dis of KEY_PURPOSE_1
853     NULL
854 };
855 
856 const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_2[] = {
857     &WR_DIS_KEY_PURPOSE_2[0],    		// [WR_DIS.KEY2_PURPOSE] wr_dis of KEY_PURPOSE_2
858     NULL
859 };
860 
861 const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_3[] = {
862     &WR_DIS_KEY_PURPOSE_3[0],    		// [WR_DIS.KEY3_PURPOSE] wr_dis of KEY_PURPOSE_3
863     NULL
864 };
865 
866 const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_4[] = {
867     &WR_DIS_KEY_PURPOSE_4[0],    		// [WR_DIS.KEY4_PURPOSE] wr_dis of KEY_PURPOSE_4
868     NULL
869 };
870 
871 const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_5[] = {
872     &WR_DIS_KEY_PURPOSE_5[0],    		// [WR_DIS.KEY5_PURPOSE] wr_dis of KEY_PURPOSE_5
873     NULL
874 };
875 
876 const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SEC_DPA_LEVEL[] = {
877     &WR_DIS_SEC_DPA_LEVEL[0],    		// [WR_DIS.DPA_SEC_LEVEL] wr_dis of SEC_DPA_LEVEL
878     NULL
879 };
880 
881 const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_EN[] = {
882     &WR_DIS_SECURE_BOOT_EN[0],    		// [] wr_dis of SECURE_BOOT_EN
883     NULL
884 };
885 
886 const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_AGGRESSIVE_REVOKE[] = {
887     &WR_DIS_SECURE_BOOT_AGGRESSIVE_REVOKE[0],    		// [] wr_dis of SECURE_BOOT_AGGRESSIVE_REVOKE
888     NULL
889 };
890 
891 const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_DOWNLOAD_MSPI_DIS[] = {
892     &WR_DIS_SPI_DOWNLOAD_MSPI_DIS[0],    		// [] wr_dis of SPI_DOWNLOAD_MSPI_DIS
893     NULL
894 };
895 
896 const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_TPUW[] = {
897     &WR_DIS_FLASH_TPUW[0],    		// [] wr_dis of FLASH_TPUW
898     NULL
899 };
900 
901 const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DOWNLOAD_MODE[] = {
902     &WR_DIS_DIS_DOWNLOAD_MODE[0],    		// [] wr_dis of DIS_DOWNLOAD_MODE
903     NULL
904 };
905 
906 const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DIRECT_BOOT[] = {
907     &WR_DIS_DIS_DIRECT_BOOT[0],    		// [] wr_dis of DIS_DIRECT_BOOT
908     NULL
909 };
910 
911 const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_USB_SERIAL_JTAG_ROM_PRINT[] = {
912     &WR_DIS_DIS_USB_SERIAL_JTAG_ROM_PRINT[0],    		// [WR_DIS.DIS_USB_PRINT] wr_dis of DIS_USB_SERIAL_JTAG_ROM_PRINT
913     NULL
914 };
915 
916 const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE[] = {
917     &WR_DIS_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE[0],    		// [] wr_dis of DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE
918     NULL
919 };
920 
921 const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ENABLE_SECURITY_DOWNLOAD[] = {
922     &WR_DIS_ENABLE_SECURITY_DOWNLOAD[0],    		// [] wr_dis of ENABLE_SECURITY_DOWNLOAD
923     NULL
924 };
925 
926 const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_UART_PRINT_CONTROL[] = {
927     &WR_DIS_UART_PRINT_CONTROL[0],    		// [] wr_dis of UART_PRINT_CONTROL
928     NULL
929 };
930 
931 const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FORCE_SEND_RESUME[] = {
932     &WR_DIS_FORCE_SEND_RESUME[0],    		// [] wr_dis of FORCE_SEND_RESUME
933     NULL
934 };
935 
936 const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_VERSION[] = {
937     &WR_DIS_SECURE_VERSION[0],    		// [] wr_dis of SECURE_VERSION
938     NULL
939 };
940 
941 const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_DISABLE_FAST_WAKE[] = {
942     &WR_DIS_SECURE_BOOT_DISABLE_FAST_WAKE[0],    		// [] wr_dis of SECURE_BOOT_DISABLE_FAST_WAKE
943     NULL
944 };
945 
946 const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DISABLE_WAFER_VERSION_MAJOR[] = {
947     &WR_DIS_DISABLE_WAFER_VERSION_MAJOR[0],    		// [] wr_dis of DISABLE_WAFER_VERSION_MAJOR
948     NULL
949 };
950 
951 const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DISABLE_BLK_VERSION_MAJOR[] = {
952     &WR_DIS_DISABLE_BLK_VERSION_MAJOR[0],    		// [] wr_dis of DISABLE_BLK_VERSION_MAJOR
953     NULL
954 };
955 
956 const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK1[] = {
957     &WR_DIS_BLK1[0],    		// [] wr_dis of BLOCK1
958     NULL
959 };
960 
961 const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_MAC[] = {
962     &WR_DIS_MAC[0],    		// [WR_DIS.MAC_FACTORY] wr_dis of MAC
963     NULL
964 };
965 
966 const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_MAC_EXT[] = {
967     &WR_DIS_MAC_EXT[0],    		// [] wr_dis of MAC_EXT
968     NULL
969 };
970 
971 const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ACTIVE_HP_DBIAS[] = {
972     &WR_DIS_ACTIVE_HP_DBIAS[0],    		// [] wr_dis of ACTIVE_HP_DBIAS
973     NULL
974 };
975 
976 const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ACTIVE_LP_DBIAS[] = {
977     &WR_DIS_ACTIVE_LP_DBIAS[0],    		// [] wr_dis of ACTIVE_LP_DBIAS
978     NULL
979 };
980 
981 const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LSLP_HP_DBG[] = {
982     &WR_DIS_LSLP_HP_DBG[0],    		// [] wr_dis of LSLP_HP_DBG
983     NULL
984 };
985 
986 const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LSLP_HP_DBIAS[] = {
987     &WR_DIS_LSLP_HP_DBIAS[0],    		// [] wr_dis of LSLP_HP_DBIAS
988     NULL
989 };
990 
991 const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DSLP_LP_DBG[] = {
992     &WR_DIS_DSLP_LP_DBG[0],    		// [] wr_dis of DSLP_LP_DBG
993     NULL
994 };
995 
996 const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DSLP_LP_DBIAS[] = {
997     &WR_DIS_DSLP_LP_DBIAS[0],    		// [] wr_dis of DSLP_LP_DBIAS
998     NULL
999 };
1000 
1001 const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DBIAS_VOL_GAP[] = {
1002     &WR_DIS_DBIAS_VOL_GAP[0],    		// [] wr_dis of DBIAS_VOL_GAP
1003     NULL
1004 };
1005 
1006 const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WAFER_VERSION_MINOR[] = {
1007     &WR_DIS_WAFER_VERSION_MINOR[0],    		// [] wr_dis of WAFER_VERSION_MINOR
1008     NULL
1009 };
1010 
1011 const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WAFER_VERSION_MAJOR[] = {
1012     &WR_DIS_WAFER_VERSION_MAJOR[0],    		// [] wr_dis of WAFER_VERSION_MAJOR
1013     NULL
1014 };
1015 
1016 const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PKG_VERSION[] = {
1017     &WR_DIS_PKG_VERSION[0],    		// [] wr_dis of PKG_VERSION
1018     NULL
1019 };
1020 
1021 const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK_VERSION_MINOR[] = {
1022     &WR_DIS_BLK_VERSION_MINOR[0],    		// [] wr_dis of BLK_VERSION_MINOR
1023     NULL
1024 };
1025 
1026 const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK_VERSION_MAJOR[] = {
1027     &WR_DIS_BLK_VERSION_MAJOR[0],    		// [] wr_dis of BLK_VERSION_MAJOR
1028     NULL
1029 };
1030 
1031 const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_CAP[] = {
1032     &WR_DIS_FLASH_CAP[0],    		// [] wr_dis of FLASH_CAP
1033     NULL
1034 };
1035 
1036 const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_TEMP[] = {
1037     &WR_DIS_FLASH_TEMP[0],    		// [] wr_dis of FLASH_TEMP
1038     NULL
1039 };
1040 
1041 const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_VENDOR[] = {
1042     &WR_DIS_FLASH_VENDOR[0],    		// [] wr_dis of FLASH_VENDOR
1043     NULL
1044 };
1045 
1046 const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SYS_DATA_PART1[] = {
1047     &WR_DIS_SYS_DATA_PART1[0],    		// [] wr_dis of BLOCK2
1048     NULL
1049 };
1050 
1051 const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_OPTIONAL_UNIQUE_ID[] = {
1052     &WR_DIS_OPTIONAL_UNIQUE_ID[0],    		// [] wr_dis of OPTIONAL_UNIQUE_ID
1053     NULL
1054 };
1055 
1056 const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_TEMP_CALIB[] = {
1057     &WR_DIS_TEMP_CALIB[0],    		// [] wr_dis of TEMP_CALIB
1058     NULL
1059 };
1060 
1061 const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_OCODE[] = {
1062     &WR_DIS_OCODE[0],    		// [] wr_dis of OCODE
1063     NULL
1064 };
1065 
1066 const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_INIT_CODE_ATTEN0[] = {
1067     &WR_DIS_ADC1_INIT_CODE_ATTEN0[0],    		// [] wr_dis of ADC1_INIT_CODE_ATTEN0
1068     NULL
1069 };
1070 
1071 const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_INIT_CODE_ATTEN1[] = {
1072     &WR_DIS_ADC1_INIT_CODE_ATTEN1[0],    		// [] wr_dis of ADC1_INIT_CODE_ATTEN1
1073     NULL
1074 };
1075 
1076 const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_INIT_CODE_ATTEN2[] = {
1077     &WR_DIS_ADC1_INIT_CODE_ATTEN2[0],    		// [] wr_dis of ADC1_INIT_CODE_ATTEN2
1078     NULL
1079 };
1080 
1081 const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_INIT_CODE_ATTEN3[] = {
1082     &WR_DIS_ADC1_INIT_CODE_ATTEN3[0],    		// [] wr_dis of ADC1_INIT_CODE_ATTEN3
1083     NULL
1084 };
1085 
1086 const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CAL_VOL_ATTEN0[] = {
1087     &WR_DIS_ADC1_CAL_VOL_ATTEN0[0],    		// [] wr_dis of ADC1_CAL_VOL_ATTEN0
1088     NULL
1089 };
1090 
1091 const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CAL_VOL_ATTEN1[] = {
1092     &WR_DIS_ADC1_CAL_VOL_ATTEN1[0],    		// [] wr_dis of ADC1_CAL_VOL_ATTEN1
1093     NULL
1094 };
1095 
1096 const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CAL_VOL_ATTEN2[] = {
1097     &WR_DIS_ADC1_CAL_VOL_ATTEN2[0],    		// [] wr_dis of ADC1_CAL_VOL_ATTEN2
1098     NULL
1099 };
1100 
1101 const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CAL_VOL_ATTEN3[] = {
1102     &WR_DIS_ADC1_CAL_VOL_ATTEN3[0],    		// [] wr_dis of ADC1_CAL_VOL_ATTEN3
1103     NULL
1104 };
1105 
1106 const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_INIT_CODE_ATTEN0_CH0[] = {
1107     &WR_DIS_ADC1_INIT_CODE_ATTEN0_CH0[0],    		// [] wr_dis of ADC1_INIT_CODE_ATTEN0_CH0
1108     NULL
1109 };
1110 
1111 const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_INIT_CODE_ATTEN0_CH1[] = {
1112     &WR_DIS_ADC1_INIT_CODE_ATTEN0_CH1[0],    		// [] wr_dis of ADC1_INIT_CODE_ATTEN0_CH1
1113     NULL
1114 };
1115 
1116 const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_INIT_CODE_ATTEN0_CH2[] = {
1117     &WR_DIS_ADC1_INIT_CODE_ATTEN0_CH2[0],    		// [] wr_dis of ADC1_INIT_CODE_ATTEN0_CH2
1118     NULL
1119 };
1120 
1121 const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_INIT_CODE_ATTEN0_CH3[] = {
1122     &WR_DIS_ADC1_INIT_CODE_ATTEN0_CH3[0],    		// [] wr_dis of ADC1_INIT_CODE_ATTEN0_CH3
1123     NULL
1124 };
1125 
1126 const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_INIT_CODE_ATTEN0_CH4[] = {
1127     &WR_DIS_ADC1_INIT_CODE_ATTEN0_CH4[0],    		// [] wr_dis of ADC1_INIT_CODE_ATTEN0_CH4
1128     NULL
1129 };
1130 
1131 const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_INIT_CODE_ATTEN0_CH5[] = {
1132     &WR_DIS_ADC1_INIT_CODE_ATTEN0_CH5[0],    		// [] wr_dis of ADC1_INIT_CODE_ATTEN0_CH5
1133     NULL
1134 };
1135 
1136 const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_INIT_CODE_ATTEN0_CH6[] = {
1137     &WR_DIS_ADC1_INIT_CODE_ATTEN0_CH6[0],    		// [] wr_dis of ADC1_INIT_CODE_ATTEN0_CH6
1138     NULL
1139 };
1140 
1141 const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_USR_DATA[] = {
1142     &WR_DIS_BLOCK_USR_DATA[0],    		// [WR_DIS.USER_DATA] wr_dis of BLOCK_USR_DATA
1143     NULL
1144 };
1145 
1146 const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_CUSTOM_MAC[] = {
1147     &WR_DIS_CUSTOM_MAC[0],    		// [WR_DIS.MAC_CUSTOM WR_DIS.USER_DATA_MAC_CUSTOM] wr_dis of CUSTOM_MAC
1148     NULL
1149 };
1150 
1151 const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY0[] = {
1152     &WR_DIS_BLOCK_KEY0[0],    		// [WR_DIS.KEY0] wr_dis of BLOCK_KEY0
1153     NULL
1154 };
1155 
1156 const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY1[] = {
1157     &WR_DIS_BLOCK_KEY1[0],    		// [WR_DIS.KEY1] wr_dis of BLOCK_KEY1
1158     NULL
1159 };
1160 
1161 const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY2[] = {
1162     &WR_DIS_BLOCK_KEY2[0],    		// [WR_DIS.KEY2] wr_dis of BLOCK_KEY2
1163     NULL
1164 };
1165 
1166 const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY3[] = {
1167     &WR_DIS_BLOCK_KEY3[0],    		// [WR_DIS.KEY3] wr_dis of BLOCK_KEY3
1168     NULL
1169 };
1170 
1171 const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY4[] = {
1172     &WR_DIS_BLOCK_KEY4[0],    		// [WR_DIS.KEY4] wr_dis of BLOCK_KEY4
1173     NULL
1174 };
1175 
1176 const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY5[] = {
1177     &WR_DIS_BLOCK_KEY5[0],    		// [WR_DIS.KEY5] wr_dis of BLOCK_KEY5
1178     NULL
1179 };
1180 
1181 const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_SYS_DATA2[] = {
1182     &WR_DIS_BLOCK_SYS_DATA2[0],    		// [WR_DIS.SYS_DATA_PART2] wr_dis of BLOCK_SYS_DATA2
1183     NULL
1184 };
1185 
1186 const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_USB_EXCHG_PINS[] = {
1187     &WR_DIS_USB_EXCHG_PINS[0],    		// [] wr_dis of USB_EXCHG_PINS
1188     NULL
1189 };
1190 
1191 const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_VDD_SPI_AS_GPIO[] = {
1192     &WR_DIS_VDD_SPI_AS_GPIO[0],    		// [] wr_dis of VDD_SPI_AS_GPIO
1193     NULL
1194 };
1195 
1196 const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SOFT_DIS_JTAG[] = {
1197     &WR_DIS_SOFT_DIS_JTAG[0],    		// [] wr_dis of SOFT_DIS_JTAG
1198     NULL
1199 };
1200 
1201 const esp_efuse_desc_t* ESP_EFUSE_RD_DIS[] = {
1202     &RD_DIS[0],    		// [] Disable reading from BlOCK4-10
1203     NULL
1204 };
1205 
1206 const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY0[] = {
1207     &RD_DIS_BLOCK_KEY0[0],    		// [RD_DIS.KEY0] rd_dis of BLOCK_KEY0
1208     NULL
1209 };
1210 
1211 const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY1[] = {
1212     &RD_DIS_BLOCK_KEY1[0],    		// [RD_DIS.KEY1] rd_dis of BLOCK_KEY1
1213     NULL
1214 };
1215 
1216 const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY2[] = {
1217     &RD_DIS_BLOCK_KEY2[0],    		// [RD_DIS.KEY2] rd_dis of BLOCK_KEY2
1218     NULL
1219 };
1220 
1221 const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY3[] = {
1222     &RD_DIS_BLOCK_KEY3[0],    		// [RD_DIS.KEY3] rd_dis of BLOCK_KEY3
1223     NULL
1224 };
1225 
1226 const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY4[] = {
1227     &RD_DIS_BLOCK_KEY4[0],    		// [RD_DIS.KEY4] rd_dis of BLOCK_KEY4
1228     NULL
1229 };
1230 
1231 const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY5[] = {
1232     &RD_DIS_BLOCK_KEY5[0],    		// [RD_DIS.KEY5] rd_dis of BLOCK_KEY5
1233     NULL
1234 };
1235 
1236 const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_SYS_DATA2[] = {
1237     &RD_DIS_BLOCK_SYS_DATA2[0],    		// [RD_DIS.SYS_DATA_PART2] rd_dis of BLOCK_SYS_DATA2
1238     NULL
1239 };
1240 
1241 const esp_efuse_desc_t* ESP_EFUSE_SWAP_UART_SDIO_EN[] = {
1242     &SWAP_UART_SDIO_EN[0],    		// [] Represents whether pad of uart and sdio is swapped or not. 1: swapped. 0: not swapped
1243     NULL
1244 };
1245 
1246 const esp_efuse_desc_t* ESP_EFUSE_DIS_ICACHE[] = {
1247     &DIS_ICACHE[0],    		// [] Represents whether icache is disabled or enabled. 1: disabled. 0: enabled
1248     NULL
1249 };
1250 
1251 const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_JTAG[] = {
1252     &DIS_USB_JTAG[0],    		// [] Represents whether the function of usb switch to jtag is disabled or enabled. 1: disabled. 0: enabled
1253     NULL
1254 };
1255 
1256 const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_ICACHE[] = {
1257     &DIS_DOWNLOAD_ICACHE[0],    		// [] Represents whether icache is disabled or enabled in Download mode. 1: disabled. 0: enabled
1258     NULL
1259 };
1260 
1261 const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_SERIAL_JTAG[] = {
1262     &DIS_USB_SERIAL_JTAG[0],    		// [] Represents whether USB-Serial-JTAG is disabled or enabled. 1: disabled. 0: enabled
1263     NULL
1264 };
1265 
1266 const esp_efuse_desc_t* ESP_EFUSE_DIS_FORCE_DOWNLOAD[] = {
1267     &DIS_FORCE_DOWNLOAD[0],    		// [] Represents whether the function that forces chip into download mode is disabled or enabled. 1: disabled. 0: enabled
1268     NULL
1269 };
1270 
1271 const esp_efuse_desc_t* ESP_EFUSE_SPI_DOWNLOAD_MSPI_DIS[] = {
1272     &SPI_DOWNLOAD_MSPI_DIS[0],    		// [] Represents whether SPI0 controller during boot_mode_download is disabled or enabled. 1: disabled. 0: enabled
1273     NULL
1274 };
1275 
1276 const esp_efuse_desc_t* ESP_EFUSE_DIS_TWAI[] = {
1277     &DIS_TWAI[0],    		// [DIS_CAN] Represents whether TWAI function is disabled or enabled. 1: disabled. 0: enabled
1278     NULL
1279 };
1280 
1281 const esp_efuse_desc_t* ESP_EFUSE_JTAG_SEL_ENABLE[] = {
1282     &JTAG_SEL_ENABLE[0],    		// [] Represents whether the selection between usb_to_jtag and pad_to_jtag through strapping gpio15 when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are equal to 0 is enabled or disabled. 1: enabled. 0: disabled
1283     NULL
1284 };
1285 
1286 const esp_efuse_desc_t* ESP_EFUSE_SOFT_DIS_JTAG[] = {
1287     &SOFT_DIS_JTAG[0],    		// [] Represents whether JTAG is disabled in soft way. Odd number: disabled. Even number: enabled
1288     NULL
1289 };
1290 
1291 const esp_efuse_desc_t* ESP_EFUSE_DIS_PAD_JTAG[] = {
1292     &DIS_PAD_JTAG[0],    		// [] Represents whether JTAG is disabled in the hard way(permanently). 1: disabled. 0: enabled
1293     NULL
1294 };
1295 
1296 const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT[] = {
1297     &DIS_DOWNLOAD_MANUAL_ENCRYPT[0],    		// [] Represents whether flash encrypt function is disabled or enabled(except in SPI boot mode). 1: disabled. 0: enabled
1298     NULL
1299 };
1300 
1301 const esp_efuse_desc_t* ESP_EFUSE_USB_EXCHG_PINS[] = {
1302     &USB_EXCHG_PINS[0],    		// [] Represents whether the D+ and D- pins is exchanged. 1: exchanged. 0: not exchanged
1303     NULL
1304 };
1305 
1306 const esp_efuse_desc_t* ESP_EFUSE_VDD_SPI_AS_GPIO[] = {
1307     &VDD_SPI_AS_GPIO[0],    		// [] Represents whether vdd spi pin is functioned as gpio. 1: functioned. 0: not functioned
1308     NULL
1309 };
1310 
1311 const esp_efuse_desc_t* ESP_EFUSE_WDT_DELAY_SEL[] = {
1312     &WDT_DELAY_SEL[0],    		// [] Represents whether RTC watchdog timeout threshold is selected at startup. 1: selected. 0: not selected
1313     NULL
1314 };
1315 
1316 const esp_efuse_desc_t* ESP_EFUSE_SPI_BOOT_CRYPT_CNT[] = {
1317     &SPI_BOOT_CRYPT_CNT[0],    		// [] Enables flash encryption when 1 or 3 bits are set and disables otherwise {0: "Disable"; 1: "Enable"; 3: "Disable"; 7: "Enable"}
1318     NULL
1319 };
1320 
1321 const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_KEY_REVOKE0[] = {
1322     &SECURE_BOOT_KEY_REVOKE0[0],    		// [] Revoke 1st secure boot key
1323     NULL
1324 };
1325 
1326 const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_KEY_REVOKE1[] = {
1327     &SECURE_BOOT_KEY_REVOKE1[0],    		// [] Revoke 2nd secure boot key
1328     NULL
1329 };
1330 
1331 const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_KEY_REVOKE2[] = {
1332     &SECURE_BOOT_KEY_REVOKE2[0],    		// [] Revoke 3rd secure boot key
1333     NULL
1334 };
1335 
1336 const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_0[] = {
1337     &KEY_PURPOSE_0[0],    		// [KEY0_PURPOSE] Represents the purpose of Key0
1338     NULL
1339 };
1340 
1341 const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_1[] = {
1342     &KEY_PURPOSE_1[0],    		// [KEY1_PURPOSE] Represents the purpose of Key1
1343     NULL
1344 };
1345 
1346 const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_2[] = {
1347     &KEY_PURPOSE_2[0],    		// [KEY2_PURPOSE] Represents the purpose of Key2
1348     NULL
1349 };
1350 
1351 const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_3[] = {
1352     &KEY_PURPOSE_3[0],    		// [KEY3_PURPOSE] Represents the purpose of Key3
1353     NULL
1354 };
1355 
1356 const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_4[] = {
1357     &KEY_PURPOSE_4[0],    		// [KEY4_PURPOSE] Represents the purpose of Key4
1358     NULL
1359 };
1360 
1361 const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_5[] = {
1362     &KEY_PURPOSE_5[0],    		// [KEY5_PURPOSE] Represents the purpose of Key5
1363     NULL
1364 };
1365 
1366 const esp_efuse_desc_t* ESP_EFUSE_SEC_DPA_LEVEL[] = {
1367     &SEC_DPA_LEVEL[0],    		// [DPA_SEC_LEVEL] Represents the spa secure level by configuring the clock random divide mode
1368     NULL
1369 };
1370 
1371 const esp_efuse_desc_t* ESP_EFUSE_CRYPT_DPA_ENABLE[] = {
1372     &CRYPT_DPA_ENABLE[0],    		// [] Represents whether anti-dpa attack is enabled. 1:enabled. 0: disabled
1373     NULL
1374 };
1375 
1376 const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_EN[] = {
1377     &SECURE_BOOT_EN[0],    		// [] Represents whether secure boot is enabled or disabled. 1: enabled. 0: disabled
1378     NULL
1379 };
1380 
1381 const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE[] = {
1382     &SECURE_BOOT_AGGRESSIVE_REVOKE[0],    		// [] Represents whether revoking aggressive secure boot is enabled or disabled. 1: enabled. 0: disabled
1383     NULL
1384 };
1385 
1386 const esp_efuse_desc_t* ESP_EFUSE_FLASH_TPUW[] = {
1387     &FLASH_TPUW[0],    		// [] Represents the flash waiting time after power-up; in unit of ms. When the value less than 15; the waiting time is the programmed value. Otherwise; the waiting time is 2 times the programmed value
1388     NULL
1389 };
1390 
1391 const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_MODE[] = {
1392     &DIS_DOWNLOAD_MODE[0],    		// [] Represents whether Download mode is disabled or enabled. 1: disabled. 0: enabled
1393     NULL
1394 };
1395 
1396 const esp_efuse_desc_t* ESP_EFUSE_DIS_DIRECT_BOOT[] = {
1397     &DIS_DIRECT_BOOT[0],    		// [] Represents whether direct boot mode is disabled or enabled. 1: disabled. 0: enabled
1398     NULL
1399 };
1400 
1401 const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT[] = {
1402     &DIS_USB_SERIAL_JTAG_ROM_PRINT[0],    		// [DIS_USB_PRINT] Represents whether print from USB-Serial-JTAG is disabled or enabled. 1: disabled. 0: enabled
1403     NULL
1404 };
1405 
1406 const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE[] = {
1407     &DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE[0],    		// [] Represents whether the USB-Serial-JTAG download function is disabled or enabled. 1: disabled. 0: enabled
1408     NULL
1409 };
1410 
1411 const esp_efuse_desc_t* ESP_EFUSE_ENABLE_SECURITY_DOWNLOAD[] = {
1412     &ENABLE_SECURITY_DOWNLOAD[0],    		// [] Represents whether security download is enabled or disabled. 1: enabled. 0: disabled
1413     NULL
1414 };
1415 
1416 const esp_efuse_desc_t* ESP_EFUSE_UART_PRINT_CONTROL[] = {
1417     &UART_PRINT_CONTROL[0],    		// [] Set the default UARTboot message output mode {0: "Enable"; 1: "Enable when GPIO8 is low at reset"; 2: "Enable when GPIO8 is high at reset"; 3: "Disable"}
1418     NULL
1419 };
1420 
1421 const esp_efuse_desc_t* ESP_EFUSE_FORCE_SEND_RESUME[] = {
1422     &FORCE_SEND_RESUME[0],    		// [] Represents whether ROM code is forced to send a resume command during SPI boot. 1: forced. 0:not forced
1423     NULL
1424 };
1425 
1426 const esp_efuse_desc_t* ESP_EFUSE_SECURE_VERSION[] = {
1427     &SECURE_VERSION[0],    		// [] Represents the version used by ESP-IDF anti-rollback feature
1428     NULL
1429 };
1430 
1431 const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE[] = {
1432     &SECURE_BOOT_DISABLE_FAST_WAKE[0],    		// [] Represents whether FAST VERIFY ON WAKE is disabled or enabled when Secure Boot is enabled. 1: disabled. 0: enabled
1433     NULL
1434 };
1435 
1436 const esp_efuse_desc_t* ESP_EFUSE_DISABLE_WAFER_VERSION_MAJOR[] = {
1437     &DISABLE_WAFER_VERSION_MAJOR[0],    		// [] Disables check of wafer version major
1438     NULL
1439 };
1440 
1441 const esp_efuse_desc_t* ESP_EFUSE_DISABLE_BLK_VERSION_MAJOR[] = {
1442     &DISABLE_BLK_VERSION_MAJOR[0],    		// [] Disables check of blk version major
1443     NULL
1444 };
1445 
1446 const esp_efuse_desc_t* ESP_EFUSE_MAC[] = {
1447     &MAC[0],    		// [MAC_FACTORY] MAC address
1448     &MAC[1],    		// [MAC_FACTORY] MAC address
1449     &MAC[2],    		// [MAC_FACTORY] MAC address
1450     &MAC[3],    		// [MAC_FACTORY] MAC address
1451     &MAC[4],    		// [MAC_FACTORY] MAC address
1452     &MAC[5],    		// [MAC_FACTORY] MAC address
1453     NULL
1454 };
1455 
1456 const esp_efuse_desc_t* ESP_EFUSE_MAC_EXT[] = {
1457     &MAC_EXT[0],    		// [] Stores the extended bits of MAC address
1458     &MAC_EXT[1],    		// [] Stores the extended bits of MAC address
1459     NULL
1460 };
1461 
1462 const esp_efuse_desc_t* ESP_EFUSE_ACTIVE_HP_DBIAS[] = {
1463     &ACTIVE_HP_DBIAS[0],    		// [] Stores the active hp dbias
1464     NULL
1465 };
1466 
1467 const esp_efuse_desc_t* ESP_EFUSE_ACTIVE_LP_DBIAS[] = {
1468     &ACTIVE_LP_DBIAS[0],    		// [] Stores the active lp dbias
1469     NULL
1470 };
1471 
1472 const esp_efuse_desc_t* ESP_EFUSE_LSLP_HP_DBG[] = {
1473     &LSLP_HP_DBG[0],    		// [] Stores the lslp hp dbg
1474     NULL
1475 };
1476 
1477 const esp_efuse_desc_t* ESP_EFUSE_LSLP_HP_DBIAS[] = {
1478     &LSLP_HP_DBIAS[0],    		// [] Stores the lslp hp dbias
1479     NULL
1480 };
1481 
1482 const esp_efuse_desc_t* ESP_EFUSE_DSLP_LP_DBG[] = {
1483     &DSLP_LP_DBG[0],    		// [] Stores the dslp lp dbg
1484     NULL
1485 };
1486 
1487 const esp_efuse_desc_t* ESP_EFUSE_DSLP_LP_DBIAS[] = {
1488     &DSLP_LP_DBIAS[0],    		// [] Stores the dslp lp dbias
1489     NULL
1490 };
1491 
1492 const esp_efuse_desc_t* ESP_EFUSE_DBIAS_VOL_GAP[] = {
1493     &DBIAS_VOL_GAP[0],    		// [] Stores the hp and lp dbias vol gap
1494     NULL
1495 };
1496 
1497 const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MINOR[] = {
1498     &WAFER_VERSION_MINOR[0],    		// []
1499     NULL
1500 };
1501 
1502 const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MAJOR[] = {
1503     &WAFER_VERSION_MAJOR[0],    		// []
1504     NULL
1505 };
1506 
1507 const esp_efuse_desc_t* ESP_EFUSE_PKG_VERSION[] = {
1508     &PKG_VERSION[0],    		// [] Package version
1509     NULL
1510 };
1511 
1512 const esp_efuse_desc_t* ESP_EFUSE_BLK_VERSION_MINOR[] = {
1513     &BLK_VERSION_MINOR[0],    		// [] BLK_VERSION_MINOR of BLOCK2
1514     NULL
1515 };
1516 
1517 const esp_efuse_desc_t* ESP_EFUSE_BLK_VERSION_MAJOR[] = {
1518     &BLK_VERSION_MAJOR[0],    		// [] BLK_VERSION_MAJOR of BLOCK2
1519     NULL
1520 };
1521 
1522 const esp_efuse_desc_t* ESP_EFUSE_FLASH_CAP[] = {
1523     &FLASH_CAP[0],    		// []
1524     NULL
1525 };
1526 
1527 const esp_efuse_desc_t* ESP_EFUSE_FLASH_TEMP[] = {
1528     &FLASH_TEMP[0],    		// []
1529     NULL
1530 };
1531 
1532 const esp_efuse_desc_t* ESP_EFUSE_FLASH_VENDOR[] = {
1533     &FLASH_VENDOR[0],    		// []
1534     NULL
1535 };
1536 
1537 const esp_efuse_desc_t* ESP_EFUSE_OPTIONAL_UNIQUE_ID[] = {
1538     &OPTIONAL_UNIQUE_ID[0],    		// [] Optional unique 128-bit ID
1539     NULL
1540 };
1541 
1542 const esp_efuse_desc_t* ESP_EFUSE_TEMP_CALIB[] = {
1543     &TEMP_CALIB[0],    		// [] Temperature calibration data
1544     NULL
1545 };
1546 
1547 const esp_efuse_desc_t* ESP_EFUSE_OCODE[] = {
1548     &OCODE[0],    		// [] ADC OCode
1549     NULL
1550 };
1551 
1552 const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN0[] = {
1553     &ADC1_INIT_CODE_ATTEN0[0],    		// [] ADC1 init code at atten0
1554     NULL
1555 };
1556 
1557 const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN1[] = {
1558     &ADC1_INIT_CODE_ATTEN1[0],    		// [] ADC1 init code at atten1
1559     NULL
1560 };
1561 
1562 const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN2[] = {
1563     &ADC1_INIT_CODE_ATTEN2[0],    		// [] ADC1 init code at atten2
1564     NULL
1565 };
1566 
1567 const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN3[] = {
1568     &ADC1_INIT_CODE_ATTEN3[0],    		// [] ADC1 init code at atten3
1569     NULL
1570 };
1571 
1572 const esp_efuse_desc_t* ESP_EFUSE_ADC1_CAL_VOL_ATTEN0[] = {
1573     &ADC1_CAL_VOL_ATTEN0[0],    		// [] ADC1 calibration voltage at atten0
1574     NULL
1575 };
1576 
1577 const esp_efuse_desc_t* ESP_EFUSE_ADC1_CAL_VOL_ATTEN1[] = {
1578     &ADC1_CAL_VOL_ATTEN1[0],    		// [] ADC1 calibration voltage at atten1
1579     NULL
1580 };
1581 
1582 const esp_efuse_desc_t* ESP_EFUSE_ADC1_CAL_VOL_ATTEN2[] = {
1583     &ADC1_CAL_VOL_ATTEN2[0],    		// [] ADC1 calibration voltage at atten2
1584     NULL
1585 };
1586 
1587 const esp_efuse_desc_t* ESP_EFUSE_ADC1_CAL_VOL_ATTEN3[] = {
1588     &ADC1_CAL_VOL_ATTEN3[0],    		// [] ADC1 calibration voltage at atten3
1589     NULL
1590 };
1591 
1592 const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN0_CH0[] = {
1593     &ADC1_INIT_CODE_ATTEN0_CH0[0],    		// [] ADC1 init code at atten0 ch0
1594     NULL
1595 };
1596 
1597 const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN0_CH1[] = {
1598     &ADC1_INIT_CODE_ATTEN0_CH1[0],    		// [] ADC1 init code at atten0 ch1
1599     NULL
1600 };
1601 
1602 const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN0_CH2[] = {
1603     &ADC1_INIT_CODE_ATTEN0_CH2[0],    		// [] ADC1 init code at atten0 ch2
1604     NULL
1605 };
1606 
1607 const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN0_CH3[] = {
1608     &ADC1_INIT_CODE_ATTEN0_CH3[0],    		// [] ADC1 init code at atten0 ch3
1609     NULL
1610 };
1611 
1612 const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN0_CH4[] = {
1613     &ADC1_INIT_CODE_ATTEN0_CH4[0],    		// [] ADC1 init code at atten0 ch4
1614     NULL
1615 };
1616 
1617 const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN0_CH5[] = {
1618     &ADC1_INIT_CODE_ATTEN0_CH5[0],    		// [] ADC1 init code at atten0 ch5
1619     NULL
1620 };
1621 
1622 const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN0_CH6[] = {
1623     &ADC1_INIT_CODE_ATTEN0_CH6[0],    		// [] ADC1 init code at atten0 ch6
1624     NULL
1625 };
1626 
1627 const esp_efuse_desc_t* ESP_EFUSE_USER_DATA[] = {
1628     &USER_DATA[0],    		// [BLOCK_USR_DATA] User data
1629     NULL
1630 };
1631 
1632 const esp_efuse_desc_t* ESP_EFUSE_USER_DATA_MAC_CUSTOM[] = {
1633     &USER_DATA_MAC_CUSTOM[0],    		// [MAC_CUSTOM CUSTOM_MAC] Custom MAC
1634     NULL
1635 };
1636 
1637 const esp_efuse_desc_t* ESP_EFUSE_KEY0[] = {
1638     &KEY0[0],    		// [BLOCK_KEY0] Key0 or user data
1639     NULL
1640 };
1641 
1642 const esp_efuse_desc_t* ESP_EFUSE_KEY1[] = {
1643     &KEY1[0],    		// [BLOCK_KEY1] Key1 or user data
1644     NULL
1645 };
1646 
1647 const esp_efuse_desc_t* ESP_EFUSE_KEY2[] = {
1648     &KEY2[0],    		// [BLOCK_KEY2] Key2 or user data
1649     NULL
1650 };
1651 
1652 const esp_efuse_desc_t* ESP_EFUSE_KEY3[] = {
1653     &KEY3[0],    		// [BLOCK_KEY3] Key3 or user data
1654     NULL
1655 };
1656 
1657 const esp_efuse_desc_t* ESP_EFUSE_KEY4[] = {
1658     &KEY4[0],    		// [BLOCK_KEY4] Key4 or user data
1659     NULL
1660 };
1661 
1662 const esp_efuse_desc_t* ESP_EFUSE_KEY5[] = {
1663     &KEY5[0],    		// [BLOCK_KEY5] Key5 or user data
1664     NULL
1665 };
1666 
1667 const esp_efuse_desc_t* ESP_EFUSE_SYS_DATA_PART2[] = {
1668     &SYS_DATA_PART2[0],    		// [BLOCK_SYS_DATA2] System data part 2 (reserved)
1669     NULL
1670 };
1671