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Searched full:vdd_spi_tieh (Results 1 – 23 of 23) sorted by relevance

/hal_espressif-latest/tools/esptool_py/espefuse/efuse/esp32s3/
Doperations.py193 sdio_tieh = efuses["VDD_SPI_TIEH"]
204 "Can't set regulator to 1.8V is VDD_SPI_TIEH efuse is already burned"
219 "by burning additional efuse VDD_SPI_TIEH"
222 "The following efuses are burned: VDD_SPI_FORCE, VDD_SPI_XPD, VDD_SPI_TIEH."
Dfields.py300 elif self["VDD_SPI_TIEH"].get() == 0:
/hal_espressif-latest/components/efuse/esp32s2/
Desp_efuse_table.csv28 WR_DIS.VDD_SPI_TIEH, EFUSE_BLK0, 3, 1, [] wr_dis of VDD_SPI_TIEH
132 VDD_SPI_TIEH, EFUSE_BLK0, 69, 1, [] If VDD_SPI_FORCE is 1; de…
133 … EFUSE_BLK0, 70, 1, [] Set this bit to use XPD_VDD_PSI_REG and VDD_SPI_TIEH to configure VD…
Desp_efuse_table.c75 {EFUSE_BLK0, 3, 1}, // [] wr_dis of VDD_SPI_TIEH,
490 static const esp_efuse_desc_t VDD_SPI_TIEH[] = { variable
495 …{EFUSE_BLK0, 70, 1}, // [] Set this bit to use XPD_VDD_PSI_REG and VDD_SPI_TIEH to configure VDD…
874 &WR_DIS_VDD_SPI_TIEH[0], // [] wr_dis of VDD_SPI_TIEH
1394 …&VDD_SPI_TIEH[0], // [] If VDD_SPI_FORCE is 1; determines VDD_SPI voltage {0: "VDD_SPI connec…
1399 …&VDD_SPI_FORCE[0], // [] Set this bit to use XPD_VDD_PSI_REG and VDD_SPI_TIEH to configure VD…
/hal_espressif-latest/tools/esptool_py/espefuse/efuse/esp32s2/
Doperations.py193 sdio_tieh = efuses["VDD_SPI_TIEH"]
204 "Can't set regulator to 1.8V is VDD_SPI_TIEH efuse is already burned"
219 "by burning additional efuse VDD_SPI_TIEH"
222 "The following efuses are burned: VDD_SPI_FORCE, VDD_SPI_XPD, VDD_SPI_TIEH."
Dfields.py339 elif self["VDD_SPI_TIEH"].get() == 0:
/hal_espressif-latest/tools/esptool_py/espefuse/efuse/esp32s3beta2/
Doperations.py193 sdio_tieh = efuses["VDD_SPI_TIEH"]
204 "Can't set regulator to 1.8V is VDD_SPI_TIEH efuse is already burned"
219 "by burning additional efuse VDD_SPI_TIEH"
222 "The following efuses are burned: VDD_SPI_FORCE, VDD_SPI_XPD, VDD_SPI_TIEH."
Dfields.py300 elif self["VDD_SPI_TIEH"].get() == 0:
/hal_espressif-latest/components/efuse/esp32s3/
Desp_efuse_table.csv31 WR_DIS.VDD_SPI_TIEH, EFUSE_BLK0, 3, 1, [] wr_dis of VDD_SPI_TIEH
147 VDD_SPI_TIEH, EFUSE_BLK0, 69, 1, [] If VDD_SPI_FORCE is 1; de…
Desp_efuse_table.c87 {EFUSE_BLK0, 3, 1}, // [] wr_dis of VDD_SPI_TIEH,
550 static const esp_efuse_desc_t VDD_SPI_TIEH[] = { variable
1017 &WR_DIS_VDD_SPI_TIEH[0], // [] wr_dis of VDD_SPI_TIEH
1597 …&VDD_SPI_TIEH[0], // [] If VDD_SPI_FORCE is 1; determines VDD_SPI voltage {0: "VDD_SPI connec…
/hal_espressif-latest/components/hal/esp32s2/include/hal/
Defuse_ll.h92 return EFUSE.rd_repeat_data1.vdd_spi_tieh; in efuse_ll_get_sdio_tieh()
/hal_espressif-latest/tools/esptool_py/esptool/targets/
Desp32.py55 VDD_SPI_TIEH = 1 << 15 # XPD_SDIO_TIEH variable in ESP32ROM
336 if efuse & (self.VDD_SPI_FORCE | self.VDD_SPI_XPD | self.VDD_SPI_TIEH):
Desp32s2.py108 VDD_SPI_TIEH = 1 << 5 variable in ESP32S2ROM
Desp32s3.py124 VDD_SPI_TIEH = 1 << 5 variable in ESP32S3ROM
/hal_espressif-latest/tools/esptool_py/docs/en/espefuse/
Dset-flash-voltage-cmd.rst8 {IDF_TARGET_VDD_TIEH:default="VDD_SPI_TIEH",esp32="XPD_SDIO_TIEH"}
/hal_espressif-latest/tools/esptool_py/docs/en/espefuse/inc/
Dsummary_ESP32-S2.rst162 …VDD_SPI_TIEH (BLOCK0) If VDD_SPI_FORCE is 1; determines VDD_SPI volta…
Dsummary_ESP32-S3.rst153 …VDD_SPI_TIEH (BLOCK0) If VDD_SPI_FORCE is 1; determines VDD_SPI volta…
/hal_espressif-latest/tools/esptool_py/espefuse/efuse_defs/
Desp32s2.yaml29 …VDD_SPI_TIEH : {show: y, blk : 0, word: 2, pos : 5, len : 1, start : 69, type …
30 … dict : '', desc: Set this bit to use XPD_VDD_PSI_REG and VDD_SPI_TIEH to configure VD…
Desp32s3.yaml27 …VDD_SPI_TIEH : {show: y, blk : 0, word: 2, pos : 5, len : 1, start : 69, type…
/hal_espressif-latest/components/soc/esp32s2/include/soc/
Defuse_struct.h289 /** vdd_spi_tieh : RO; bitpos: [5]; default: 0;
293 uint32_t vdd_spi_tieh:1; member
295 * Set this bit to use XPD_VDD_PSI_REG and VDD_SPI_TIEH to configure VDD_SPI LDO.
Defuse_reg.h355 * Set this bit to use XPD_VDD_PSI_REG and VDD_SPI_TIEH to configure VDD_SPI LDO.
/hal_espressif-latest/components/soc/esp32s3/include/soc/
Defuse_struct.h283 /** vdd_spi_tieh : RO; bitpos: [5]; default: 0;
286 uint32_t vdd_spi_tieh:1; member
/hal_espressif-latest/tools/esptool_py/test/
Dtest_espefuse.py533 "Can't set regulator to 1.8V is VDD_SPI_TIEH efuse is already burned"