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/Zephyr-latest/doc/_static/images/
Dlogo-readme-light.svg1 <?xml version="1.0" encoding="UTF-8" standalone="no"?>
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Dlogo-readme-dark.svg1 <?xml version="1.0" encoding="UTF-8" standalone="no"?>
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Dlogo.svg1 <?xml version="1.0" encoding="UTF-8" standalone="no"?>
29 …s-6{fill:url(#linear-gradient-3);}.cls-7{fill:url(#linear-gradient-4);}.cls-8{fill:#2d3136;}</styl…
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139 class="cls-8"
140 …19883,-21.44631 8.53182,0 13.00874,4.81875 4.47491,4.81926 4.47592,14.03724 v 4.8378 z m 16.799,-6…
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145 …V 221.175 h -9.828 v -55.00617 h 9.06618 v 3.92357 a 23.592,23.592 0 0 1 5.77107,-3.71406 16.89719…
149 class="cls-8"
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/Zephyr-latest/doc/_doxygen/
Dlogo.svg1 <?xml version="1.0" encoding="UTF-8" standalone="no"?>
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149 class="cls-8"
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/Zephyr-latest/boards/native/doc/
Dlayering_natsim.svg1 <?xml version="1.0" encoding="UTF-8" standalone="no"?>
17 xmlns:v="http://schemas.microsoft.com/visio/2003/SVGExtensions/"><defs
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/Zephyr-latest/tests/bsim/bluetooth/audio/test_scripts/
Dcap_unicast_ac_11_ii.sh19 -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=0 -testid=cap_initiator_ac_11_ii \
23 -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=1 -testid=cap_acceptor_unicast \
27 -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=2 -testid=cap_acceptor_unicast \
31 Execute ./bs_2G4_phy_v1 -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} \
39 Execute_AC_11_II 8_1_1 8_1_1
40 Execute_AC_11_II 8_2_1 8_2_1
Dcap_unicast_ac_7_ii.sh19 -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=0 -testid=cap_initiator_ac_7_ii \
23 -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=1 -testid=cap_acceptor_unicast \
27 -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=2 -testid=cap_acceptor_unicast \
31 Execute ./bs_2G4_phy_v1 -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} \
39 Execute_AC_7_II 8_1_1 8_1_1
40 Execute_AC_7_II 8_2_1 8_2_1
Dcap_unicast_ac_8_ii.sh19 -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=0 -testid=cap_initiator_ac_8_ii \
23 -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=1 -testid=cap_acceptor_unicast \
27 -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=2 -testid=cap_acceptor_unicast \
31 Execute ./bs_2G4_phy_v1 -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} \
39 Execute_AC_8_II 8_1_1 8_1_1
40 Execute_AC_8_II 8_2_1 8_2_1
Dcap_unicast_ac_3.sh20 -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=0 -testid=cap_initiator_ac_3 \
24 -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=1 -testid=cap_acceptor_unicast \
28 Execute ./bs_2G4_phy_v1 -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} \
36 Execute_AC_3 8_1_1 8_1_1
37 Execute_AC_3 8_2_1 8_2_1
Dcap_unicast_ac_5.sh20 -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=0 -testid=cap_initiator_ac_5 \
24 -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=1 -testid=cap_acceptor_unicast \
28 Execute ./bs_2G4_phy_v1 -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} \
34 Execute_AC_5 8_1_1 8_1_1
35 Execute_AC_5 8_2_1 8_2_1
Dcap_unicast_ac_7_i.sh19 -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=0 -testid=cap_initiator_ac_7_i \
23 -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=1 -testid=cap_acceptor_unicast \
27 Execute ./bs_2G4_phy_v1 -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} \
35 Execute_AC_7_I 8_1_1 8_1_1
36 Execute_AC_7_I 8_2_1 8_2_1
Dcap_broadcast_ac_12.sh19 -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=0 -testid=cap_initiator_ac_12 \
23 -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=1 -testid=cap_acceptor_broadcast \
27 Execute ./bs_2G4_phy_v1 -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} \
36 Execute_AC_12 8_1_1
37 Execute_AC_12 8_2_1
54 Execute_AC_12 8_1_2
55 Execute_AC_12 8_2_2
Dcap_unicast_ac_11_i.sh19 -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=0 -testid=cap_initiator_ac_11_i \
23 -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=1 -testid=cap_acceptor_unicast \
27 Execute ./bs_2G4_phy_v1 -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} \
35 Execute_AC_11_I 8_1_1 8_1_1
36 Execute_AC_11_I 8_2_1 8_2_1
Dcap_unicast_ac_8_i.sh19 -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=0 -testid=cap_initiator_ac_8_i \
23 -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=1 -testid=cap_acceptor_unicast \
27 Execute ./bs_2G4_phy_v1 -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} \
35 Execute_AC_8_I 8_1_1 8_1_1
36 Execute_AC_8_I 8_2_1 8_2_1
Dcap_broadcast_ac_13.sh19 -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=0 -testid=cap_initiator_ac_13 \
23 -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=1 -testid=cap_acceptor_broadcast \
27 Execute ./bs_2G4_phy_v1 -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} \
35 Execute_AC_13 8_1_1
36 Execute_AC_13 8_2_1
53 # Execute_AC_13 8_1_2 # BT_ISO_FLAGS_ERROR
54 # Execute_AC_13 8_2_2 # BT_ISO_FLAGS_ERROR
Dcap_broadcast_ac_14.sh19 -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=0 -testid=cap_initiator_ac_14 \
23 -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=1 -testid=cap_acceptor_broadcast \
27 Execute ./bs_2G4_phy_v1 -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} \
36 Execute_AC_14 8_1_1
37 Execute_AC_14 8_2_1
56 Execute_AC_14 8_1_2
57 Execute_AC_14 8_2_2
Dcap_unicast_ac_6_ii.sh19 -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=0 -testid=cap_initiator_ac_6_ii \
23 -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=1 -testid=cap_acceptor_unicast \
27 -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=2 -testid=cap_acceptor_unicast \
31 Execute ./bs_2G4_phy_v1 -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} \
39 Execute_AC_6_II 8_1_1
40 Execute_AC_6_II 8_2_1
Dcap_unicast_ac_9_ii.sh19 -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=0 -testid=cap_initiator_ac_9_ii \
23 -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=1 -testid=cap_acceptor_unicast \
27 -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=2 -testid=cap_acceptor_unicast \
31 Execute ./bs_2G4_phy_v1 -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} \
39 Execute_AC_9_II 8_1_1
40 Execute_AC_9_II 8_2_1
Dcap_unicast_ac_4.sh19 -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=0 -testid=cap_initiator_ac_4 \
23 -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=1 -testid=cap_acceptor_unicast \
27 Execute ./bs_2G4_phy_v1 -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} \
33 Execute_AC_4 8_1_1
34 Execute_AC_4 8_2_1
Dcap_unicast_ac_6_i.sh19 -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=0 -testid=cap_initiator_ac_6_i \
23 -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=1 -testid=cap_acceptor_unicast \
27 Execute ./bs_2G4_phy_v1 -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} \
33 Execute_AC_6_I 8_1_1
34 Execute_AC_6_I 8_2_1
/Zephyr-latest/include/zephyr/arch/riscv/
Delf.h36 #define R_RISCV_TLS_DTPREL32 8
95 * "wordclass" from RISC-V specification
112 /** @brief Generate mask for immediate in B-type RISC-V instruction
120 (R_RISCV_IMM8_GET_BIT(imm8, 9) << 29) | (R_RISCV_IMM8_GET_BIT(imm8, 8) << 28) | \
124 (R_RISCV_IMM8_GET_BIT(imm8, 1) << 8) | (R_RISCV_IMM8_GET_BIT(imm8, 11) << 7))
126 /** @brief Generate mask for immediate in J-type RISC-V instruction
134 (R_RISCV_IMM8_GET_BIT(imm8, 9) << 29) | (R_RISCV_IMM8_GET_BIT(imm8, 8) << 28) | \
144 /** @brief Generate mask for immediate in S-type RISC-V instruction
151 (R_RISCV_IMM8_GET_BIT(imm8, 9) << 29) | (R_RISCV_IMM8_GET_BIT(imm8, 8) << 28) | \
155 (R_RISCV_IMM8_GET_BIT(imm8, 1) << 8) | (R_RISCV_IMM8_GET_BIT(imm8, 0) << 7))
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/Zephyr-latest/soc/nxp/s32/s32k3/
Dpmc.c15 #define PMC_LVSC_HVDAF(v) FIELD_PREP(PMC_LVSC_HVDAF_MASK, (v)) argument
17 #define PMC_LVSC_HVDBF(v) FIELD_PREP(PMC_LVSC_HVDBF_MASK, (v)) argument
19 #define PMC_LVSC_HVD25F(v) FIELD_PREP(PMC_LVSC_HVD25F_MASK, (v)) argument
21 #define PMC_LVSC_HVD11F(v) FIELD_PREP(PMC_LVSC_HVD11F_MASK, (v)) argument
23 #define PMC_LVSC_LVD5AF(v) FIELD_PREP(PMC_LVSC_LVD5AF_MASK, (v)) argument
25 #define PMC_LVSC_LVD15F(v) FIELD_PREP(PMC_LVSC_LVD15F_MASK, (v)) argument
26 #define PMC_LVSC_HVDAS_MASK BIT(8)
27 #define PMC_LVSC_HVDAS(v) FIELD_PREP(PMC_LVSC_HVDAS_MASK, (v)) argument
29 #define PMC_LVSC_HVDBS(v) FIELD_PREP(PMC_LVSC_HVDBS_MASK, (v)) argument
31 #define PMC_LVSC_HVD25S(v) FIELD_PREP(PMC_LVSC_HVD25S_MASK, (v)) argument
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Dpinctrl_soc.h17 #define SIUL2_MSCR_SSS(v) FIELD_PREP(SIUL2_MSCR_SSS_MASK, (v)) argument
19 #define SIUL2_MSCR_SMC(v) FIELD_PREP(SIUL2_MSCR_SMC_MASK, (v)) argument
21 #define SIUL2_MSCR_IFE(v) FIELD_PREP(SIUL2_MSCR_IFE_MASK, (v)) argument
22 #define SIUL2_MSCR_DSE_MASK BIT(8)
23 #define SIUL2_MSCR_DSE(v) FIELD_PREP(SIUL2_MSCR_DSE_MASK, (v)) argument
25 #define SIUL2_MSCR_PUS(v) FIELD_PREP(SIUL2_MSCR_PUS_MASK, (v)) argument
27 #define SIUL2_MSCR_PUE(v) FIELD_PREP(SIUL2_MSCR_PUE_MASK, (v)) argument
29 #define SIUL2_MSCR_SRC(v) FIELD_PREP(SIUL2_MSCR_SRC_MASK, (v)) argument
31 #define SIUL2_MSCR_PKE(v) FIELD_PREP(SIUL2_MSCR_PKE_MASK, (v)) argument
33 #define SIUL2_MSCR_INV(v) FIELD_PREP(SIUL2_MSCR_INV_MASK, (v)) argument
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/Zephyr-latest/soc/microchip/mec/mec172x/reg/
Dmec172x_espi_vw.h18 #define ESPI_M2SW0_MTOS_SRC_POS 8u
33 #define ESPI_M2SW1_SRC1_SEL_POS 8
40 #define ESPI_M2SW1_SRC_SEL_POS(n) ((n) * 8u)
41 #define ESPI_M2SW1_SRC_SEL_MASK(n) SHLU32(0xfu, ((n) * 8u))
42 #define ESPI_M2SW1_SRC_SEL_VAL(n, v) SHLU32(((v) & 0xfu), ((n) * 8u)) argument
44 #define ESPI_M2SW2_OFS 8u
48 #define ESPI_M2SW2_SRC1_POS 8u
55 #define ESPI_M2SW2_SRC_POS(n) ((n) * 8u)
56 #define ESPI_M2SW2_SRC_MASK(n) SHLU32(0xfu, ((n) * 8u))
57 #define ESPI_M2SW2_SRC_VAL(n, v) SHLU32(((v) & 0xfu), ((n) * 8u)) argument
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/Zephyr-latest/arch/riscv/
DKconfig24 bool "RISC-V global pointer relative addressing"
31 Note: To support this feature, RISC-V SoC needs to initialize
51 This is for RISC-V implementations that require every mret to be
52 balanced with an ecall. This is not required by the RISC-V spec
57 prompt "RISC-V SMP IPI implementation"
94 Option selected by SoCs implementing the RISC-V privileged ISA.
143 the RISC-V SoC needs to do something different and more than reading and
153 the RISC-V SoC needs to do something different and more than reading and
176 end in a semicolon, for portability. The generic RISC-V
276 For RISC-V systems such as MPFS and FU540 this would be set to 1 to
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