18 #define ESPI_M2SW0_MTOS_SRC_POS		8u
33 #define ESPI_M2SW1_SRC1_SEL_POS		8
40 #define ESPI_M2SW1_SRC_SEL_POS(n)	((n) * 8u)
41 #define ESPI_M2SW1_SRC_SEL_MASK(n)	SHLU32(0xfu, ((n) * 8u))
42 #define ESPI_M2SW1_SRC_SEL_VAL(n, v)	SHLU32(((v) & 0xfu), ((n) * 8u))  argument
44 #define ESPI_M2SW2_OFS			8u
48 #define ESPI_M2SW2_SRC1_POS		8u
55 #define ESPI_M2SW2_SRC_POS(n)		((n) * 8u)
56 #define ESPI_M2SW2_SRC_MASK(n)		SHLU32(0xfu, ((n) * 8u))
57 #define ESPI_M2SW2_SRC_VAL(n, v)	SHLU32(((v) & 0xfu), ((n) * 8u))  argument
82 #define ESPI_S2MW0_STOM_POS		8u
83 #define ESPI_S2MW0_STOM_SRC_POS		8u
108 #define ESPI_S2MW1_CHG(v, n)		\  argument
109 	(((uint32_t)(v) >> ESPI_S2MW1_CHG_POS(n)) & 0x01)
115 #define ESPI_S2MW1_SRC1_POS		8u
123 #define ESPI_S2MW1_SRC(v, n)		\  argument
124 	SHLU32(((uint32_t)(v) & 0x01), (ESPI_S2MW1_SRC_POS(n)))
150 #define MSVW_SRC0_OFS		8u
167 #define MEC_MSVW_SRC1_IRQ_SEL_POS	8u
193 	((uint32_t)(isel) << ((src) * 8u))
196 #define MEC_MSVW_SRC1_POS	8u
203 #define MEC_MSVW_SRC1_MASK	BIT(8)
212 	((uint32_t)(val & 0x01u) << ((src) * 8u))
332 	volatile uint8_t THVWB[8];