Lines Matching +full:8 +full:v

24 	bool "RISC-V global pointer relative addressing"
31 	  Note: To support this feature, RISC-V SoC needs to initialize
51 	  This is for RISC-V implementations that require every mret to be
52 	  balanced with an ecall. This is not required by the RISC-V spec
57 	prompt "RISC-V SMP IPI implementation"
94 	  Option selected by SoCs implementing the RISC-V privileged ISA.
143 	  the RISC-V SoC needs to do something different and more than reading and
153 	  the RISC-V SoC needs to do something different and more than reading and
176 	    end in a semicolon, for portability. The generic RISC-V
276 	  For RISC-V systems such as MPFS and FU540 this would be set to 1 to
284 	  For RISC-V systems with HART ID starting from non-zero value,
285 	  i.e. 128, 129, ..(0x80, 8x81, ..), this can be configured to 63 (0x7f)
297 	bool "RISC-V PMP Support"
316 	default 8
319 	  Typical values are 8 or 16.
339 	default y if (PMP_SLOTS = 8)
350 	default 8 if (PMP_NO_TOR && PMP_NO_NA4)
354 	  (ie 4, 8, 16, ...), but if neither TOR mode nor NA4 mode is
355 	  supported, the minimum granularity is 8.
403 	  According to the RISC-V Instruction Set Manual: Volume II, Version 20240411
427 	int "Alignment of RISC-V trap handler in bytes"
431 	  This value configures the alignment of RISC-V trap handling
433 	  the format of MTVEC register which is RISC-V platform-specific.