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/Zephyr-latest/dts/bindings/clock/
Dmicrochip,xec-pcr.yaml23 default value is 480 for 100 kHz.
25 pll-32k-src:
28 description: 32 KHz clock source for PLL
30 periph-32k-src:
33 description: 32 KHz clock source for peripherals
43 32KHz clock monitor minimum valid 32KHz period in 48MHz units
49 32KHz clock monitor maximum valid 32KHz period in 48MHz units
56 the measured 32KHz high and low pulse widths.
62 Minimum number of consecutive 32KHz pulses that pass all monitor tests
86 If the internal silicon 32KHz oscillator is not chosen as the source
[all …]
Despressif,esp32-rtc.yaml31 - 0: ESP32_RTC_SLOW_CLK_SRC_RC_SLOW - 136 KHz (C3/S3) - 90 kHz (S2) - 150 kHz (ESP32)
32 - 1: ESP32_RTC_SLOW_CLK_SRC_XTAL32K - 32,768U KHz
34 - 9: ESP32_RTC_SLOW_CLK_32K_EXT_OSC - External 32k oscillator connected to 32K_XP pin
Dst,stm32-msi-clock.yaml18 - 0 # range 0 around 100 kHz
19 - 1 # range 1 around 200 kHz
20 - 2 # range 2 around 400 kHz
21 - 3 # range 3 around 800 kHz
28 - 10 # range 10 around 32 MHz
/Zephyr-latest/samples/drivers/clock_control_xec/
DREADME.rst9 This sample demonstrates configuring the 32KHz clock
20 GPIO221 alternate function 1 is 32KHZ_OUT and can be monitored on Assembly 6915 JP7 pin 5.
22 Internal Silicon 32KHz Oscillator jumper configuration
28 Dual-ended 32KHz Crystal jumper configuration
36 Remove jumper on JP121 to prevent U15 32KHz 50% duty waveform
39 External single-ended 32KHz waveform to MEC172x XTAL2 input
43 Jumper on JP2 1-2 connect external 32KHz signal to XTAL2
47 Jumper on JP121 pins 3-4 connect U15 32KHz output to
50 External single-ended 32KHz waveform to MEC172x 32KHZ_IN pin
58 Jumper on JP121 pins 1-2 connect U15 32KHz output to
[all …]
/Zephyr-latest/dts/bindings/pwm/
Dmicrochip,xec-pwmbbled.yaml31 Clock source selection: 32 KHz is available in deep sleep.
33 - PWM_BBLED_CLK_32K: Clock source is the 32KHz domain
47 enable-low-power-32k:
52 - 32KHz Core clock (32.768KHz)
54 PCR(Power, Clock and Reset) block. But 32KHz Core clock will be available to BBLED.
56 Property "enable-low-power-32k" shall be used along with 32KHz clock to blink (or) not blink
/Zephyr-latest/samples/drivers/clock_control_xec/src/
Dmain.c28 LOG_INF("PCR Power Reset Status register(bit[10] is 32K_ACTIVE) = 0x%x", r); in pcr_clock_regs()
48 LOG_INF("32KHz clock source is XTAL"); in vbat_clock_regs()
51 " (external 32KHz waveform)"); in vbat_clock_regs()
57 LOG_INF("32KHz clock source is the Internal Silicon 32KHz OSC"); in vbat_clock_regs()
60 LOG_INF("32KHz clock domain uses the 32KHZ_IN pin(GPIO_0165 F1)"); in vbat_clock_regs()
62 LOG_INF("32KHz clock domain uses the 32KHz clock source"); in vbat_clock_regs()
65 LOG_INF("32KHz trim = 0x%08x", vbr->CKK32_TRIM); in vbat_clock_regs()
88 LOG_INF("PLL 32K clock source is Internal Silicon OSC(VTR)"); in print_pll_clock_src()
90 LOG_INF("PLL 32K clock source is XTAL input(VTR)"); in print_pll_clock_src()
92 LOG_INF("PLL 32K clock source is 32KHZ_IN pin(VTR)"); in print_pll_clock_src()
[all …]
/Zephyr-latest/soc/atmel/sam0/common/
DKconfig.samd5x7 bool "The external 32 kHz crystal oscillator"
9 Say y to enable the external 32 kHZ crystal oscillator at
15 hex "Startup time external 32 kHz crystal oscillator"
19 Selects the startup time for the external 32 kHz crystal oscillator.
DKconfig.samd2x13 bool "Internal 32.768 kHz RC oscillator"
15 Enable the internal 32.768 kHz RC oscillator at startup.
25 bool "External 32.768 kHz clock source"
27 Enable the external 32.768 kHz clock source at startup.
31 bool "External 32.768 kHz clock is a crystal oscillator"
39 bool "External 0.4..32 MHz clock source"
41 Enable the external 0.4..32 MHz clock source at startup.
45 bool "External 0.4..32 MHz clock is a crystal oscillator"
53 int "External 0.4..32 MHz clock oscillator frequency"
58 External 0.4..32 MHz clock oscillator reference frequency.
/Zephyr-latest/dts/bindings/timer/
Dmicrochip,mec5-ktimer.yaml6 the 32kHz 32-bit RTOS timer with 32-bit basic timer 5.
23 description: RTOS timer runs at fixed 32 KHz.
/Zephyr-latest/drivers/clock_control/
Dclock_control_mchp_xec.c30 * 32KHz period counter minimum for pass/fail: 16-bit
31 * 32KHz period counter maximum for pass/fail: 16-bit
32 * 32KHz duty cycle variation max for pass/fail: 16-bit
33 * 32KHz valid count minimum: 8-bit
37 * One 32KHz clock pulse = 1464.84 48 MHz counts.
156 #define XEC_CC_VBATR_CS_XTAL_SE BIT(9) /* crystal XTAL2 used as 32KHz input */
162 /* MEC172x Select source of peripheral 32KHz clock */
168 #define XEC_CC_VBATR_CS_PCS_VTR_PIN_SO 0x20000u /* VTR 32KHZ_IN, VBAT silicon OSC */
169 #define XEC_CC_VBATR_CS_PCS_VTR_PIN_XTAL 0x30000u /* VTR 32KHZ_IN, VBAT XTAL */
190 uint16_t period_min; /* mix and max 32KHz period range */
[all …]
/Zephyr-latest/drivers/crypto/
DKconfig.ataes132a7 bool "Atmel ATAES132A 32k AES Serial EEPROM support"
12 Enable Atmel ATAES132A 32k AES Serial EEPROM support.
23 Standard bis speed of up to 100KHz.
28 Fast bus speed of up to 400KHz.
/Zephyr-latest/include/zephyr/dt-bindings/clock/
Dmchp_xec_pcr.h10 /* PLL 32KHz clock source VTR rail ON. */
15 /* Peripheral 32KHz clock source for VTR rail ON and off(VBAT operation) */
/Zephyr-latest/dts/bindings/espi/
Dmicrochip,xec-espi-saf.yaml22 description: poll flash busy timeout in 32KHz periods
38 description: force suspended erase or program to resume in 32KHz periods
Dmicrochip,xec-espi-saf-v2.yaml28 description: poll flash busy timeout in 32KHz periods
44 description: force suspended erase or program to resume in 32KHz periods
/Zephyr-latest/soc/microchip/mec/mec172x/reg/
Dmec172x_pcr.h117 /* PCR Slow Clock Control. Clock divider for 100KHz clock domain */
276 /* VTR Source 32 KHz Clock (Offset +8Ch) */
284 * Clock monitor 32KHz period counter (Offset +C0h, RO)
285 * Clock monitor 32KHz high counter (Offset +C4h, RO)
286 * Clock monitor 32KHz period counter minimum (Offset +C8h, RW)
287 * Clock monitor 32KHz period counter maximum (Offset +CCh, RW)
288 * Clock monitor 32KHz Duty Cycle variation counter (Offset +D0h, RO)
289 * Clock monitor 32KHz Duty Cycle variation counter maximum (Offset +D4h, RW)
294 * Clock monitor 32KHz Valid Count (Offset +0xD8, RO)
295 * Clock monitor 32KHz Valid Count minimum (Offset +0xDC, RW)
[all …]
Dmec172x_vbat.h33 /* Offset 0x08 32K Clock Source register */
44 /* Enable and start internal 32KHz Silicon Oscillator */
57 /* Select source of peripheral 32KHz clock */
64 /* 32K silicon OSC when chip powered by VBAT or VTR */
66 /* 32K external crystal when chip powered by VBAT or VTR */
68 /* 32K input pin on VTR. Switch to Silicon OSC on VBAT */
70 /* 32K input pin on VTR. Switch to crystal on VBAT */
72 /* Disable internal 32K VBAT clock source when VTR is off */
77 * Monotonic Counter least significant word (32-bit), read-only.
82 /* Monotonic Counter most significant word (32-bit). Read-Write */
/Zephyr-latest/drivers/timer/
DKconfig.mec514 The 32-bit 32 KHz based RTOS timer which is operational in
16 32-bit down counter with frequency divider used for the
/Zephyr-latest/drivers/i2c/
DKconfig.it8xxx211 Supported Speeds: 100kHz, 400kHz and 1MHz.
23 The I2C controller supports two 32-bytes FIFOs,
54 range 32 2048
/Zephyr-latest/boards/holyiot/yj16019/
Dholyiot_yj16019_defconfig3 # 32kHz clock source
/Zephyr-latest/boards/ezurio/bl654_usb/
Dbl654_usb_defconfig16 # 32KHz clock source
/Zephyr-latest/dts/bindings/watchdog/
Dgd,gd32-fwdgt.yaml30 the low-speed internal RC oscillator frequency is 32kHz or 40kHz.
/Zephyr-latest/boards/adafruit/feather_nrf52840/
Dadafruit_feather_nrf52840_nrf52840_sense_defconfig16 # 32kHz clock source
/Zephyr-latest/boards/ezurio/bt510/
Dbt510_defconfig16 # 32KHz clock source
/Zephyr-latest/boards/ezurio/bl654_sensor_board/
Dbl654_sensor_board_defconfig17 # 32KHz clock source
/Zephyr-latest/boards/ezurio/bl653_dvk/
Dbl653_dvk_defconfig20 # 32kHz clock source

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