Lines Matching +full:32 +full:khz
30 * 32KHz period counter minimum for pass/fail: 16-bit
31 * 32KHz period counter maximum for pass/fail: 16-bit
32 * 32KHz duty cycle variation max for pass/fail: 16-bit
33 * 32KHz valid count minimum: 8-bit
37 * One 32KHz clock pulse = 1464.84 48 MHz counts.
156 #define XEC_CC_VBATR_CS_XTAL_SE BIT(9) /* crystal XTAL2 used as 32KHz input */
162 /* MEC172x Select source of peripheral 32KHz clock */
168 #define XEC_CC_VBATR_CS_PCS_VTR_PIN_SO 0x20000u /* VTR 32KHZ_IN, VBAT silicon OSC */
169 #define XEC_CC_VBATR_CS_PCS_VTR_PIN_XTAL 0x30000u /* VTR 32KHZ_IN, VBAT XTAL */
190 uint16_t period_min; /* mix and max 32KHz period range */
193 uint8_t xtal_se; /* External 32KHz square wave on XTAL2 pin */
194 uint8_t max_dc_va; /* 32KHz monitor maximum duty cycle variation */
195 uint8_t min_valid; /* minimum number of valid consecutive 32KHz pulses */
221 * its reference clock. Available peripheral timers using 32KHz are:
227 * one 32KHz cycle to move pre-load into count register.
229 * Hibernation timer is using the chosen 32KHz source. If the external 32KHz source
267 /* MEC15xx uses the same 32KHz source for both PLL and Peripheral 32K clock domains.
269 * If XTAL is selected (parallel) or single-ended the external 32KHz MUST stay on
271 * If PIN(32KHZ_IN pin) as the external source, hardware can auto-switch to internal
272 * silicon OSC if the signal on the 32KHZ_PIN goes away.
303 case PLL_CLK32K_SRC_PIN: /* 32KHZ_IN pin falls back to Silicon OSC */ in soc_clk32_init()
390 /* caller has enabled internal silicon 32 KHz oscillator */
408 htmr0->CTRL = 0; /* 32k time base */ in hib_timer_delay()
444 * Start external 32 KHz crystal.
546 * Set the clock source for either PLL or Peripheral-32K clock domain.
547 * The source must be a stable 32 KHz input: internal silicon oscillator,
549 * or a 50% duty cycles waveform on the 32KHZ_PIN.
550 * NOTE: 32KHZ_PIN is an alternate function of a chip specific GPIO.
551 * Signal on 32KHZ_PIN may go off when VTR rail go down. MEC172x can automatically
553 * when using 32KHZ_PIN.
554 * !!! IMPORTANT !!! Fall back from 32KHZ_PIN to SO/XTAL is only for the Peripheral
555 * Clock domain. If the PLL is configured to use 32KHZ_PIN as its source then the
606 /* two bit field in PCR VTR 32KHz source register */
631 /* two bit field in VBAT source 32KHz register */
654 * MEC172x has two 32 KHz clock domains
655 * PLL domain: 32 KHz clock input for PLL to produce 96 MHz and 48 MHz clocks
656 * Peripheral domain: 32 KHz clock for subset of peripherals.
657 * Each domain 32 KHz clock input can be from one of the following sources:
660 * External 32KHZ_PIN 50% duty cycle waveform with fall back to either
661 * Silicon OSC or crystal when 32KHZ_PIN signal goes away or VTR power rail
665 * If no VBAT reset occurs the VBAT 32 KHz source register maintains its state.
677 /* disable PCR 32K monitor and clear counters */ in soc_clk32_init()
687 /* Default to 32KHz Silicon OSC for PLL and peripherals */ in soc_clk32_init()
693 LOG_ERR("XEC clock control: MEC172x lock timeout for internal 32K OSC"); in soc_clk32_init()
697 /* If crystal input required, enable and check. Single-ended 32KHz square wave in soc_clk32_init()
776 * slp_idx = zero based index into 32-bit PCR sleep enable registers.
785 if ((slp_idx >= MCHP_MAX_PCR_SCR_REGS) || (slp_pos >= 32)) { in z_mchp_xec_pcr_periph_sleep()
806 if ((slp_idx >= MCHP_MAX_PCR_SCR_REGS) || (slp_pos >= 32)) { in z_mchp_xec_pcr_periph_reset()
900 * turned off. Exception is 32 KHz clock.
936 * Two main clock domains: PLL and Peripheral-32K. Each domain's 32 KHz source
940 * external 32 KHz 50% duty cycle waveform on 32KHZ_IN pin.
942 * peripherals except those in the Peripheral-32K clock domain. The slow clock
948 * Peripheral-32K domain peripherals:
951 * Peripherals using both PLL and 32K clock domains: