Searched +full:2 +full:- +full:cell (Results 1 – 25 of 92) sorted by relevance
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9 * SPDX-License-Identifier: Apache-2.020 * @defgroup devicetree-clocks Devicetree Clocks API26 * @brief Test if a node has a clocks phandle-array property at a given index28 * This expands to 1 if the given index is valid clocks property phandle-array index.33 * n1: node-1 {37 * n2: node-2 {45 * DT_CLOCKS_HAS_IDX(DT_NODELABEL(n1), 2) // 049 * @param idx index of a clocks property phandle-array whose existence to check56 * @brief Test if a node has a clock-names array property holds a given name58 * This expands to 1 if the name is available as clocks-name array property cell.[all …]
9 * SPDX-License-Identifier: Apache-2.020 * @defgroup devicetree-dmas Devicetree DMA API36 * dmas = <&dma1 1 2 0x400 0x3>,64 * dmas = <&dma1 1 2 0x400 0x3>,66 * dma-names = "tx", "rx";75 * @param name lowercase-and-underscores name of a dmas element76 * as defined by the node's dma-names property109 * @param name lowercase-and-underscores name of a dmas element110 * as defined by the node's dma-names property127 * @brief Get a DMA specifier's cell value at an index[all …]
10 * SPDX-License-Identifier: Apache-2.021 * @defgroup devicetree-gpio Devicetree GPIO API28 * gpio phandle-array property at an index46 * @param gpio_pha lowercase-and-underscores GPIO property with47 * type "phandle-array"59 * @param gpio_pha lowercase-and-underscores GPIO property with60 * type "phandle-array"69 * @brief Get a GPIO specifier's pin cell at an index78 * #gpio-cells = <2>;83 * #gpio-cells = <2>;[all …]
9 * SPDX-License-Identifier: Apache-2.020 * @defgroup devicetree-pwms Devicetree PWMs API31 * pwm1: pwm-controller@... { ... };33 * pwm2: pwm-controller@... { ... };60 * pwm1: pwm-controller@... { ... };62 * pwm2: pwm-controller@... { ... };67 * pwm-names = "alpha", "beta";76 * @param name lowercase-and-underscores name of a pwms element77 * as defined by the node's pwm-names property94 * @brief Get PWM specifier's cell value at an index[all …]
1 .. zephyr:code-sample:: eth-ivshmem2 :name: Inter-VM Shared Memory (ivshmem) Ethernet3 :relevant-api: ivshmem ethernet5 Communicate with another "cell" in the Jailhouse hypervisor using IVSHMEM Ethernet.11 another "cell" in the Jailhouse hypervisor. Currently only the qemu_cortex_a5320 .. code-block:: console22 git clone https://github.com/siemens/jailhouse-images.git23 cd jailhouse-images29 .. code-block:: console31 ./kas-container menu[all …]
6 The LS1046A reference design board (RDB) is a high-performance computing,10 of high-speed SerDes ports.12 The Layerscape LS1046A processor integrates four 64-bit Arm(R) Cortex(R) A7213 cores with packet processing acceleration and high-speed peripherals. The25 - Four 32/64-bit Arm(R) Cortex(R)V8 A72 CPUs, up to 1.6 GHz core speed26 - Supports 8 GB DDR4 SDRAM memory27 - SDHC port connects directly to an adapter card slot, featuring 4 GB eMMCi29 - One 512 MB SLC NAND flash with ECC support (1.8 V)30 - CPLD connection: 8-bit registers in CPLD to configure mux/demux selections31 - Support two 64 MB onboard QSPI NOR flash memories[all …]
4 # SPDX-License-Identifier: Apache-2.063 int "Transparency grid cell size"69 hex "Transparency grid cell color 1"75 hex "Transparency grid cell color 2"
3 compatible: "atmel,sam0-dmac"5 include: dma-controller.yaml14 "#dma-cells":15 const: 217 # #dma-cells : Must be <2>.18 # The 1st cell specifies the DMAC channel to be used for the data transfer.21 # The 2nd cell defines the peripheral trigger which is the source of the transfer.31 # dma-names = "rx", "tx";37 dma-cells:38 - channel[all …]
3 compatible: "microchip,xec-dmac"5 include: dma-controller.yaml24 aggregated-girq:30 "#dma-cells":31 const: 233 "pcr-cells":35 const: 237 "girq-cells":39 const: 241 # #dma-cells : Must be <2>.[all …]
2 # SPDX-License-Identifier: Apache-2.012 - bit 6-7: Direction (see dma.h)13 - 0x0: MEMORY to MEMORY14 - 0x1: MEMORY to PERIPH15 - 0x2: PERIPH to MEMORY16 - 0x3: reserved for PERIPH to PERIPH18 - bit 9: Peripheral address increase19 - 0x0: no address increment between transfers20 - 0x1: increment address between transfers22 - bit 10: Memory address increase[all …]
2 # SPDX-License-Identifier: Apache-2.06 compatible: "nxp,mcux-edma"8 include: dma-controller.yaml20 dma-channels:23 dma-requests:26 dmamux-reg-offset:33 channel-gap:47 irq-shared-offset:54 no-error-irq:62 - 2[all …]
2 # SPDX-License-Identifier: Apache-2.010 - bit 6-7: Direction (see dma.h)11 - 0x0: MEMORY to MEMORY12 - 0x1: MEMORY to PERIPH13 - 0x2: PERIPH to MEMORY14 - 0x3: reserved for PERIPH to PERIPH16 - bit 9: Peripheral address increase17 - 0x0: no address increment between transfers18 - 0x1: increment address between transfers20 - bit 10: Memory address increase[all …]
2 # SPDX-License-Identifier: Apache-2.010 described in the dma.txt file, using a four-cell specifier for each13 described in the dma.txt file, using a 3-cell specifier for each15 1. channel: the dma stream from 1 to <dma-requests>16 2. slot: DMA periph request ID, which is written in the DMAREQ_ID of the DMAMUX_CxCR17 this value is 0 for Memory-to-memory transfers18 or a value between <1> .. <dma-generators> (not supported yet)19 or a value between <dma-generators>+1 .. <dma-generators>+<dma-requests>20 3. channel-config: A 32bit mask specifying the DMA channel configuration23 -bit 5 : DMA cyclic mode config[all …]
2 # SPDX-License-Identifier: Apache-2.08 include: [dma-controller.yaml, base.yaml]13 valid-channels:18 property and "dma-channels" is the fact that this23 and "dma-channels" are mutually exclusive, meaning you26 "#dma-cells":27 const: 229 # IMPORTANT: if your EDMA version doesn't support channel MUX-ing please30 # leave the MUX cell as 0. This is not mandatory for the driver as the33 dma-cells:[all …]
4 * SPDX-License-Identifier: Apache-2.011 ESP_GDMA_TRIG_PERIPH_M2M = -1,14 ESP_GDMA_TRIG_PERIPH_UHCI0 = 2,32 #define ESP32_DT_INST_DMA_CELL(n, name, cell) \ argument34 (DT_INST_DMAS_CELL_BY_NAME(n, name, cell)), \
2 * SPDX-License-Identifier: Apache-2.039 * -----------------42 * part in DT_N_<path-id>_P_<property-id> macros, or the "prop-suf"60 * _IDX_<i>_VAL_<val>_EXISTS: cell value exists, by index64 * _NAME_<name>_VAL_<val>_EXISTS: cell value exists, by name71 * @defgroup devicetree-generic-id Node identifiers and helpers96 * The arguments to this macro are the names of non-root nodes in the98 * Non-alphanumeric characters in each name must be converted to108 * current-speed = <115200>;119 * Example usage with DT_PROP() to get the `current-speed` property:[all …]
7 processor, composed of a quad Cortex®-A53 cluster and a single Cortex®-M7 core.8 Zephyr OS is ported to run on the Cortex®-A53 core.10 - Board features:12 - RAM: 2GB LPDDR413 - Storage:15 - SanDisk 16GB eMMC5.116 - Micron 32MB QSPI NOR17 - microSD Socket18 - Wireless:20 - WiFi: 2.4/5GHz IEEE 802.11b/g/n[all …]
4 * SPDX-License-Identifier: BSD-3-Clause9 /dts-v1/;16 interrupt-parent-test {18 compatible = "interrupt-three-cell";19 #interrupt-cells = <3>;20 interrupt-controller;23 interrupts = <1 2 3 4 5 6>;24 interrupt-names = "foo", "bar";25 interrupt-parent = <&{/interrupt-parent-test/controller}>;28 interrupts-extended-test {[all …]
2 # SPDX-License-Identifier: Apache-2.06 64-byte area with 2-byte prefix and 1-byte checksum with 61 usable bytes10 compatible = "zephyr,memory-region", "mmio-sram";12 zephyr,memory-region = "RetainedMem";16 compatible = "zephyr,retained-ram";18 #address-cells = <1>;19 #size-cells = <1>;36 "#address-cells":39 Address reg cell is for the offset of the area in parent node, can be43 "#size-cells":[all …]
2 # SPDX-License-Identifier: Apache-2.06 compatible: "atmel,sam-adc"8 include: [adc-controller.yaml, pinctrl-device.yaml]25 startup-time:32 settling-time:37 or differential input parameters of the analog cell change38 between two channels, the analog cell may need a specific42 tracking-time:49 enum: [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16]51 "#io-channel-cells":[all …]
1 # Copyright (c) 2018-2019 Linaro4 # SPDX-License-Identifier: Apache-2.015 ZEPHYR_BASE = str(Path(__file__).resolve().parents[2])17 "python-devicetree", "src"))157 foo: some-node { ... };252 def _node_ph_array_prop(node, prop, index, cell, unit=None): argument255 a cell ('cell') and it will look to see if that node has a property256 called 'prop' and if that 'prop' is an phandle-array type.257 Then it will check if that phandle array has a cell matching the given index258 and then return the value of the cell named 'cell' in this array index.[all …]
4 * SPDX-License-Identifier: Apache-2.030 /** Anti-aliased points, point radius is 1-256 pixels */31 #define FT8XX_POINTS 2U33 * Anti-aliased lines, with width from 0 to 4095 1/16th of pixel units.37 /** Anti-aliased lines, connected head-to-tail */48 * Round-cornered rectangles, curvature of the corners can be adjusted using57 * - @ref FT8XX_BITMAPS58 * - @ref FT8XX_POINTS59 * - @ref FT8XX_LINES60 * - @ref FT8XX_LINE_STRIP[all …]
2 # SPDX-License-Identifier: Apache-2.016 clocks = <&pmc PMC_TYPE_PERIPHERAL p-id>;20 In this example the clock-type was defined as PMC_TYPE_PERIPHERAL and the21 peripheral-id was defined as p-id. The p-id number should be consulted on24 NOTE: The predefined clock type cell is defined at27 The clock-type constants are:34 compatible: "atmel,sam-pmc"36 include: [clock-controller.yaml, base.yaml]42 "#clock-cells":43 const: 2[all …]
4 # SPDX-License-Identifier: Apache-2.07 compatible: "st,stm32f1-clock-mco"20 pinctrl-0 = <&rcc_mco_pa8>;21 pinctrl-names = "default";25 Note: in the `clocks` property, the domain clock source cell should30 /* PLL3 clock divided by 2 */36 - name: st,stm32-clock-mco.yaml37 property-blocklist:38 - prescaler
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