Home
last modified time | relevance | path

Searched +full:15 +full:u (Results 1 – 25 of 516) sorted by relevance

12345678910>>...21

/Zephyr-latest/dts/bindings/phy/
Dst,stm32u5-otghs-phy.yaml23 clocks = <&rcc STM32_CLOCK(AHB2, 15U)>,
27 clocks = <&rcc STM32_CLOCK(AHB2, 15U)>,
31 clocks = <&rcc STM32_CLOCK(AHB2, 15U)>,
35 clocks = <&rcc STM32_CLOCK(AHB2, 15U)>,
/Zephyr-latest/soc/microchip/mec/common/
Dsoc_pins.h15 #define MCHP_GPIO_000 (0U)
16 #define MCHP_GPIO_001 (1U)
17 #define MCHP_GPIO_002 (2U)
18 #define MCHP_GPIO_003 (3U)
19 #define MCHP_GPIO_004 (4U)
20 #define MCHP_GPIO_005 (5U)
21 #define MCHP_GPIO_006 (6U)
22 #define MCHP_GPIO_007 (7U)
23 #define MCHP_GPIO_010 (8U)
24 #define MCHP_GPIO_011 (9U)
[all …]
/Zephyr-latest/include/zephyr/bluetooth/audio/
Dgmap_lc3_preset.h44 BT_AUDIO_CODEC_CFG_DURATION_7_5, _loc, 60U, 1, \
46 BT_BAP_QOS_CFG_UNFRAMED(7500u, 60U, 1U, 15U, 10000U))
56 BT_AUDIO_CODEC_CFG_DURATION_10, _loc, 80U, 1, \
58 BT_BAP_QOS_CFG_UNFRAMED(10000u, 80U, 1U, 20U, 10000U))
68 BT_AUDIO_CODEC_CFG_DURATION_7_5, _loc, 75U, 1, \
70 BT_BAP_QOS_CFG_UNFRAMED(7500u, 75U, 1U, 15U, 10000U))
82 BT_AUDIO_CODEC_CFG_DURATION_10, _loc, 100U, 1, \
84 BT_BAP_QOS_CFG_UNFRAMED(10000u, 100U, 1U, 20U, 10000U))
94 BT_AUDIO_CODEC_CFG_DURATION_7_5, _loc, 90U, 1, \
96 BT_BAP_QOS_CFG_UNFRAMED(7500u, 90U, 1U, 15U, 10000U))
[all …]
/Zephyr-latest/soc/microchip/mec/mec172x/reg/
Dmec172x_ecia.h16 #define MCHP_FIRST_GIRQ_NOS 8u
17 #define MCHP_LAST_GIRQ_NOS 26u
23 #define MCHP_ECIA_GIRQ_CLK_WAKE_ONLY 22u
29 #define MCHP_ECIA_DIRECT_BITMAP (BIT(13) | BIT(14) | BIT(15) | BIT(16) | \
36 #define MCHP_NVIC_NUM_PRI_BITS 3u
37 #define MCHP_NVIC_PRI_LO_VAL 7u
44 #define MCHP_NUM_NVIC_REGS 6u
166 #define MCHP_GPIO_0157_GIRQ_POS 15
194 #define MCHP_GPIO_0157_GIRQ_BIT BIT(15)
224 #define MCHP_GPIO_0117_GIRQ_POS 15
[all …]
/Zephyr-latest/include/zephyr/dt-bindings/pinctrl/
Dgecko-pinctrl-s1.h15 * - 15..8: Port for UART_RX/UART_TX functions.
17 * - 15..8: Reserved for UART_LOC function.
27 #define GECKO_FUN_POS 24U
32 #define GECKO_PIN_POS 0U
37 #define GECKO_PORT_POS 8U
42 #define GECKO_LOC_POS 0U
54 #define GECKO_FUN_UART_TX 0U
56 #define GECKO_FUN_UART_RX 1U
58 #define GECKO_FUN_UART_RTS 2U
60 #define GECKO_FUN_UART_CTS 3U
[all …]
Dti-cc32xx-pinctrl.h15 * - 15..10: Reserved.
32 #define TI_CC32XX_PIN_POS 16U
34 #define TI_CC32XX_MUX_POS 0U
53 #define GPIO10_P1 TI_CC32XX_PINMUX(1U, 0U)
54 #define I2C_SCL_P1 TI_CC32XX_PINMUX(1U, 1U)
55 #define GT_PWM06_P1 TI_CC32XX_PINMUX(1U, 3U)
56 #define UART1_TX_P1 TI_CC32XX_PINMUX(1U, 7U)
57 #define SDCARD_CLK_P1 TI_CC32XX_PINMUX(1U, 6U)
58 #define GT_CCP01_P1 TI_CC32XX_PINMUX(1U, 12U)
60 #define GPIO11_P2 TI_CC32XX_PINMUX(2U, 0U)
[all …]
Dnumicro-pinctrl.h10 #define NUMICRO_MFP_SHIFT 0U
12 #define NUMICRO_PIN_SHIFT 4U
14 #define NUMICRO_PORT_SHIFT 8U
27 * @param pin Pin (0..15)
28 * @param mfp Multi-function value (0..15)
Dnrf-pinctrl.h18 * - 15: Pin low power mode.
30 #define NRF_FUN_POS 24U
34 #define NRF_GPD_FAST_ACTIVE1_POS 18U
38 #define NRF_CLOCKPIN_ENABLE_POS 17U
42 #define NRF_INVERT_POS 16U
46 #define NRF_LP_POS 15U
50 #define NRF_DRIVE_POS 11U
54 #define NRF_PULL_POS 9U
58 #define NRF_PIN_POS 0U
70 #define NRF_FUN_UART_TX 0U
[all …]
Dgecko-pinctrl.h15 * - 15..8: Port for UART_RX/UART_TX functions.
17 * - 15..8: Reserved for UART_LOC function.
27 #define GECKO_FUN_POS 24U
32 #define GECKO_PIN_POS 0U
37 #define GECKO_PORT_POS 8U
42 #define GECKO_LOC_POS 0U
54 #define GECKO_FUN_UART_TX 0U
56 #define GECKO_FUN_UART_RX 1U
58 #define GECKO_FUN_UART_RTS 2U
60 #define GECKO_FUN_UART_CTS 3U
[all …]
/Zephyr-latest/include/zephyr/dt-bindings/clock/
Dgd32e50x-clocks.h30 #define GD32_CLOCK_DMA0 GD32_CLOCK_CONFIG(AHBEN, 0U)
31 #define GD32_CLOCK_DMA1 GD32_CLOCK_CONFIG(AHBEN, 1U)
32 #define GD32_CLOCK_SRAMSP GD32_CLOCK_CONFIG(AHBEN, 2U)
33 #define GD32_CLOCK_FMCSP GD32_CLOCK_CONFIG(AHBEN, 4U)
34 #define GD32_CLOCK_CRC GD32_CLOCK_CONFIG(AHBEN, 6U)
35 #define GD32_CLOCK_EXMC GD32_CLOCK_CONFIG(AHBEN, 8U)
36 #define GD32_CLOCK_USBHS GD32_CLOCK_CONFIG(AHBEN, 12U)
37 #define GD32_CLOCK_ULPI GD32_CLOCK_CONFIG(AHBEN, 13U)
38 #define GD32_CLOCK_ENET GD32_CLOCK_CONFIG(AHBEN, 14U)
39 #define GD32_CLOCK_ENETTX GD32_CLOCK_CONFIG(AHBEN, 15U)
[all …]
Dkinetis_scg.h11 #define KINETIS_SCG_SOSC_MODE_EXT 0U
12 #define KINETIS_SCG_SOSC_MODE_LOW_POWER 4U
13 #define KINETIS_SCG_SOSC_MODE_HIGH_GAIN 12U
16 #define KINETIS_SCG_CORESYS_CLK 0U
17 #define KINETIS_SCG_BUS_CLK 1U
18 #define KINETIS_SCG_FLEXBUS_CLK 2U
19 #define KINETIS_SCG_FLASH_CLK 3U
20 #define KINETIS_SCG_SOSC_CLK 4U
21 #define KINETIS_SCG_SIRC_CLK 5U
22 #define KINETIS_SCG_FIRC_CLK 6U
[all …]
Dgd32f403-clocks.h30 #define GD32_CLOCK_DMA0 GD32_CLOCK_CONFIG(AHBEN, 0U)
31 #define GD32_CLOCK_DMA1 GD32_CLOCK_CONFIG(AHBEN, 1U)
32 #define GD32_CLOCK_SRAMSP GD32_CLOCK_CONFIG(AHBEN, 2U)
33 #define GD32_CLOCK_FMCSP GD32_CLOCK_CONFIG(AHBEN, 4U)
34 #define GD32_CLOCK_CRC GD32_CLOCK_CONFIG(AHBEN, 6U)
35 #define GD32_CLOCK_EXMC GD32_CLOCK_CONFIG(AHBEN, 8U)
36 #define GD32_CLOCK_SDIO GD32_CLOCK_CONFIG(AHBEN, 10U)
37 #define GD32_CLOCK_USBFS GD32_CLOCK_CONFIG(AHBEN, 12U)
40 #define GD32_CLOCK_TIMER2 GD32_CLOCK_CONFIG(APB1EN, 1U)
41 #define GD32_CLOCK_TIMER3 GD32_CLOCK_CONFIG(APB1EN, 2U)
[all …]
/Zephyr-latest/drivers/display/
Ddisplay_ili9488.h21 #define ILI9488_FRMCTR1_LEN 2U
22 #define ILI9488_DISCTRL_LEN 3U
23 #define ILI9488_PWCTRL1_LEN 2U
24 #define ILI9488_PWCTRL2_LEN 1U
25 #define ILI9488_VMCTRL_LEN 4U
26 #define ILI9488_PGAMCTRL_LEN 15U
27 #define ILI9488_NGAMCTRL_LEN 15U
30 #define ILI9488_X_RES 320U
32 #define ILI9488_Y_RES 480U
Ddisplay_ili9340.h23 #define ILI9340_GAMSET_LEN 1U
24 #define ILI9340_FRMCTR1_LEN 2U
25 #define ILI9340_DISCTRL_LEN 3U
26 #define ILI9340_PWCTRL1_LEN 2U
27 #define ILI9340_PWCTRL2_LEN 1U
28 #define ILI9340_VMCTRL1_LEN 2U
29 #define ILI9340_VMCTRL2_LEN 1U
30 #define ILI9340_PGAMCTRL_LEN 15U
31 #define ILI9340_NGAMCTRL_LEN 15U
34 #define ILI9340_X_RES 240U
[all …]
Ddisplay_ili9342c.h30 #define ILI9342C_GAMSET_LEN 1U
31 #define ILI9342C_IFMODE_LEN 1U
32 #define ILI9342C_FRMCTR1_LEN 2U
33 #define ILI9342C_INVTR_LEN 1U
34 #define ILI9342C_DISCTRL_LEN 4U
35 #define ILI9342C_ETMOD_LEN 1U
36 #define ILI9342C_PWCTRL1_LEN 2U
37 #define ILI9342C_PWCTRL2_LEN 1U
38 #define ILI9342C_PWCTRL3_LEN 1U
39 #define ILI9342C_VMCTRL1_LEN 1U
[all …]
/Zephyr-latest/include/zephyr/dt-bindings/reset/
Dgd32f403.h30 #define GD32_RESET_AFIO GD32_RESET_CONFIG(APB2RST, 0U)
31 #define GD32_RESET_GPIOA GD32_RESET_CONFIG(APB2RST, 2U)
32 #define GD32_RESET_GPIOB GD32_RESET_CONFIG(APB2RST, 3U)
33 #define GD32_RESET_GPIOC GD32_RESET_CONFIG(APB2RST, 4U)
34 #define GD32_RESET_GPIOD GD32_RESET_CONFIG(APB2RST, 5U)
35 #define GD32_RESET_GPIOE GD32_RESET_CONFIG(APB2RST, 6U)
36 #define GD32_RESET_GPIOF GD32_RESET_CONFIG(APB2RST, 7U)
37 #define GD32_RESET_GPIOG GD32_RESET_CONFIG(APB2RST, 8U)
38 #define GD32_RESET_ADC0 GD32_RESET_CONFIG(APB2RST, 9U)
39 #define GD32_RESET_ADC1 GD32_RESET_CONFIG(APB2RST, 10U)
[all …]
Dgd32e50x.h30 #define GD32_RESET_AFIO GD32_RESET_CONFIG(APB2RST, 0U)
31 #define GD32_RESET_GPIOA GD32_RESET_CONFIG(APB2RST, 2U)
32 #define GD32_RESET_GPIOB GD32_RESET_CONFIG(APB2RST, 3U)
33 #define GD32_RESET_GPIOC GD32_RESET_CONFIG(APB2RST, 4U)
34 #define GD32_RESET_GPIOD GD32_RESET_CONFIG(APB2RST, 5U)
35 #define GD32_RESET_GPIOE GD32_RESET_CONFIG(APB2RST, 6U)
36 #define GD32_RESET_GPIOF GD32_RESET_CONFIG(APB2RST, 7U)
37 #define GD32_RESET_GPIOG GD32_RESET_CONFIG(APB2RST, 8U)
38 #define GD32_RESET_ADC0 GD32_RESET_CONFIG(APB2RST, 9U)
39 #define GD32_RESET_ADC1 GD32_RESET_CONFIG(APB2RST, 10U)
[all …]
Dgd32f4xx.h32 #define GD32_RESET_GPIOA GD32_RESET_CONFIG(AHB1RST, 0U)
33 #define GD32_RESET_GPIOB GD32_RESET_CONFIG(AHB1RST, 1U)
34 #define GD32_RESET_GPIOC GD32_RESET_CONFIG(AHB1RST, 2U)
35 #define GD32_RESET_GPIOD GD32_RESET_CONFIG(AHB1RST, 3U)
36 #define GD32_RESET_GPIOE GD32_RESET_CONFIG(AHB1RST, 4U)
37 #define GD32_RESET_GPIOF GD32_RESET_CONFIG(AHB1RST, 5U)
38 #define GD32_RESET_GPIOG GD32_RESET_CONFIG(AHB1RST, 6U)
39 #define GD32_RESET_GPIOH GD32_RESET_CONFIG(AHB1RST, 7U)
40 #define GD32_RESET_GPIOI GD32_RESET_CONFIG(AHB1RST, 8U)
41 #define GD32_RESET_CRC GD32_RESET_CONFIG(AHB1RST, 12U)
[all …]
/Zephyr-latest/include/zephyr/dt-bindings/spi/
Dspi.h23 #define SPI_FULL_DUPLEX (0U << 11)
24 #define SPI_HALF_DUPLEX (1U << 11)
39 #define SPI_FRAME_FORMAT_MOTOROLA (0U << 15)
40 #define SPI_FRAME_FORMAT_TI (1U << 15)
/Zephyr-latest/include/zephyr/dsp/
Dutils.h46 #define Z_SHIFT_Q7_TO_F32(src, m) ((float32_t)(((src << m)) / (float32_t)(1U << 7)))
52 * @param m The number of bits to left shift the input value (0 to 15).
55 #define Z_SHIFT_Q15_TO_F32(src, m) ((float32_t)((src << m) / (float32_t)(1U << 15)))
64 #define Z_SHIFT_Q31_TO_F32(src, m) ((float32_t)(((int64_t)src) << m) / (float32_t)(1U << 31))
73 #define Z_SHIFT_Q7_TO_F64(src, m) (((float64_t)(src << m)) / (1U << 7))
79 * @param m The number of bits to left shift the input value (0 to 15).
82 #define Z_SHIFT_Q15_TO_F64(src, m) (((float64_t)(src << m)) / (1UL << 15))
115 ((q7_t)Z_CLAMP((int32_t)(src * (1U << 7)) >> m, INT8_MIN, INT8_MAX))
121 * @param m The number of bits to right shift the input value (0 to 15).
125 ((q15_t)Z_CLAMP((int32_t)(src * (1U << 15)) >> m, INT16_MIN, INT16_MAX))
[all …]
/Zephyr-latest/soc/microchip/mec/common/reg/
Dmec_tach.h14 #define MCHP_TACH_INST_SPACING_P2 4u
17 #define MCHP_TACH_CONTROL_REG_OFS 0U
34 #define MCHP_TACH_CTRL_READ_MODE_INPUT 0U
41 #define MCHP_TACH_CTRL_EDGES_2 0U
42 #define MCHP_TACH_CTRL_EDGES_3 SHLU32(1u, 11)
43 #define MCHP_TACH_CTRL_EDGES_5 SHLU32(2u, 11)
44 #define MCHP_TACH_CTRL_EDGES_9 SHLU32(3u, 11)
51 #define MCHP_TACH_CTRL_TOGGLE_INT_EN_POS 15
52 #define MCHP_TACH_CTRL_TOGGLE_INT_EN BIT(15)
64 #define MCHP_TACH_STATUS_REG_OFS 4U
[all …]
Dmec_global_cfg.h16 * b[15:8] = Device Sub-ID
22 #define MCHP_GCFG_DEV_ID_REG32_OFS 28u
27 #define MCHP_GCFG_DID_SUB_ID_MASK GENMASK(15, 8)
32 #define MCHP_GCFG_REV_A1 2u
33 #define MCHP_GCFG_REV_B0 3u
43 #define MCHP_GCFG_SUB_ID_PKG_UNDEF 0u
44 #define MCHP_GCFG_SUB_ID_PKG_64_PIN 1u
45 #define MCHP_GCFG_SUB_ID_PKG_84_PIN 2u
46 #define MCHP_GCFG_SUB_ID_PKG_128_PIN 3u
47 #define MCHP_GCFG_SUB_ID_PKG_144_PIN 4u
[all …]
Dmec_timers.h20 #define MCHP_BTMR_BASE_FREQ 48000000u
26 * 16-bit Basic timers: bits[15:0]=R/W, bits[31:15]=RO=0
33 * 16-bit Basic timers: bits[15:0]=R/W, bits[31:15]=RO=0
48 #define MCHP_BTMR_INTDIS 0u
54 #define MCHP_BTMR_CTRL_PRESCALE_POS 16u
66 #define MCHP_BTMR_CTRL_HALT_POS 7u
67 #define MCHP_BTMR_CTRL_RELOAD_POS 6u
68 #define MCHP_BTMR_CTRL_START_POS 5u
69 #define MCHP_BTMR_CTRL_SRESET_POS 4u
70 #define MCHP_BTMR_CTRL_AUTO_RESTART_POS 3u
[all …]
/Zephyr-latest/samples/boards/nordic/battery/src/
Dmain.c20 * dropped about linearly to 3.58 V over 15 hours. It then
24 * Based on eyeball comparisons we'll say that 15/16 of life
44 s = now % 60U; in now_str()
45 now /= 60U; in now_str()
46 min = now % 60U; in now_str()
47 now /= 60U; in now_str()
50 snprintf(buf, sizeof(buf), "%u:%02u:%02u.%03u", in now_str()
75 printk("[%s]: %d mV; %u pptt\n", now_str(), in main()
/Zephyr-latest/drivers/led/
Dlp3943.c16 * 0 to 7 and 8 to 15 and assigns PSC0/PWM0 to LEDs from 0 to 7 and PSC1/PWM1
17 * to LEDs from 8 to 15. So, it is not possible to set unique blink period
78 *led -= 4U; in lp3943_get_led_reg()
86 *led -= 8U; in lp3943_get_led_reg()
92 case 15: in lp3943_get_led_reg()
94 *led -= 12U; in lp3943_get_led_reg()
141 /* Use DIM0 for LEDs 0 to 7 and DIM1 for LEDs 8 to 15 */ in lp3943_led_blink()
154 val = (period * 255U) / dev_data->max_period; in lp3943_led_blink()
182 /* Use DIM0 for LEDs 0 to 7 and DIM1 for LEDs 8 to 15 */ in lp3943_led_set_brightness()
195 val = (value * 255U) / dev_data->max_brightness; in lp3943_led_set_brightness()
[all …]

12345678910>>...21