Lines Matching +full:15 +full:u

30 #define GD32_CLOCK_DMA0       GD32_CLOCK_CONFIG(AHBEN, 0U)
31 #define GD32_CLOCK_DMA1       GD32_CLOCK_CONFIG(AHBEN, 1U)
32 #define GD32_CLOCK_SRAMSP     GD32_CLOCK_CONFIG(AHBEN, 2U)
33 #define GD32_CLOCK_FMCSP      GD32_CLOCK_CONFIG(AHBEN, 4U)
34 #define GD32_CLOCK_CRC        GD32_CLOCK_CONFIG(AHBEN, 6U)
35 #define GD32_CLOCK_EXMC       GD32_CLOCK_CONFIG(AHBEN, 8U)
36 #define GD32_CLOCK_USBHS      GD32_CLOCK_CONFIG(AHBEN, 12U)
37 #define GD32_CLOCK_ULPI       GD32_CLOCK_CONFIG(AHBEN, 13U)
38 #define GD32_CLOCK_ENET       GD32_CLOCK_CONFIG(AHBEN, 14U)
39 #define GD32_CLOCK_ENETTX     GD32_CLOCK_CONFIG(AHBEN, 15U)
40 #define GD32_CLOCK_ENETRX     GD32_CLOCK_CONFIG(AHBEN, 16U)
41 #define GD32_CLOCK_TMU        GD32_CLOCK_CONFIG(AHBEN, 30U)
42 #define GD32_CLOCK_SQPI       GD32_CLOCK_CONFIG(AHBEN, 31U)
45 #define GD32_CLOCK_TIMER1     GD32_CLOCK_CONFIG(APB1EN, 0U)
46 #define GD32_CLOCK_TIMER2     GD32_CLOCK_CONFIG(APB1EN, 1U)
47 #define GD32_CLOCK_TIMER3     GD32_CLOCK_CONFIG(APB1EN, 2U)
48 #define GD32_CLOCK_TIMER4     GD32_CLOCK_CONFIG(APB1EN, 3U)
49 #define GD32_CLOCK_TIMER5     GD32_CLOCK_CONFIG(APB1EN, 4U)
50 #define GD32_CLOCK_TIMER6     GD32_CLOCK_CONFIG(APB1EN, 5U)
51 #define GD32_CLOCK_TIMER11    GD32_CLOCK_CONFIG(APB1EN, 6U)
52 #define GD32_CLOCK_TIMER12    GD32_CLOCK_CONFIG(APB1EN, 7U)
53 #define GD32_CLOCK_TIMER13    GD32_CLOCK_CONFIG(APB1EN, 8U)
54 #define GD32_CLOCK_WWDGT      GD32_CLOCK_CONFIG(APB1EN, 11U)
55 #define GD32_CLOCK_SPI1       GD32_CLOCK_CONFIG(APB1EN, 14U)
56 #define GD32_CLOCK_SPI2       GD32_CLOCK_CONFIG(APB1EN, 15U)
57 #define GD32_CLOCK_USART1     GD32_CLOCK_CONFIG(APB1EN, 17U)
58 #define GD32_CLOCK_USART2     GD32_CLOCK_CONFIG(APB1EN, 18U)
59 #define GD32_CLOCK_UART3      GD32_CLOCK_CONFIG(APB1EN, 19U)
60 #define GD32_CLOCK_UART4      GD32_CLOCK_CONFIG(APB1EN, 20U)
61 #define GD32_CLOCK_I2C0       GD32_CLOCK_CONFIG(APB1EN, 21U)
62 #define GD32_CLOCK_I2C1       GD32_CLOCK_CONFIG(APB1EN, 22U)
63 #define GD32_CLOCK_I2C2       GD32_CLOCK_CONFIG(APB1EN, 24U)
64 #define GD32_CLOCK_CAN0       GD32_CLOCK_CONFIG(APB1EN, 25U)
65 #define GD32_CLOCK_CAN1       GD32_CLOCK_CONFIG(APB1EN, 26U)
66 #define GD32_CLOCK_BKPI       GD32_CLOCK_CONFIG(APB1EN, 27U)
67 #define GD32_CLOCK_PMU        GD32_CLOCK_CONFIG(APB1EN, 28U)
68 #define GD32_CLOCK_DAC        GD32_CLOCK_CONFIG(APB1EN, 29U)
71 #define GD32_CLOCK_AFIO       GD32_CLOCK_CONFIG(APB2EN, 0U)
72 #define GD32_CLOCK_GPIOA      GD32_CLOCK_CONFIG(APB2EN, 2U)
73 #define GD32_CLOCK_GPIOB      GD32_CLOCK_CONFIG(APB2EN, 3U)
74 #define GD32_CLOCK_GPIOC      GD32_CLOCK_CONFIG(APB2EN, 4U)
75 #define GD32_CLOCK_GPIOD      GD32_CLOCK_CONFIG(APB2EN, 5U)
76 #define GD32_CLOCK_GPIOE      GD32_CLOCK_CONFIG(APB2EN, 6U)
77 #define GD32_CLOCK_GPIOF      GD32_CLOCK_CONFIG(APB2EN, 7U)
78 #define GD32_CLOCK_GPIOG      GD32_CLOCK_CONFIG(APB2EN, 8U)
79 #define GD32_CLOCK_ADC0       GD32_CLOCK_CONFIG(APB2EN, 9U)
80 #define GD32_CLOCK_ADC1       GD32_CLOCK_CONFIG(APB2EN, 10U)
81 #define GD32_CLOCK_TIMER0     GD32_CLOCK_CONFIG(APB2EN, 11U)
82 #define GD32_CLOCK_SPI0       GD32_CLOCK_CONFIG(APB2EN, 12U)
83 #define GD32_CLOCK_TIMER7     GD32_CLOCK_CONFIG(APB2EN, 13U)
84 #define GD32_CLOCK_USART0     GD32_CLOCK_CONFIG(APB2EN, 14U)
85 #define GD32_CLOCK_ADC2       GD32_CLOCK_CONFIG(APB2EN, 15U)
86 #define GD32_CLOCK_TIMER8     GD32_CLOCK_CONFIG(APB2EN, 19U)
87 #define GD32_CLOCK_TIMER9     GD32_CLOCK_CONFIG(APB2EN, 20U)
88 #define GD32_CLOCK_TIMER10    GD32_CLOCK_CONFIG(APB2EN, 21U)
89 #define GD32_CLOCK_USART5     GD32_CLOCK_CONFIG(APB2EN, 28U)
90 #define GD32_CLOCK_SHRTIMER   GD32_CLOCK_CONFIG(APB2EN, 29U)
91 #define GD32_CLOCK_CMP        GD32_CLOCK_CONFIG(APB2EN, 31U)
94 #define GD32_CLOCK_CTC        GD32_CLOCK_CONFIG(ADDAPB1EN, 27U)
95 #define GD32_CLOCK_CAN2       GD32_CLOCK_CONFIG(ADDAPB1EN, 31U)