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/Zephyr-Core-3.6.0/include/zephyr/drivers/dma/
Ddma_gd32.h10 #define GD32_DMA_CONFIG_DIRECTION(config) ((config >> 6) & 0x3)
11 #define GD32_DMA_CONFIG_PERIPH_ADDR_INC(config) ((config >> 9) & 0x1)
12 #define GD32_DMA_CONFIG_MEMORY_ADDR_INC(config) ((config >> 10) & 0x1)
13 #define GD32_DMA_CONFIG_PERIPH_WIDTH(config) ((config >> 11) & 0x3)
14 #define GD32_DMA_CONFIG_MEMORY_WIDTH(config) ((config >> 13) & 0x3)
15 #define GD32_DMA_CONFIG_PERIPHERAL_INC_FIXED(config) ((config >> 15) & 0x1)
16 #define GD32_DMA_CONFIG_PRIORITY(config) ((config >> 16) & 0x3)
18 #define GD32_DMA_FEATURES_FIFO_THRESHOLD(threshold) (threshold & 0x3)
Ddma_stm32.h13 #define STM32_DMA_HAL_OVERRIDE 0x7F
15 /* @brief gives the first DMA channel : 0 or 1 in the register map
16 * when counting channels from 1 to N or from 0 to N-1
19 /* from DTS the dma stream id is in range 0..N-1 */
20 #define STM32_DMA_STREAM_OFFSET 0
23 /* so decrease to set range from 0 from now on */
29 /* from DTS the dma stream id is in range 0..N-1 */
30 #define STM32_DMA_STREAM_OFFSET 0
35 #define STM32_DMA_SLOT(id, dir, slot) 0
45 #define STM32_DMA_FEATURES(id, dir) 0
[all …]
/Zephyr-Core-3.6.0/dts/arm/st/f4/
Dstm32f411.dtsi16 #size-cells = <0>;
17 reg = <0x40015000 0x400>;
18 clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00100000>;
26 #size-cells = <0>;
27 reg = <0x40013000 0x400>;
28 clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00001000>;
30 dmas = <&dma2 3 3 0x400 0x3
31 &dma2 2 3 0x400 0x3>;
39 #size-cells = <0>;
40 reg = <0x40013400 0x400>;
[all …]
Dstm32f410.dtsi21 #size-cells = <0>;
22 reg = <0x40003800 0x400>;
23 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00004000>;
31 #size-cells = <0>;
32 reg = <0x40015000 0x400>;
33 clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00100000>;
41 #size-cells = <0>;
42 reg = <0x40013000 0x400>;
43 clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00001000>;
45 dmas = <&dma2 3 3 0x400 0x3
[all …]
Dstm32f401.dtsi12 #clock-cells = <0>;
24 #size-cells = <0>;
25 reg = <0x40003800 0x400>;
26 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00004000>;
34 #size-cells = <0>;
35 reg = <0x40003c00 0x400>;
36 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00008000>;
44 #size-cells = <0>;
45 reg = <0x40013400 0x400>;
46 clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00002000>;
[all …]
/Zephyr-Core-3.6.0/drivers/watchdog/
Dwdt_nxp_fs26.h13 #define FS26_M_FS (0x1 << 31)
16 #define FS26_REG_ADDR_MASK (0x7f << FS26_REG_ADDR_SHIFT)
19 /* Read/Write (reading = 0) */
20 #define FS26_RW (0x1 << 24)
26 #define FS26_DEV_STATUS_MASK (0xff << FS26_DEV_STATUS_SHIFT)
29 #define FS26_M_AVAL (0x1 << 31)
31 #define FS26_FS_EN (0x1 << 30)
33 #define FS26_FS_G (0x1 << 29)
35 #define FS26_COM_G (0x1 << 28)
37 #define FS26_WIO_G (0x1 << 27)
[all …]
/Zephyr-Core-3.6.0/arch/arm64/core/
Duserspace.S28 mov x3, x0
29 mov x0, #0
30 mov x4, #0
38 ldrb w5, [x3, x0]
47 mov x0, #0
61 mrs x3, DAIF
75 tbnz x4, #0, abv_fail
80 msr DAIF, x3
81 mov x0, #0
85 msr DAIF, x3
[all …]
/Zephyr-Core-3.6.0/include/zephyr/dt-bindings/pinctrl/
Dstm32-pinctrl.h18 #define STM32_AF0 0x0
19 #define STM32_AF1 0x1
20 #define STM32_AF2 0x2
21 #define STM32_AF3 0x3
22 #define STM32_AF4 0x4
23 #define STM32_AF5 0x5
24 #define STM32_AF6 0x6
25 #define STM32_AF7 0x7
26 #define STM32_AF8 0x8
27 #define STM32_AF9 0x9
[all …]
Dstm32f1-pinctrl.h20 #define STM32_MODE_SHIFT 0U
21 #define STM32_MODE_MASK 0x3U
23 #define STM32_LINE_MASK 0xFU
25 #define STM32_PORT_MASK 0xFU
27 #define STM32_REMAP_MASK 0x3FFU
34 * - mode [ 0 : 1 ]
40 * @param line Pin (0..15)
54 #define ALTERNATE 0x0 /* Alternate function output */
55 #define GPIO_IN 0x1 /* Input */
56 #define ANALOG 0x2 /* Analog */
[all …]
/Zephyr-Core-3.6.0/soc/arm/nxp_lpc/lpc11u6x/
Dsoc.h29 * [0:2] function.
40 #define IOCON_PIO_FUNC(x) (((x) & 0x7))
41 #define IOCON_PIO_FUNC_MASK IOCON_PIO_FUNC(0x7)
42 #define IOCON_PIO_MODE(x) (((x) & 0x3) << 3)
43 #define IOCON_PIO_MODE_MASK IOCON_PIO_MODE(0x3)
44 #define IOCON_PIO_HYS(x) (((x) & 0x1) << 5)
45 #define IOCON_PIO_HYS_MASK IOCON_PIO_HYS(0x1)
46 #define IOCON_PIO_INVERT(x) (((x) & 0x1) << 2)
47 #define IOCON_PIO_INVERT_MASK IOCON_PIO_INVERT(0x1)
48 #define IOCON_PIO_OD(x) (((x) & 0x1) << 10)
[all …]
/Zephyr-Core-3.6.0/samples/subsys/usb/dfu/
DREADME.rst33 to be loaded at the offset of SLOT-0.
47 the USB DFU sample at the offset of SLOT-0.
65 Use the following command to backup the SLOT-0 image:
69 dfu-util --alt 0 --upload slot0_backup.bin
84 I: Primary image: magic=good, swap_type=0x3, copy_done=0x1, image_ok=0x1
85 I: Secondary image: magic=good, swap_type=0x2, copy_done=0x3, image_ok=0x3
88 I: Bootloader chainload address offset: 0xc000
101 I: Primary image: magic=good, swap_type=0x2, copy_done=0x1, image_ok=0x3
102 I: Secondary image: magic=unset, swap_type=0x1, copy_done=0x3, image_ok=0x3
105 I: Secondary image: magic=unset, swap_type=0x1, copy_done=0x3, image_ok=0x3
[all …]
/Zephyr-Core-3.6.0/include/zephyr/dt-bindings/dma/
Dgd32_dma.h13 #define GD32_DMA_CH_CFG_DIRECTION(val) ((val & 0x3) << 6)
14 #define GD32_DMA_MEMORY_TO_MEMORY GD32_DMA_CH_CFG_DIRECTION(0)
19 #define GD32_DMA_CH_CFG_PERIPH_ADDR_INC(val) ((val & 0x1) << 9)
20 #define GD32_DMA_NO_PERIPH_ADDR_INC GD32_DMA_CH_CFG_PERIPH_ADDR_INC(0)
24 #define GD32_DMA_CH_CFG_MEMORY_ADDR_INC(val) ((val & 0x1) << 10)
25 #define GD32_DMA_NO_MEMORY_ADDR_INC GD32_DMA_CH_CFG_MEMORY_ADDR_INC(0)
29 #define GD32_DMA_CH_CFG_PERIPH_WIDTH(val) ((val & 0x3) << 11)
30 #define GD32_DMA_PERIPH_WIDTH_8BIT GD32_DMA_CH_CFG_PERIPH_WIDTH(0)
35 #define GD32_DMA_CH_CFG_MEMORY_WIDTH(val) ((val & 0x3) << 13)
36 #define GD32_DMA_MEMORY_WIDTH_8BIT GD32_DMA_CH_CFG_PERIPH_WIDTH(0)
[all …]
Dstm32_dma.h14 #define STM32_DMA_CH_CFG_MODE(val) ((val & 0x1) << 5)
15 #define STM32_DMA_MODE_NORMAL STM32_DMA_CH_CFG_MODE(0)
19 #define STM32_DMA_CH_CFG_DIRECTION(val) ((val & 0x3) << 6)
20 #define STM32_DMA_MEMORY_TO_MEMORY STM32_DMA_CH_CFG_DIRECTION(0)
26 #define STM32_DMA_CH_CFG_PERIPH_ADDR_INC(val) ((val & 0x1) << 9)
27 #define STM32_DMA_PERIPH_NO_INC STM32_DMA_CH_CFG_PERIPH_ADDR_INC(0)
31 #define STM32_DMA_CH_CFG_MEM_ADDR_INC(val) ((val & 0x1) << 10)
32 #define STM32_DMA_MEM_NO_INC STM32_DMA_CH_CFG_MEM_ADDR_INC(0)
36 #define STM32_DMA_CH_CFG_PERIPH_WIDTH(val) ((val & 0x3) << 11)
37 #define STM32_DMA_PERIPH_8BITS STM32_DMA_CH_CFG_PERIPH_WIDTH(0)
[all …]
/Zephyr-Core-3.6.0/dts/arm/nuvoton/npcx/
Dnpcx-alts-map.dtsi12 /* SCFG DEVALT 0 */
14 alts = <&scfg 0x00 0x0 0>;
17 alts = <&scfg 0x00 0x3 1>;
21 alts = <&scfg 0x00 0x7 1>;
26 alts = <&scfg 0x01 0x0 0>;
29 alts = <&scfg 0x01 0x2 0>;
32 alts = <&scfg 0x01 0x3 0>;
35 alts = <&scfg 0x01 0x4 1>;
38 alts = <&scfg 0x01 0x5 0>;
41 alts = <&scfg 0x01 0x6 0>;
[all …]
/Zephyr-Core-3.6.0/dts/bindings/dma/
Dst,stm32u5-dma.yaml12 Tx using channel 0 with request 7
15 dmas = <&gpdma1 0 7 0x10440>,
16 <&gpdma1 1 6 0x10480>;
20 1. channel: the stream or channel from 0 to (<dma-channels> - 1).
22 the slot is a value between <0> .. (<dma-requests> - 1).
26 0x0: MEM to MEM
27 0x1: MEM to PERIPH
28 0x2: PERIPH to MEM
29 0x3: reserved for PERIPH to PERIPH
31 0x0: no address increment between transfers
[all …]
Dgd,gd32-dma.yaml11 - 0x0: MEMORY to MEMORY
12 - 0x1: MEMORY to PERIPH
13 - 0x2: PERIPH to MEMORY
14 - 0x3: reserved for PERIPH to PERIPH
17 - 0x0: no address increment between transfers
18 - 0x1: increment address between transfers
21 - 0x0: no address increase between transfers
22 - 0x1: increase address between transfers
25 - 0x0: 8 bits
26 - 0x1: 16 bits
[all …]
Dst,stm32-dma-v1.yaml12 1. channel: the dma stream from 0 to <dma-requests>
14 this value is 0 for Memory-to-memory transfers
20 0x0: MEM to MEM
21 0x1: MEM to PERIPH
22 0x2: PERIPH to MEM
23 0x3: reserved for PERIPH to PERIPH
25 0x0: no address increment between transfers
26 0x1: increment address between transfers
28 0x0: no address increment between transfers
29 0x1: increment address between transfers
[all …]
Dgd,gd32-dma-v1.yaml13 - 0x0: MEMORY to MEMORY
14 - 0x1: MEMORY to PERIPH
15 - 0x2: PERIPH to MEMORY
16 - 0x3: reserved for PERIPH to PERIPH
19 - 0x0: no address increment between transfers
20 - 0x1: increment address between transfers
23 - 0x0: no address increase between transfers
24 - 0x1: increase address between transfers
27 - 0x0: 8 bits
28 - 0x1: 16 bits
[all …]
Dst,stm32-dmamux.yaml11 1. channel: the mux channel from 0 to <dma-channels> - 1
16 0x0: MEM to MEM
17 0x1: MEM to PERIPH
18 0x2: PERIPH to MEM
19 0x3: reserved for PERIPH to PERIPH
21 0x0: no address increment between transfers
22 0x1: increment address between transfers
24 0x0: no address increment between transfers
25 0x1: increment address between transfers
27 0x0: Byte (8 bits)
[all …]
Dst,stm32-bdma.yaml13 1. channel: the bdma stream from 0 to <bdma-requests>
18 0x0: MEM to MEM
19 0x1: MEM to PERIPH
20 0x2: PERIPH to MEM
21 0x3: reserved for PERIPH to PERIPH
23 0x0: no address increment between transfers
24 0x1: increment address between transfers
26 0x0: no address increment between transfers
27 0x1: increment address between transfers
29 0x0: Byte (8 bits)
[all …]
Dst,stm32-dma-v2bis.yaml18 0x0: STM32_DMA_MODE_NORMAL
19 0x1: STM32_DMA_MODE_CYCLIC
21 0x0: STM32_DMA_MEMORY_TO_MEMORY: MEM to MEM
22 0x1: STM32_DMA_MEMORY_TO_PERIPH: MEM to PERIPH
23 0x2: STM32_DMA_PERIPH_TO_MEMORY: PERIPH to MEM
24 0x3: reserved for PERIPH to PERIPH
26 0x0: STM32_DMA_PERIPH_NO_INC: no address increment between transfers
27 0x1: STM32_DMA_PERIPH_INC: increment address between transfers
29 0x0: STM32_DMA_MEM_NO_INC: no address increment between transfers
30 0x1: STM32_DMA_MEM_INC: increment address between transfers
[all …]
Dandestech,atcdmac300.yaml35 -bit 0-1 : Direction (see dma.h)
36 0x0: MEM to MEM
37 0x1: MEM to PERIPH
38 0x2: PERIPH to MEM
39 0x3: reserved for PERIPH to PERIPH
41 0x0: no address increment between transfers
42 0x1: increment address between transfers
44 0x0: no address increment between transfers
45 0x1: increment address between transfers
47 0x0: Byte (8 bits)
[all …]
/Zephyr-Core-3.6.0/drivers/sensor/fdc2x1x/
Dfdc2x1x.h19 #define FDC2X1X_DATA_CH0 0x00
20 #define FDC2X1X_DATA_LSB_CH0 0x01
21 #define FDC2X1X_DATA_CH1 0x02
22 #define FDC2X1X_DATA_LSB_CH1 0x03
23 #define FDC2X1X_DATA_CH2 0x04
24 #define FDC2X1X_DATA_LSB_CH2 0x05
25 #define FDC2X1X_DATA_CH3 0x06
26 #define FDC2X1X_DATA_LSB_CH3 0x07
27 #define FDC2X1X_RCOUNT_CH0 0x08
28 #define FDC2X1X_RCOUNT_CH1 0x09
[all …]
/Zephyr-Core-3.6.0/drivers/charger/
Dbq24190.h11 #define BQ24190_REG_ISC 0x00
16 #define BQ24190_REG_ISC_IINLIM_MASK GENMASK(2, 0)
19 #define BQ24190_REG_POC 0x01
27 #define BQ24190_REG_POC_CHG_CONFIG_DISABLE 0x0
28 #define BQ24190_REG_POC_CHG_CONFIG_CHARGE 0x1
29 #define BQ24190_REG_POC_CHG_CONFIG_OTG 0x2
30 #define BQ24190_REG_POC_CHG_CONFIG_OTG_ALT 0x3
35 #define BQ24190_REG_POC_BOOST_LIM_MASK BIT(0)
36 #define BQ24190_REG_POC_BOOST_LIM_SHIFT 0
39 #define BQ24190_REG_CCC 0x02
[all …]
/Zephyr-Core-3.6.0/include/zephyr/dt-bindings/sensor/
Dlsm6dso16is.h10 #define LSM6DSO16IS_DT_FS_2G 0
16 #define LSM6DSO16IS_DT_FS_250DPS 0x0
17 #define LSM6DSO16IS_DT_FS_500DPS 0x1
18 #define LSM6DSO16IS_DT_FS_1000DPS 0x2
19 #define LSM6DSO16IS_DT_FS_2000DPS 0x3
20 #define LSM6DSO16IS_DT_FS_125DPS 0x10
23 #define LSM6DSO16IS_DT_ODR_OFF 0x0
24 #define LSM6DSO16IS_DT_ODR_12Hz5_HP 0x1
25 #define LSM6DSO16IS_DT_ODR_26H_HP 0x2
26 #define LSM6DSO16IS_DT_ODR_52Hz_HP 0x3
[all …]

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