Lines Matching +full:0 +full:x3

20 #define STM32_MODE_SHIFT  0U
21 #define STM32_MODE_MASK   0x3U
23 #define STM32_LINE_MASK   0xFU
25 #define STM32_PORT_MASK   0xFU
27 #define STM32_REMAP_MASK  0x3FFU
34  * - mode  [ 0 : 1 ]
40  * @param line Pin (0..15)
54 #define ALTERNATE	0x0  /* Alternate function output */
55 #define GPIO_IN		0x1  /* Input */
56 #define ANALOG		0x2  /* Analog */
57 #define GPIO_OUT	0x3  /* Output */
64  *    GPIO I/O Mode       [ 0 ]
76 #define STM32_MODE_INPUT		(0x0 << STM32_MODE_INOUT_SHIFT)
77 #define STM32_MODE_OUTPUT		(0x1 << STM32_MODE_INOUT_SHIFT)
78 #define STM32_MODE_INOUT_MASK		0x1
79 #define STM32_MODE_INOUT_SHIFT		0
82 #define STM32_CNF_IN_ANALOG		(0x0 << STM32_CNF_IN_SHIFT)
83 #define STM32_CNF_IN_FLOAT		(0x1 << STM32_CNF_IN_SHIFT)
84 #define STM32_CNF_IN_PUPD		(0x2 << STM32_CNF_IN_SHIFT)
85 #define STM32_CNF_IN_MASK		0x3
89 #define STM32_MODE_OUTPUT_MAX_10	(0x0 << STM32_MODE_OSPEED_SHIFT)
90 #define STM32_MODE_OUTPUT_MAX_2		(0x1 << STM32_MODE_OSPEED_SHIFT)
91 #define STM32_MODE_OUTPUT_MAX_50	(0x2 << STM32_MODE_OSPEED_SHIFT)
92 #define STM32_MODE_OSPEED_MASK		0x3
95 #define STM32_CNF_PUSH_PULL		(0x0 << STM32_CNF_OUT_0_SHIFT)
96 #define STM32_CNF_OPEN_DRAIN		(0x1 << STM32_CNF_OUT_0_SHIFT)
97 #define STM32_CNF_OUT_0_MASK		0x1
100 #define STM32_CNF_GP_OUTPUT		(0x0 << STM32_CNF_OUT_1_SHIFT)
101 #define STM32_CNF_ALT_FUNC		(0x1 << STM32_CNF_OUT_1_SHIFT)
102 #define STM32_CNF_OUT_1_MASK		0x1
106 #define STM32_PUPD_NO_PULL		(0x0 << STM32_PUPD_SHIFT)
107 #define STM32_PUPD_PULL_UP		(0x1 << STM32_PUPD_SHIFT)
108 #define STM32_PUPD_PULL_DOWN		(0x2 << STM32_PUPD_SHIFT)
109 #define STM32_PUPD_MASK			0x3
113 #define STM32_ODR_0			(0x0 << STM32_ODR_SHIFT)
114 #define STM32_ODR_1			(0x1 << STM32_ODR_SHIFT)
115 #define STM32_ODR_MASK			0x1