1/*
2 * Copyright (c) 2017 Linaro Limited
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include <st/f4/stm32f4.dtsi>
8
9/ {
10	clocks {
11		plli2s: plli2s {
12			#clock-cells = <0>;
13			compatible = "st,stm32f4-plli2s-clock";
14			status = "disabled";
15		};
16	};
17
18	soc {
19		compatible = "st,stm32f401", "st,stm32f4", "simple-bus";
20
21		spi2: spi@40003800 {
22			compatible = "st,stm32-spi";
23			#address-cells = <1>;
24			#size-cells = <0>;
25			reg = <0x40003800 0x400>;
26			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00004000>;
27			interrupts = <36 5>;
28			status = "disabled";
29		};
30
31		spi3: spi@40003c00 {
32			compatible = "st,stm32-spi";
33			#address-cells = <1>;
34			#size-cells = <0>;
35			reg = <0x40003c00 0x400>;
36			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00008000>;
37			interrupts = <51 5>;
38			status = "disabled";
39		};
40
41		spi4: spi@40013400 {
42			compatible = "st,stm32-spi";
43			#address-cells = <1>;
44			#size-cells = <0>;
45			reg = <0x40013400 0x400>;
46			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00002000>;
47			interrupts = <84 5>;
48			status = "disabled";
49		};
50
51		i2s2: i2s@40003800 {
52			compatible = "st,stm32-i2s";
53			#address-cells = <1>;
54			#size-cells = <0>;
55			reg = <0x40003800 0x400>;
56			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00004000>;
57			interrupts = <36 5>;
58			dmas = <&dma1 4 0 0x400 0x3
59				&dma1 3 0 0x400 0x3>;
60			dma-names = "tx", "rx";
61			status = "disabled";
62		};
63
64		i2s3: i2s@40003c00 {
65			compatible = "st,stm32-i2s";
66			#address-cells = <1>;
67			#size-cells = <0>;
68			reg = <0x40003c00 0x400>;
69			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00008000>;
70			interrupts = <51 5>;
71			dmas = <&dma1 5 0 0x400 0x3
72				&dma1 0 0 0x400 0x3>;
73			dma-names = "tx", "rx";
74			status = "disabled";
75		};
76
77	};
78};
79