Lines Matching +full:0 +full:x3
13 #define FS26_M_FS (0x1 << 31)
16 #define FS26_REG_ADDR_MASK (0x7f << FS26_REG_ADDR_SHIFT)
19 /* Read/Write (reading = 0) */
20 #define FS26_RW (0x1 << 24)
26 #define FS26_DEV_STATUS_MASK (0xff << FS26_DEV_STATUS_SHIFT)
29 #define FS26_M_AVAL (0x1 << 31)
31 #define FS26_FS_EN (0x1 << 30)
33 #define FS26_FS_G (0x1 << 29)
35 #define FS26_COM_G (0x1 << 28)
37 #define FS26_WIO_G (0x1 << 27)
39 #define FS26_VSUP_G (0x1 << 26)
41 #define FS26_REG_G (0x1 << 25)
43 #define FS26_TSD_G (0x1 << 24)
49 #define FS26_DATA_MASK (0xffff << FS26_DATA_SHIFT)
54 #define FS26_DATA_LSB_MASK (0xff << FS26_DATA_LSB_SHIFT)
59 #define FS26_DATA_MSB_MASK (0xff << FS26_DATA_MSB_SHIFT)
63 #define FS26_CRC_SHIFT (0)
64 #define FS26_CRC_MASK (0xff << FS26_CRC_SHIFT)
70 #define FS26_M_DEVICE_ID (0x0)
71 #define FS26_M_PROGID (0x1)
72 #define FS26_M_STATUS (0x2)
73 #define FS26_M_TSD_FLG (0x3)
74 #define FS26_M_TSD_MSK (0x4)
75 #define FS26_M_REG_FLG (0x5)
76 #define FS26_M_REG_MSK (0x6)
77 #define FS26_M_VSUP_FLG (0x7)
78 #define FS26_M_VSUP_MSK (0x8)
79 #define FS26_M_WIO_FLG (0x9)
80 #define FS26_M_WIO_MSK (0xa)
81 #define FS26_M_COM_FLG (0xb)
82 #define FS26_M_COM_MSK (0xc)
83 #define FS26_M_SYS_CFG (0xd)
84 #define FS26_M_TSD_CFG (0xe)
85 #define FS26_M_REG_CFG (0xf)
86 #define FS26_M_WIO_CFG (0x10)
87 #define FS26_M_REG_CTRL1 (0x11)
88 #define FS26_M_REG_CTRL2 (0x12)
89 #define FS26_M_AMUX_CTRL (0x13)
90 #define FS26_M_LDT_CFG1 (0x14)
91 #define FS26_M_LDT_CFG2 (0x15)
92 #define FS26_M_LDT_CFG3 (0x16)
93 #define FS26_M_LDT_CTRL (0x17)
94 #define FS26_M_MEMORY0 (0x18)
95 #define FS26_M_MEMORY1 (0x19)
99 #define FS26_FS_GRL_FLAGS (0x40)
100 #define FS26_FS_I_OVUV_SAFE_REACTION1 (0x41)
101 #define FS26_FS_I_NOT_OVUV_SAFE_REACTION1 (0x42)
102 #define FS26_FS_I_OVUV_SAFE_REACTION2 (0x43)
103 #define FS26_FS_I_NOT_OVUV_SAFE_REACTION2 (0x44)
104 #define FS26_FS_I_WD_CFG (0x45)
105 #define FS26_FS_I_NOT_WD_CFG (0x46)
106 #define FS26_FS_I_SAFE_INPUTS (0x47)
107 #define FS26_FS_I_NOT_SAFE_INPUTS (0x48)
108 #define FS26_FS_I_FSSM (0x49)
109 #define FS26_FS_I_NOT_FSSM (0x4a)
110 #define FS26_FS_WDW_DURATION (0x4b)
111 #define FS26_FS_NOT_WDW_DURATION (0x4c)
112 #define FS26_FS_WD_ANSWER (0x4d)
113 #define FS26_FS_WD_TOKEN (0x4e)
114 #define FS26_FS_ABIST_ON_DEMAND (0x4f)
115 #define FS26_FS_OVUV_REG_STATUS (0x50)
116 #define FS26_FS_RELEASE_FS0B_FS1B (0x51)
117 #define FS26_FS_SAFE_IOS_1 (0x52)
118 #define FS26_FS_SAFE_IOS_2 (0x53)
119 #define FS26_FS_DIAG_SAFETY1 (0x54)
120 #define FS26_FS_DIAG_SAFETY2 (0x55)
121 #define FS26_FS_INTB_MASK (0x56)
122 #define FS26_FS_STATES (0x57)
123 #define FS26_FS_LP_REQ (0x58)
124 #define FS26_FS_LDT_LPSEL (0x59)
130 #define VMON_PRE_OV_FS_REACTION_MASK (0x3 << VMON_PRE_OV_FS_REACTION_SHIFT)
131 #define VMON_PRE_OV_FS_REACTION_NO_EFFECT (0x0 << VMON_PRE_OV_FS_REACTION_SHIFT)
132 #define VMON_PRE_OV_FS_REACTION_FS0B (0x1 << VMON_PRE_OV_FS_REACTION_SHIFT)
133 #define VMON_PRE_OV_FS_REACTION_RSTB_FS0B (0x2 << VMON_PRE_OV_FS_REACTION_SHIFT)
137 #define VMON_PRE_UV_FS_REACTION_MASK (0x3 << VMON_PRE_UV_FS_REACTION_SHIFT)
138 #define VMON_PRE_UV_FS_REACTION_NO_EFFECT (0x0 << VMON_PRE_UV_FS_REACTION_SHIFT)
139 #define VMON_PRE_UV_FS_REACTION_FS0B (0x1 << VMON_PRE_UV_FS_REACTION_SHIFT)
140 #define VMON_PRE_UV_FS_REACTION_RSTB_FS0B (0x2 << VMON_PRE_UV_FS_REACTION_SHIFT)
144 #define VMON_CORE_OV_FS_REACTION_MASK (0x3 << VMON_CORE_OV_FS_REACTION_SHIFT)
145 #define VMON_CORE_OV_FS_REACTION_NO_EFFECT (0x0 << VMON_CORE_OV_FS_REACTION_SHIFT)
146 #define VMON_CORE_OV_FS_REACTION_FS0B (0x1 << VMON_CORE_OV_FS_REACTION_SHIFT)
147 #define VMON_CORE_OV_FS_REACTION_RSTB_FS0B (0x2 << VMON_CORE_OV_FS_REACTION_SHIFT)
151 #define VMON_CORE_UV_FS_REACTION_MASK (0x3 << VMON_CORE_UV_FS_REACTION_SHIFT)
152 #define VMON_CORE_UV_FS_REACTION_NO_EFFECT (0x0 << VMON_CORE_UV_FS_REACTION_SHIFT)
153 #define VMON_CORE_UV_FS_REACTION_FS0B (0x1 << VMON_CORE_UV_FS_REACTION_SHIFT)
154 #define VMON_CORE_UV_FS_REACTION_RSTB_FS0B (0x2 << VMON_CORE_UV_FS_REACTION_SHIFT)
158 #define VMON_LDO1_OV_FS_REACTION_MASK (0x3 << VMON_LDO1_OV_FS_REACTION_SHIFT)
159 #define VMON_LDO1_OV_FS_REACTION_NO_EFFECT (0x0 << VMON_LDO1_OV_FS_REACTION_SHIFT)
160 #define VMON_LDO1_OV_FS_REACTION_FS0B (0x1 << VMON_LDO1_OV_FS_REACTION_SHIFT)
161 #define VMON_LDO1_OV_FS_REACTION_RSTB_FS0B (0x2 << VMON_LDO1_OV_FS_REACTION_SHIFT)
165 #define VMON_LDO1_UV_FS_REACTION_MASK (0x3 << VMON_LDO1_UV_FS_REACTION_SHIFT)
166 #define VMON_LDO1_UV_FS_REACTION_NO_EFFECT (0x0 << VMON_LDO1_UV_FS_REACTION_SHIFT)
167 #define VMON_LDO1_UV_FS_REACTION_FS0B (0x1 << VMON_LDO1_UV_FS_REACTION_SHIFT)
168 #define VMON_LDO1_UV_FS_REACTION_RSTB_FS0B (0x2 << VMON_LDO1_UV_FS_REACTION_SHIFT)
172 #define VMON_LDO2_OV_FS_REACTION_MASK (0x3 << VMON_LDO2_OV_FS_REACTION_SHIFT)
173 #define VMON_LDO2_OV_FS_REACTION_NO_EFFECT (0x0 << VMON_LDO2_OV_FS_REACTION_SHIFT)
174 #define VMON_LDO2_OV_FS_REACTION_FS0B (0x1 << VMON_LDO2_OV_FS_REACTION_SHIFT)
175 #define VMON_LDO2_OV_FS_REACTION_RSTB_FS0B (0x2 << VMON_LDO2_OV_FS_REACTION_SHIFT)
178 #define VMON_LDO2_UV_FS_REACTION_SHIFT (0)
179 #define VMON_LDO2_UV_FS_REACTION_MASK (0x3 << VMON_LDO2_UV_FS_REACTION_SHIFT)
180 #define VMON_LDO2_UV_FS_REACTION_NO_EFFECT (0x0 << VMON_LDO2_UV_FS_REACTION_SHIFT)
181 #define VMON_LDO2_UV_FS_REACTION_FS0B (0x1 << VMON_LDO2_UV_FS_REACTION_SHIFT)
182 #define VMON_LDO2_UV_FS_REACTION_RSTB_FS0B (0x2 << VMON_LDO2_UV_FS_REACTION_SHIFT)
188 #define VMON_EXT_OV_FS_REACTION_MASK (0x3 << VMON_EXT_OV_FS_REACTION_SHIFT)
189 #define VMON_EXT_OV_FS_REACTION_NO_EFFECT (0x0 << VMON_EXT_OV_FS_REACTION_SHIFT)
190 #define VMON_EXT_OV_FS_REACTION_FS0B (0x1 << VMON_EXT_OV_FS_REACTION_SHIFT)
191 #define VMON_EXT_OV_FS_REACTION_RSTB_FS0B (0x2 << VMON_EXT_OV_FS_REACTION_SHIFT)
195 #define VMON_EXT_UV_FS_REACTION_MASK (0x3 << VMON_EXT_UV_FS_REACTION_SHIFT)
196 #define VMON_EXT_UV_FS_REACTION_NO_EFFECT (0x0 << VMON_EXT_UV_FS_REACTION_SHIFT)
197 #define VMON_EXT_UV_FS_REACTION_FS0B (0x1 << VMON_EXT_UV_FS_REACTION_SHIFT)
198 #define VMON_EXT_UV_FS_REACTION_RSTB_FS0B (0x2 << VMON_EXT_UV_FS_REACTION_SHIFT)
202 #define VMON_REF_OV_FS_REACTION_MASK (0x3 << VMON_REF_OV_FS_REACTION_SHIFT)
203 #define VMON_REF_OV_FS_REACTION_NO_EFFECT (0x0 << VMON_REF_OV_FS_REACTION_SHIFT)
204 #define VMON_REF_OV_FS_REACTION_FS0B (0x1 << VMON_REF_OV_FS_REACTION_SHIFT)
205 #define VMON_REF_OV_FS_REACTION_RSTB_FS0B (0x2 << VMON_REF_OV_FS_REACTION_SHIFT)
209 #define VMON_REF_UV_FS_REACTION_MASK (0x3 << VMON_REF_UV_FS_REACTION_SHIFT)
210 #define VMON_REF_UV_FS_REACTION_NO_EFFECT (0x0 << VMON_REF_UV_FS_REACTION_SHIFT)
211 #define VMON_REF_UV_FS_REACTION_FS0B (0x1 << VMON_REF_UV_FS_REACTION_SHIFT)
212 #define VMON_REF_UV_FS_REACTION_RSTB_FS0B (0x2 << VMON_REF_UV_FS_REACTION_SHIFT)
216 #define VMON_TRK2_OV_FS_REACTION_MASK (0x3 << VMON_TRK2_OV_FS_REACTION_SHIFT)
217 #define VMON_TRK2_OV_FS_REACTION_NO_EFFECT (0x0 << VMON_TRK2_OV_FS_REACTION_SHIFT)
218 #define VMON_TRK2_OV_FS_REACTION_FS0B (0x1 << VMON_TRK2_OV_FS_REACTION_SHIFT)
219 #define VMON_TRK2_OV_FS_REACTION_RSTB_FS0B (0x2 << VMON_TRK2_OV_FS_REACTION_SHIFT)
223 #define VMON_TRK2_UV_FS_REACTION_MASK (0x3 << VMON_TRK2_UV_FS_REACTION_SHIFT)
224 #define VMON_TRK2_UV_FS_REACTION_NO_EFFECT (0x0 << VMON_TRK2_UV_FS_REACTION_SHIFT)
225 #define VMON_TRK2_UV_FS_REACTION_FS0B (0x1 << VMON_TRK2_UV_FS_REACTION_SHIFT)
226 #define VMON_TRK2_UV_FS_REACTION_RSTB_FS0B (0x2 << VMON_TRK2_UV_FS_REACTION_SHIFT)
230 #define VMON_TRK1_OV_FS_REACTION_MASK (0x3 << VMON_TRK1_OV_FS_REACTION_SHIFT)
231 #define VMON_TRK1_OV_FS_REACTION_NO_EFFECT (0x0 << VMON_TRK1_OV_FS_REACTION_SHIFT)
232 #define VMON_TRK1_OV_FS_REACTION_FS0B (0x1 << VMON_TRK1_OV_FS_REACTION_SHIFT)
233 #define VMON_TRK1_OV_FS_REACTION_RSTB_FS0B (0x2 << VMON_TRK1_OV_FS_REACTION_SHIFT)
236 #define VMON_TRK1_UV_FS_REACTION_SHIFT (0)
237 #define VMON_TRK1_UV_FS_REACTION_MASK (0x3 << VMON_TRK1_UV_FS_REACTION_SHIFT)
238 #define VMON_TRK1_UV_FS_REACTION_NO_EFFECT (0x0 << VMON_TRK1_UV_FS_REACTION_SHIFT)
239 #define VMON_TRK1_UV_FS_REACTION_FS0B (0x1 << VMON_TRK1_UV_FS_REACTION_SHIFT)
240 #define VMON_TRK1_UV_FS_REACTION_RSTB_FS0B (0x2 << VMON_TRK1_UV_FS_REACTION_SHIFT)
246 #define WD_ERR_LIMIT_MASK (0x3 << WD_ERR_LIMIT_SHIFT)
247 #define WD_ERR_LIMIT_8 (0x0 << WD_ERR_LIMIT_SHIFT)
248 #define WD_ERR_LIMIT_6 (0x1 << WD_ERR_LIMIT_SHIFT)
249 #define WD_ERR_LIMIT_4 (0x2 << WD_ERR_LIMIT_SHIFT)
250 #define WD_ERR_LIMIT_2 (0x3 << WD_ERR_LIMIT_SHIFT)
254 #define WD_RFR_LIMIT_MASK (0x3 << WD_RFR_LIMIT_SHIFT)
255 #define WD_RFR_LIMIT_6 (0x0 << WD_RFR_LIMIT_SHIFT)
256 #define WD_RFR_LIMIT_4 (0x1 << WD_RFR_LIMIT_SHIFT)
257 #define WD_RFR_LIMIT_2 (0x2 << WD_RFR_LIMIT_SHIFT)
258 #define WD_RFR_LIMIT_1 (0x3 << WD_RFR_LIMIT_SHIFT)
262 #define WD_FS_REACTION_MASK (0x3 << WD_FS_REACTION_SHIFT)
263 #define WD_FS_REACTION_NO_ACTION (0x0 << WD_FS_REACTION_SHIFT)
264 #define WD_FS_REACTION_FS0B (0x1 << WD_FS_REACTION_SHIFT)
265 #define WD_FS_REACTION_RSTB_FS0B (0x2 << WD_FS_REACTION_SHIFT)
269 #define WD_RFR_CNT_MASK (0x7 << WD_RFR_CNT_SHIFT)
270 #define WD_RFR_CNT(n) ((n) & (0x7 << WD_RFR_CNT_SHIFT))
273 #define WD_ERR_CNT_SHIFT (0)
274 #define WD_ERR_CNT_MASK (0xf << WD_ERR_CNT_SHIFT)
276 (((n) & (0x7 << WD_RFR_CNT_SHIFT)) > 11) ? (11) : (((n) & (0x7 << WD_RFR_CNT_SHIFT)))
282 #define FCCU_CFG_MASK (0x7 << FCCU_CFG_SHIFT)
283 #define FCCU_CFG_NO_MONITORING (0x0 << FCCU_CFG_SHIFT)
284 #define FCCU_CFG_FCCU1_FCCU2_PAIR (0x1 << FCCU_CFG_SHIFT)
285 #define FCCU_CFG_FCCU1_FCCU2_SINGLE (0x2 << FCCU_CFG_SHIFT)
286 #define FCCU_CFG_FCCU1_ONLY (0x3 << FCCU_CFG_SHIFT)
287 #define FCCU_CFG_FCCU2_ONLY (0x4 << FCCU_CFG_SHIFT)
288 #define FCCU_CFG_FCCU1_FCCU2_PWM (0x5 << FCCU_CFG_SHIFT)
289 #define FCCU_CFG_FCCU1_PWM_FCCU2_SINGLE (0x6 << FCCU_CFG_SHIFT)
290 #define FCCU_CFG_FCCU2_PWM_FCCU1_SINGLE (0x7 << FCCU_CFG_SHIFT)
294 #define FCCU12_FLT_POL_MASK (0x1 << FCCU12_FLT_POL_SHIFT)
295 #define FCCU12_FLT_POL_FCCU1_0_FCCU2_1_IS_FAULT (0x0 << FCCU12_FLT_POL_SHIFT)
296 #define FCCU12_FLT_POL_FCCU1_1_FCCU2_0_IS_FAULT (0x1 << FCCU12_FLT_POL_SHIFT)
300 #define FCCU1_FLT_POL_MASK (0x1 << FCCU1_FLT_POL_SHIFT)
301 #define FCCU1_FLT_POL_LOW (0x0 << FCCU1_FLT_POL_SHIFT)
302 #define FCCU1_FLT_POL_HIGH (0x1 << FCCU1_FLT_POL_SHIFT)
306 #define FCCU2_FLT_POL_MASK (0x1 << FCCU2_FLT_POL_SHIFT)
307 #define FCCU2_FLT_POL_LOW (0x0 << FCCU2_FLT_POL_SHIFT)
308 #define FCCU2_FLT_POL_HIGH (0x1 << FCCU2_FLT_POL_SHIFT)
312 #define FCCU12_FS_REACTION_MASK (0x1 << FCCU12_FS_REACTION_SHIFT)
317 #define FCCU1_FS_REACTION_MASK (0x1 << FCCU1_FS_REACTION_SHIFT)
322 #define FCCU2_FS_REACTION_MASK (0x1 << FCCU2_FS_REACTION_SHIFT)
327 #define ERRMON_FLT_POLARITY_MASK (0x1 << ERRMON_FLT_POLARITY_SHIFT)
328 #define ERRMON_FLT_POLARITY_LOW (0x0 << ERRMON_FLT_POLARITY_SHIFT)
329 #define ERRMON_FLT_POLARITY_HIGH (0x1 << ERRMON_FLT_POLARITY_SHIFT)
333 #define ERRMON_ACK_TIME_MASK (0x3 << ERRMON_ACK_TIME_SHIFT)
334 #define ERRMON_ACK_TIME_1MS (0x0 << ERRMON_ACK_TIME_SHIFT)
335 #define ERRMON_ACK_TIME_8MS (0x1 << ERRMON_ACK_TIME_SHIFT)
336 #define ERRMON_ACK_TIME_16MS (0x2 << ERRMON_ACK_TIME_SHIFT)
337 #define ERRMON_ACK_TIME_32MS (0x3 << ERRMON_ACK_TIME_SHIFT)
341 #define ERRMON_FS_REACTION_MASK (0x1 << FCCU2_FS_REACTION_SHIFT)
345 #define FCCU12_FILT_SHIFT (0)
346 #define FCCU12_FILT_MASK (0x3 << FCCU12_FILT_SHIFT)
347 #define FCCU12_FILT_3US (0x0 << FCCU12_FILT_SHIFT)
348 #define FCCU12_FILT_6US (0x1 << FCCU12_FILT_SHIFT)
349 #define FCCU12_FILT_10US (0x2 << FCCU12_FILT_SHIFT)
350 #define FCCU12_FILT_20US (0x3 << FCCU12_FILT_SHIFT)
356 #define FLT_ERR_CNT_LIMIT_MASK (0x3 << FLT_ERR_CNT_LIMIT_SHIFT)
357 #define FLT_ERR_CNT_LIMIT_2 (0x0 << FLT_ERR_CNT_LIMIT_SHIFT)
358 #define FLT_ERR_CNT_LIMIT_6 (0x1 << FLT_ERR_CNT_LIMIT_SHIFT)
359 #define FLT_ERR_CNT_LIMIT_8 (0x2 << FLT_ERR_CNT_LIMIT_SHIFT)
360 #define FLT_ERR_CNT_LIMIT_12 (0x3 << FLT_ERR_CNT_LIMIT_SHIFT)
364 #define FLT_ERR_REACTION_MASK (0x3 << FLT_ERR_REACTION_SHIFT)
365 #define FLT_ERR_REACTION_NO_EFFECT (0x0 << FLT_ERR_REACTION_SHIFT)
366 #define FLT_ERR_REACTION_FS0B (0x1 << FLT_ERR_REACTION_SHIFT)
367 #define FLT_ERR_REACTION_RSTB_FS0B (0x2 << FLT_ERR_REACTION_SHIFT)
371 #define RSTB_DUR_MASK (0x1 << RSTB_DUR_SHIFT)
373 #define RSTB_DUR_10MS (0)
377 #define BACKUP_SAFETY_PATH_FS0B_MASK (0x1 << BACKUP_SAFETY_PATH_FS0B_SHIFT)
382 #define BACKUP_SAFETY_PATH_FS1B_MASK (0x1 << BACKUP_SAFETY_PATH_FS1B_SHIFT)
387 #define CLK_MON_DIS_MASK (0x1 << CLK_MON_DIS_SHIFT)
392 #define DIS8S_MASK (0x1 << DIS8S_SHIFT)
396 #define FLT_ERR_CNT_SHIFT (0)
397 #define FLT_ERR_CNT_MASK (0xf << FLT_ERR_CNT_SHIFT)
399 ((n & (0x7 << FLT_ERR_CNT_SHIFT)) > 12) ? (12) : ((n & (0x7 << FLT_ERR_CNT_SHIFT)))
405 #define WDW_PERIOD_MASK (0xf << WDW_PERIOD_SHIFT)
406 #define WDW_PERIOD_DISABLE (0x0 << WDW_PERIOD_SHIFT)
407 #define WDW_PERIOD_1MS (0x1 << WDW_PERIOD_SHIFT)
408 #define WDW_PERIOD_2MS (0x2 << WDW_PERIOD_SHIFT)
409 #define WDW_PERIOD_3MS (0x3 << WDW_PERIOD_SHIFT)
410 #define WDW_PERIOD_4MS (0x4 << WDW_PERIOD_SHIFT)
411 #define WDW_PERIOD_6MS (0x5 << WDW_PERIOD_SHIFT)
412 #define WDW_PERIOD_8MS (0x6 << WDW_PERIOD_SHIFT)
413 #define WDW_PERIOD_12MS (0x7 << WDW_PERIOD_SHIFT)
414 #define WDW_PERIOD_16MS (0x8 << WDW_PERIOD_SHIFT)
415 #define WDW_PERIOD_24MS (0x9 << WDW_PERIOD_SHIFT)
416 #define WDW_PERIOD_32MS (0xa << WDW_PERIOD_SHIFT)
417 #define WDW_PERIOD_64MS (0xb << WDW_PERIOD_SHIFT)
418 #define WDW_PERIOD_128MS (0xc << WDW_PERIOD_SHIFT)
419 #define WDW_PERIOD_256MS (0xd << WDW_PERIOD_SHIFT)
420 #define WDW_PERIOD_512MS (0xe << WDW_PERIOD_SHIFT)
421 #define WDW_PERIOD_1024MS (0xf << WDW_PERIOD_SHIFT)
425 #define WDW_DC_MASK (0x7 << WDW_DC_SHIFT)
426 #define WDW_DC_31_68 (0x0 << WDW_PERIOD_SHIFT)
427 #define WDW_DC_37_62 (0x1 << WDW_PERIOD_SHIFT)
428 #define WDW_DC_50_50 (0x2 << WDW_PERIOD_SHIFT)
429 #define WDW_DC_62_37 (0x3 << WDW_PERIOD_SHIFT)
430 #define WDW_DC_68_31 (0x4 << WDW_PERIOD_SHIFT)
433 #define WDW_RECOVERY_SHIFT (0)
434 #define WDW_RECOVERY_MASK (0xf << WDW_RECOVERY_SHIFT)
435 #define WDW_RECOVERY_DISABLE (0x0 << WDW_RECOVERY_SHIFT)
436 #define WDW_RECOVERY_1MS (0x1 << WDW_RECOVERY_SHIFT)
437 #define WDW_RECOVERY_2MS (0x2 << WDW_RECOVERY_SHIFT)
438 #define WDW_RECOVERY_3MS (0x3 << WDW_RECOVERY_SHIFT)
439 #define WDW_RECOVERY_4MS (0x4 << WDW_RECOVERY_SHIFT)
440 #define WDW_RECOVERY_6MS (0x5 << WDW_RECOVERY_SHIFT)
441 #define WDW_RECOVERY_8MS (0x6 << WDW_RECOVERY_SHIFT)
442 #define WDW_RECOVERY_12MS (0x7 << WDW_RECOVERY_SHIFT)
443 #define WDW_RECOVERY_16MS (0x8 << WDW_RECOVERY_SHIFT)
444 #define WDW_RECOVERY_24MS (0x9 << WDW_RECOVERY_SHIFT)
445 #define WDW_RECOVERY_32MS (0xa << WDW_RECOVERY_SHIFT)
446 #define WDW_RECOVERY_64MS (0xb << WDW_RECOVERY_SHIFT)
447 #define WDW_RECOVERY_128MS (0xc << WDW_RECOVERY_SHIFT)
448 #define WDW_RECOVERY_256MS (0xd << WDW_RECOVERY_SHIFT)
449 #define WDW_RECOVERY_512MS (0xe << WDW_RECOVERY_SHIFT)
450 #define WDW_RECOVERY_1024MS (0xf << WDW_RECOVERY_SHIFT)
456 #define BAD_WD_DATA_MASK (0x1 << BAD_WD_DATA_SHIFT)
461 #define BAD_WD_TIMING_MASK (0x1 << BAD_WD_TIMING_SHIFT)
466 #define ABIST1_PASS_MASK (0x1 << ABIST1_PASS_SHIFT)
471 #define ABIST2_PASS_MASK (0x1 << ABIST2_PASS_SHIFT)
476 #define ABIST2_DONE_MASK (0x1 << ABIST2_DONE_SHIFT)
481 #define SPI_FS_CLK_MASK (0x1 << SPI_FS_CLK_SHIFT)
486 #define SPI_FS_REQ_MASK (0x1 << SPI_FS_REQ_SHIFT)
491 #define SPI_FS_CRC_MASK (0x1 << SPI_FS_CRC_SHIFT)
496 #define FS_OSC_DRIFT_MASK (0x1 << FS_OSC_DRIFT_SHIFT)
500 #define LBIST_STATUS_SHIFT (0)
501 #define LBIST_STATUS_MASK (0x3 << LBIST_STATUS_SHIFT)
503 #define LBIST_STATUS_FAIL (0x0 << LBIST_STATUS_SHIFT)
504 #define LBIST_STATUS_BYPASSED (0x1 << LBIST_STATUS_SHIFT)
505 #define LBIST_STATUS_FAIL2 (0x2 << LBIST_STATUS_SHIFT)
506 #define LBIST_STATUS_OK (0x3 << LBIST_STATUS_SHIFT)
512 #define EXIT_DBG_MODE_MASK (0x1 << EXIT_DBG_MODE_SHIFT)
517 #define DBG_MODE_MASK (0x1 << DBG_MODE_SHIFT)
522 #define OTP_CORRUPT_MASK (0x1 << OTP_CORRUPT_SHIFT)
527 #define REG_CORRUPT_MASK (0x1 << REG_CORRUPT_SHIFT)
531 #define FS_STATES_SHIFT (0)
532 #define FS_STATES_MASK (0x1f << FS_STATES_SHIFT)
534 #define FS_STATES_DEBUG_ENTRY (0x4 << FS_STATES_SHIFT)
535 #define FS_STATES_ENABLE_MON (0x6 << FS_STATES_SHIFT)
536 #define FS_STATES_RSTB_RELEASE (0x8 << FS_STATES_SHIFT)
537 #define FS_STATES_INIT_FS (0x9 << FS_STATES_SHIFT)
538 #define FS_STATES_SAFETY_OUT_NOT (0xa << FS_STATES_SHIFT)
539 #define FS_STATES_NORMAL (0xb << FS_STATES_SHIFT)
545 #define FS_COM_G_MASK (0x1 << FS_COM_G_SHIFT)
550 #define FS_WD_G_MASK (0x1 << FS_WD_G_SHIFT)
555 #define FS_IO_G_MASK (0x1 << FS_IO_G_SHIFT)
560 #define FS_REG_OVUV_G_MASK (0x1 << FS_REG_OVUV_G_SHIFT)
565 #define FS_BIST_G_MASK (0x1 << FS_BIST_G_SHIFT)
572 #define FS_GOTO_INIT_MASK (0x1 << FS_GOTO_INIT_SHIFT)
578 #define BAD_WD_M (0x1 << 5)