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/Zephyr-latest/doc/connectivity/networking/
Dzephyr_netstack_overview.svg1 <?xml version="1.0" encoding="UTF-8" standalone="no"?>
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Dzephyr_netstack_overview-tx_sequence.svg1 <?xml version="1.0" encoding="UTF-8" standalone="no"?>
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Dzephyr_netstack_overview-rx_sequence.svg1 <?xml version="1.0" encoding="UTF-8" standalone="no"?>
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/Zephyr-latest/boards/native/doc/
Dlayering.svg1 <?xml version="1.0" encoding="UTF-8" standalone="no"?>
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DPort_vs_QEMU_vs.svg1 <?xml version="1.0" encoding="UTF-8" standalone="no"?>
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DZephyr_and_bsim.svg1 <?xml version="1.0" encoding="UTF-8" standalone="no"?>
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Dlayering_natsim.svg1 <?xml version="1.0" encoding="UTF-8" standalone="no"?>
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/Zephyr-latest/soc/nxp/s32/s32k3/
Dpmc.c4 * SPDX-License-Identifier: Apache-2.0
15 #define PMC_LVSC_HVDAF(v) FIELD_PREP(PMC_LVSC_HVDAF_MASK, (v)) argument
17 #define PMC_LVSC_HVDBF(v) FIELD_PREP(PMC_LVSC_HVDBF_MASK, (v)) argument
19 #define PMC_LVSC_HVD25F(v) FIELD_PREP(PMC_LVSC_HVD25F_MASK, (v)) argument
21 #define PMC_LVSC_HVD11F(v) FIELD_PREP(PMC_LVSC_HVD11F_MASK, (v)) argument
23 #define PMC_LVSC_LVD5AF(v) FIELD_PREP(PMC_LVSC_LVD5AF_MASK, (v)) argument
25 #define PMC_LVSC_LVD15F(v) FIELD_PREP(PMC_LVSC_LVD15F_MASK, (v)) argument
27 #define PMC_LVSC_HVDAS(v) FIELD_PREP(PMC_LVSC_HVDAS_MASK, (v)) argument
29 #define PMC_LVSC_HVDBS(v) FIELD_PREP(PMC_LVSC_HVDBS_MASK, (v)) argument
31 #define PMC_LVSC_HVD25S(v) FIELD_PREP(PMC_LVSC_HVD25S_MASK, (v)) argument
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Dpinctrl_soc.h2 * Copyright 2022-2024 NXP
4 * SPDX-License-Identifier: Apache-2.0
10 #include <zephyr/dt-bindings/pinctrl/nxp-s32-pinctrl.h>
17 #define SIUL2_MSCR_SSS(v) FIELD_PREP(SIUL2_MSCR_SSS_MASK, (v)) argument
19 #define SIUL2_MSCR_SMC(v) FIELD_PREP(SIUL2_MSCR_SMC_MASK, (v)) argument
21 #define SIUL2_MSCR_IFE(v) FIELD_PREP(SIUL2_MSCR_IFE_MASK, (v)) argument
23 #define SIUL2_MSCR_DSE(v) FIELD_PREP(SIUL2_MSCR_DSE_MASK, (v)) argument
25 #define SIUL2_MSCR_PUS(v) FIELD_PREP(SIUL2_MSCR_PUS_MASK, (v)) argument
27 #define SIUL2_MSCR_PUE(v) FIELD_PREP(SIUL2_MSCR_PUE_MASK, (v)) argument
29 #define SIUL2_MSCR_SRC(v) FIELD_PREP(SIUL2_MSCR_SRC_MASK, (v)) argument
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/Zephyr-latest/scripts/coccinelle/
Dunsigned_suffix.cocci5 // SPDX-License-Identifier: Apache-2.0
13 … unsigned short, unsigned int, uint8_t, uint16_t, uint32_t, uint64_t, u8_t, u16_t, u32_t, u64_t} v;
19 v = C@p
21 v == C@p
23 v != C@p
25 v <= C@p
27 v >= C@p
29 v += C@p
31 v -= C@p
33 v * C@p
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Dreserved_names.cocci2 // https://gitlab.com/MISRA/MISRA-C/MISRA-C-2012/Example-Suite/-/blob/master/R_21_02.c
7 // SPDX-License-Identifier: Apache-2.0
16 identifier t, v;
21 struct t *v@p;
23 struct t v@p;
25 union t v@p;
27 T v@p;
29 T *v@p;
31 struct t *v@p = E;
33 struct t v@p = E;
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Dsame_identifier.cocci2 // https://gitlab.com/MISRA/MISRA-C/MISRA-C-2012/Example-Suite/-/blob/master/R_05_07.c
7 // SPDX-License-Identifier: Apache-2.0
16 identifier t, v;
19 struct t *v@p;
21 struct t v@p;
23 union t v@p;
28 v << common_case.v;
32 msg = "WARNING: Violation to rule 5.7 (Tag name should be unique) tag: {}".format(v)
33 if t == v:
38 identifier v;
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Dboolean.cocci2 // https://gitlab.com/MISRA/MISRA-C/MISRA-C-2012/Example-Suite/-/blob/master/R_14_04.c
7 // SPDX-License-Identifier: Apache-2.0
16 identifier function, v;
22 T1 function(P1, T2 v, P2) {...}
24 T1 function(P1, T2 *v, P2) {...}
29 v << rule1_base.v;
36 identifier rule1_base.v;
40 while (v@p) {...}
42 if (v@p) {...}
53 identifier v;
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/Zephyr-latest/drivers/clock_control/
Dclock_stm32_ll_common.h5 * SPDX-License-Identifier: Apache-2.0
18 #define z_pllm(v) LL_RCC_PLLM_DIV_ ## v argument
19 #define pllm(v) z_pllm(v) argument
21 #define z_pllp(v) LL_RCC_PLLP_DIV_ ## v argument
22 #define pllp(v) z_pllp(v) argument
24 #define z_pllq(v) LL_RCC_PLLQ_DIV_ ## v argument
25 #define pllq(v) z_pllq(v) argument
27 #define z_pllr(v) LL_RCC_PLLR_DIV_ ## v argument
28 #define pllr(v) z_pllr(v) argument
32 #define z_plli2s_m(v) LL_RCC_PLLI2SM_DIV_ ## v argument
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/Zephyr-latest/soc/nxp/s32/s32ze/
Dpinctrl_soc.h2 * Copyright 2022-2024 NXP
4 * SPDX-License-Identifier: Apache-2.0
10 #include <zephyr/dt-bindings/pinctrl/nxp-s32-pinctrl.h>
17 #define SIUL2_MSCR_SSS(v) FIELD_PREP(SIUL2_MSCR_SSS_MASK, (v)) argument
19 #define SIUL2_MSCR_SMC(v) FIELD_PREP(SIUL2_MSCR_SMC_MASK, (v)) argument
21 #define SIUL2_MSCR_TRC(v) FIELD_PREP(SIUL2_MSCR_TRC_MASK, (v)) argument
23 #define SIUL2_MSCR_RCVR(v) FIELD_PREP(SIUL2_MSCR_RCVR_MASK, (v)) argument
25 #define SIUL2_MSCR_CREF(v) FIELD_PREP(SIUL2_MSCR_CREF_MASK, (v)) argument
27 #define SIUL2_MSCR_PUS(v) FIELD_PREP(SIUL2_MSCR_PUS_MASK, (v)) argument
29 #define SIUL2_MSCR_PUE(v) FIELD_PREP(SIUL2_MSCR_PUE_MASK, (v)) argument
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/Zephyr-latest/dts/bindings/pinctrl/
Dnxp,imx8m-pinctrl.yaml2 # SPDX-License-Identifier: Apache-2.0
15 drive-strength = "40-ohm";
16 slew-rate = "slow";
26 input-schmitt-enable: HYS=1
27 bias-pull-up: PUE=1
28 drive-open-drain: ODE=1
29 slew-rate: SRE=<enum_idx>
30 drive-strength: DSE=<enum_idx>
31 input-enable: SION=1 (in SW_MUX_CTL_PAD register)
39 SRE=<slew-rate>,
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/Zephyr-latest/include/zephyr/arch/arc/asm-compat/
Dasm-macro-32-bit-mwdt.h1 /* SPDX-License-Identifier: Apache-2.0 */
5 * ALU/Memory instructions pseudo-mnemonics for ARCv2 and ARC32 ISA
47 .macro ADDR, d, s, v
48 add\&$suffix d, s, v
51 .macro ADD2R, d, s, v
52 add2\&$suffix d, s, v
55 .macro ADD3R, d, s, v
56 add3 d, s, v
59 .macro SUBR, d, s, v
60 sub d, s, v
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Dasm-macro-64-bit-mwdt.h1 /* SPDX-License-Identifier: Apache-2.0 */
5 * ALU/Memory instructions pseudo-mnemonics for ARC64 ISA
47 .macro ADDR, d, s, v
48 addl\&$suffix d, s, v
51 .macro ADD2R, d, s, v
52 add2l\&$suffix d, s, v
55 .macro ADD3R, d, s, v
56 add3l d, s, v
59 .macro SUBR, d, s, v
60 subl d, s, v
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Dasm-macro-32-bit-gnu.h1 /* SPDX-License-Identifier: Apache-2.0 */
7 * ALU/Memory instructions pseudo-mnemonics for ARCv2 and ARC32 ISA
50 .macro ADDR\cc d, s, v
51 add\cc \d, \s, \v
56 .macro ADD2R\cc d, s, v
57 add2\cc \d, \s, \v
61 .macro ADD3R d, s, v
62 add3 \d, \s, \v
65 .macro SUBR d, s, v
66 sub \d, \s, \v
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Dasm-macro-64-bit-gnu.h1 /* SPDX-License-Identifier: Apache-2.0 */
7 * pseudo-mnemonics for ALU/Memory instructions for ARC64 ISA
62 .macro ADDR\cc d, s, v
63 addl\cc \d, \s, \v
68 .macro ADD2R\cc d, s, v
69 add2l\cc \d, \s, \v
73 .macro ADD3R d, s, v
74 add3l \d, \s, \v
77 .macro SUBR d, s, v
78 subl \d, \s, \v
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/Zephyr-latest/samples/subsys/sip_svc/
DREADME.rst1 .. zephyr:code-sample:: sip_svc
25 .. zephyr-app-commands::
26 :zephyr-app: samples/subsys/sip_svc
36 .. code-block:: console
38 *** Booting Zephyr OS build zephyr-v3.3.0-2963-gb5ba49ae300e ***
39 Got response of transaction id 0x00 and voltage is 0.846878v
40 Got response of transaction id 0x01 and voltage is 0.858170v
41 Got response of transaction id 0x02 and voltage is 0.860168v
42 Got response of transaction id 0x03 and voltage is 0.846832v
43 Got response of transaction id 0x04 and voltage is 0.858337v
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/Zephyr-latest/drivers/sensor/tdk/icm42605/
Dicm42605_setup.c4 * SPDX-License-Identifier: Apache-2.0
19 const struct icm42605_config *cfg = dev->config; in icm42605_set_fs()
23 result = inv_spi_read(&cfg->spi, REG_ACCEL_CONFIG0, &databuf, 1); in icm42605_set_fs()
31 result = inv_spi_single_write(&cfg->spi, REG_ACCEL_CONFIG0, &databuf); in icm42605_set_fs()
33 result = inv_spi_read(&cfg->spi, REG_GYRO_CONFIG0, &databuf, 1); in icm42605_set_fs()
42 result = inv_spi_single_write(&cfg->spi, REG_GYRO_CONFIG0, &databuf); in icm42605_set_fs()
53 const struct icm42605_config *cfg = dev->config; in icm42605_set_odr()
60 return -ENOTSUP; in icm42605_set_odr()
63 result = inv_spi_read(&cfg->spi, REG_ACCEL_CONFIG0, &databuf, 1); in icm42605_set_odr()
99 result = inv_spi_single_write(&cfg->spi, REG_ACCEL_CONFIG0, &databuf); in icm42605_set_odr()
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/Zephyr-latest/soc/nxp/s32/common/
Dmc_me.c4 * SPDX-License-Identifier: Apache-2.0
17 #define MC_ME_CTL_KEY_KEY(v) FIELD_PREP(MC_ME_CTL_KEY_KEY_MASK, (v)) argument
21 #define MC_ME_MODE_CONF_DEST_RST(v) FIELD_PREP(MC_ME_MODE_CONF_DEST_RST_MASK, (v)) argument
23 #define MC_ME_MODE_CONF_FUNC_RST(v) FIELD_PREP(MC_ME_MODE_CONF_FUNC_RST_MASK, (v)) argument
25 #define MC_ME_MODE_CONF_STANDBY(v) FIELD_PREP(MC_ME_MODE_CONF_STANDBY_MASK, (v)) argument
29 #define MC_ME_MODE_UPD_MODE_UPD(v) FIELD_PREP(MC_ME_MODE_UPD_MODE_UPD_MASK, (v)) argument
33 #define MC_ME_MODE_STAT_PREV_MODE(v) FIELD_PREP(MC_ME_MODE_STAT_PREV_MODE_MASK, (v)) argument
37 #define MC_ME_MAIN_COREID_CIDX(v) FIELD_PREP(MC_ME_MAIN_COREID_CIDX_MASK, (v)) argument
39 #define MC_ME_MAIN_COREID_PIDX(v) FIELD_PREP(MC_ME_MAIN_COREID_PIDX_MASK, (v)) argument
43 #define MC_ME_PRTN_PCONF_PCE(v) FIELD_PREP(MC_ME_PRTN_PCONF_PCE_MASK, (v)) argument
[all …]
Dmc_rgm.c4 * SPDX-License-Identifier: Apache-2.0
15 #define MC_RGM_DES_F_POR(v) FIELD_PREP(MC_RGM_DES_F_POR_MASK, (v)) argument
19 #define MC_RGM_FES_F_EXR(v) FIELD_PREP(MC_RGM_FES_F_EXR_MASK, (v)) argument
27 #define MC_RGM_FREC_FREC(v) FIELD_PREP(MC_RGM_FREC_FREC_MASK, (v)) argument
31 #define MC_RGM_FRET_FRET(v) FIELD_PREP(MC_RGM_FRET_FRET_MASK, (v)) argument
35 #define MC_RGM_DRET_DRET(v) FIELD_PREP(MC_RGM_DRET_DRET_MASK, (v)) argument
39 #define MC_RGM_ERCTRL_ERASSERT(v) FIELD_PREP(MC_RGM_ERCTRL_ERASSERT_MASK, (v)) argument
43 #define MC_RGM_RDSS_DES_RES(v) FIELD_PREP(MC_RGM_RDSS_DES_RES_MASK, (v)) argument
45 #define MC_RGM_RDSS_FES_RES(v) FIELD_PREP(MC_RGM_RDSS_FES_RES_MASK, (v)) argument
49 #define MC_RGM_FRENTC_FRET_EN(v) FIELD_PREP(MC_RGM_FRENTC_FRET_EN_MASK, (v)) argument
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/Zephyr-latest/drivers/charger/
Dcharger_bq24190.c4 * SPDX-License-Identifier: Apache-2.0
38 const struct bq24190_config *const config = dev->config; in bq24190_register_reset()
42 ret = i2c_reg_update_byte_dt(&config->i2c, BQ24190_REG_POC, BQ24190_REG_POC_RESET_MASK, in bq24190_register_reset()
54 ret = i2c_reg_read_byte_dt(&config->i2c, BQ24190_REG_POC, &val); in bq24190_register_reset()
64 } while (--limit); in bq24190_register_reset()
66 return -EIO; in bq24190_register_reset()
72 const struct bq24190_config *const config = dev->config; in bq24190_charger_get_charge_type()
73 uint8_t v; in bq24190_charger_get_charge_type() local
78 ret = i2c_reg_read_byte_dt(&config->i2c, BQ24190_REG_POC, &v); in bq24190_charger_get_charge_type()
83 v = FIELD_GET(BQ24190_REG_POC_CHG_CONFIG_MASK, v); in bq24190_charger_get_charge_type()
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